[llvm] [ISel] Introduce llvm.clmul intrinsic (PR #168731)

[Craig Topper via llvm-commits]

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@@ -221,6 +223,7 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
   case ISD::VP_SDIV:
   case ISD::VP_SREM:     Res = PromoteIntRes_SExtIntBinOp(N); break;
 
+  case ISD::CLMUL:
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topperc wrote:

Why does this need to call PromoteIntRes_ZExtIntBinOp? The upper bits past the original type should't matter.

https://github.com/llvm/llvm-project/pull/168731