[llvm] [ISel] Introduce llvm.clmul intrinsic (PR #168731)

[Craig Topper via llvm-commits]

================
@@ -11420,6 +11420,31 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
   if (SDValue AVG = foldShiftToAvg(N, DL))
     return AVG;
 
+  SDValue Y;
+  if (VT.getScalarSizeInBits() % 2 == 0) {
+    // Fold clmul(zext(x), zext(y)) >> (BW - 1 | BW) -> clmul(r|h)(x, y).
+    unsigned HalfBW = VT.getScalarSizeInBits() / 2;
+    if (sd_match(N0, m_Clmul(m_ZExt(m_Value(X)), m_ZExt(m_Value(Y)))) &&
+        X.getScalarValueSizeInBits() == HalfBW &&
+        Y.getScalarValueSizeInBits() == HalfBW) {
+      if (sd_match(N1, m_SpecificInt(HalfBW - 1)))
+        return DAG.getNode(
+            ISD::ZERO_EXTEND, DL, VT,
+            DAG.getNode(ISD::CLMULR, DL, X.getValueType(), X, Y));
+      if (sd_match(N1, m_SpecificInt(HalfBW)))
+        return DAG.getNode(
+            ISD::ZERO_EXTEND, DL, VT,
+            DAG.getNode(ISD::CLMULH, DL, X.getValueType(), X, Y));
+    }
+  }
+
+  // Fold bitreverse(clmul(bitreverse(x), bitreverse(y))) >> 1 ->
+  // clmulh(x, y).
+  if (sd_match(N0, m_BitReverse(m_Clmul(m_BitReverse(m_Value(X)),
+                                        m_BitReverse(m_Value(Y))))) &&
+      sd_match(N1, m_SpecificInt(1)))
----------------
topperc wrote:

```suggestion
  if (N1C && N1C->getZExtValue() == 1 &&
      sd_match(N0, m_BitReverse(m_Clmul(m_BitReverse(m_Value(X)),
                                        m_BitReverse(m_Value(Y)))))
```

https://github.com/llvm/llvm-project/pull/168731