[llvm] Add LoopVectorizer support for `llvm.vector.partial.reduce.fadd` (PR #163975)
Damian Heaton via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 11 03:50:50 PST 2025
https://github.com/dheaton-arm updated https://github.com/llvm/llvm-project/pull/163975
>From 1a84521b3ffabcb9462abb402f70be00ad569691 Mon Sep 17 00:00:00 2001
From: Damian Heaton <Damian.Heaton at arm.com>
Date: Wed, 8 Oct 2025 13:48:01 +0000
Subject: [PATCH 1/9] Add LoopVectoriser support for
`llvm.vector.partial.reduce.fadd`
---
.../llvm/Analysis/TargetTransformInfo.h | 7 +-
llvm/lib/Analysis/TargetTransformInfo.cpp | 2 +
.../AArch64/AArch64TargetTransformInfo.cpp | 6 +-
.../Transforms/Vectorize/LoopVectorize.cpp | 18 +-
.../AArch64/partial-reduce-fdot-product.ll | 203 ++++++++++++++++++
5 files changed, 228 insertions(+), 8 deletions(-)
create mode 100644 llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fdot-product.ll
diff --git a/llvm/include/llvm/Analysis/TargetTransformInfo.h b/llvm/include/llvm/Analysis/TargetTransformInfo.h
index e24e22da5681b..7f4ee11150eb2 100644
--- a/llvm/include/llvm/Analysis/TargetTransformInfo.h
+++ b/llvm/include/llvm/Analysis/TargetTransformInfo.h
@@ -275,7 +275,12 @@ class TargetTransformInfoImplBase;
/// for IR-level transformations.
class TargetTransformInfo {
public:
- enum PartialReductionExtendKind { PR_None, PR_SignExtend, PR_ZeroExtend };
+ enum PartialReductionExtendKind {
+ PR_None,
+ PR_SignExtend,
+ PR_ZeroExtend,
+ PR_FPExtend
+ };
/// Get the kind of extension that an instruction represents.
LLVM_ABI static PartialReductionExtendKind
diff --git a/llvm/lib/Analysis/TargetTransformInfo.cpp b/llvm/lib/Analysis/TargetTransformInfo.cpp
index c529d87502acd..497f937b35cbb 100644
--- a/llvm/lib/Analysis/TargetTransformInfo.cpp
+++ b/llvm/lib/Analysis/TargetTransformInfo.cpp
@@ -1022,6 +1022,8 @@ TargetTransformInfo::getPartialReductionExtendKind(
return PR_ZeroExtend;
case Instruction::CastOps::SExt:
return PR_SignExtend;
+ case Instruction::CastOps::FPExt:
+ return PR_FPExtend;
default:
return PR_None;
}
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
index 3a5f1499f9d2d..9c58dc5e0132f 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -5798,7 +5798,8 @@ InstructionCost AArch64TTIImpl::getPartialReductionCost(
(!ST->isNeonAvailable() || !ST->hasDotProd()))
return Invalid;
- if ((Opcode != Instruction::Add && Opcode != Instruction::Sub) ||
+ if ((Opcode != Instruction::Add && Opcode != Instruction::Sub &&
+ Opcode != Instruction::FAdd) ||
OpAExtend == TTI::PR_None)
return Invalid;
@@ -5808,7 +5809,8 @@ InstructionCost AArch64TTIImpl::getPartialReductionCost(
// We only support multiply binary operations for now, and for muls we
// require the types being extended to be the same.
- if (BinOp && (*BinOp != Instruction::Mul || InputTypeA != InputTypeB))
+ if (BinOp && ((*BinOp != Instruction::Mul && *BinOp != Instruction::FMul) ||
+ InputTypeA != InputTypeB))
return Invalid;
bool IsUSDot = OpBExtend != TTI::PR_None && OpAExtend != OpBExtend;
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index 62b68232925d9..c5dbc464fb826 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -5387,14 +5387,16 @@ LoopVectorizationCostModel::getReductionPatternCost(Instruction *I,
// it is not we return an invalid cost specifying the orignal cost method
// should be used.
Instruction *RetI = I;
- if (match(RetI, m_ZExtOrSExt(m_Value()))) {
+ if (match(RetI, m_ZExtOrSExt(m_Value())) || match(RetI, m_FPExt(m_Value()))) {
if (!RetI->hasOneUser())
return std::nullopt;
RetI = RetI->user_back();
}
- if (match(RetI, m_OneUse(m_Mul(m_Value(), m_Value()))) &&
- RetI->user_back()->getOpcode() == Instruction::Add) {
+ if ((match(RetI, m_OneUse(m_Mul(m_Value(), m_Value()))) &&
+ RetI->user_back()->getOpcode() == Instruction::Add) ||
+ (match(RetI, m_OneUse(m_FMul(m_Value(), m_Value()))) &&
+ RetI->user_back()->getOpcode() == Instruction::FAdd)) {
RetI = RetI->user_back();
}
@@ -8120,7 +8122,8 @@ bool VPRecipeBuilder::getScaledReductions(
continue;
}
Value *ExtOp;
- if (!match(OpI, m_ZExtOrSExt(m_Value(ExtOp))))
+ if (!match(OpI, m_ZExtOrSExt(m_Value(ExtOp))) &&
+ !match(OpI, m_FPExt(m_Value(ExtOp))))
return false;
Exts[I] = cast<Instruction>(OpI);
@@ -8301,6 +8304,9 @@ VPRecipeBuilder::tryToCreatePartialReduction(VPInstruction *Reduction,
"all accumulators in chain must have same scale factor");
auto *ReductionI = Reduction->getUnderlyingInstr();
+ if (Reduction->getOpcode() == Instruction::FAdd &&
+ !ReductionI->hasAllowReassoc())
+ return nullptr;
if (Reduction->getOpcode() == Instruction::Sub) {
auto *const Zero = ConstantInt::get(ReductionI->getType(), 0);
SmallVector<VPValue *, 2> Ops;
@@ -8316,7 +8322,9 @@ VPRecipeBuilder::tryToCreatePartialReduction(VPInstruction *Reduction,
Cond = getBlockInMask(Builder.getInsertBlock());
return new VPReductionRecipe(
- RecurKind::Add, FastMathFlags(), ReductionI, Accumulator, BinOp, Cond,
+ Reduction->getOpcode() == Instruction::FAdd ? RecurKind::FAdd
+ : RecurKind::Add,
+ FastMathFlags(), ReductionI, Accumulator, BinOp, Cond,
RdxUnordered{/*VFScaleFactor=*/ScaleFactor}, ReductionI->getDebugLoc());
}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fdot-product.ll b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fdot-product.ll
new file mode 100644
index 0000000000000..e441ffb7dbc95
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fdot-product.ll
@@ -0,0 +1,203 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6
+; RUN: opt -passes=loop-vectorize -force-vector-interleave=1 -enable-epilogue-vectorization=false -mattr=+sve2p1,+dotprod -S < %s | FileCheck %s --check-prefixes=CHECK-INTERLEAVE1
+; RUN: opt -passes=loop-vectorize -enable-epilogue-vectorization=false -mattr=+sve2p1,+dotprod -S < %s | FileCheck %s --check-prefixes=CHECK-INTERLEAVED
+; RUN: opt -passes=loop-vectorize -force-vector-interleave=1 -vectorizer-maximize-bandwidth -enable-epilogue-vectorization=false -mattr=+sve2p1,+dotprod -S < %s | FileCheck %s --check-prefixes=CHECK-MAXBW
+
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64-none-unknown-elf"
+
+define float @fdotp(ptr %a, ptr %b) #0 {
+; CHECK-INTERLEAVE1-LABEL: define float @fdotp(
+; CHECK-INTERLEAVE1-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-INTERLEAVE1-NEXT: [[ENTRY:.*]]:
+; CHECK-INTERLEAVE1-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVE1-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP4]], 1
+; CHECK-INTERLEAVE1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK-INTERLEAVE1: [[VECTOR_PH]]:
+; CHECK-INTERLEAVE1-NEXT: [[TMP12:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVE1-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP12]], 2
+; CHECK-INTERLEAVE1-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
+; CHECK-INTERLEAVE1-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
+; CHECK-INTERLEAVE1-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-INTERLEAVE1: [[VECTOR_BODY]]:
+; CHECK-INTERLEAVE1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT1:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 2 x float> [ insertelement (<vscale x 2 x float> splat (float -0.000000e+00), float 0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[TMP9:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[TMP0:%.*]] = getelementptr half, ptr [[A]], i64 [[INDEX]]
+; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 2 x half>, ptr [[TMP0]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP5:%.*]] = fpext <vscale x 2 x half> [[WIDE_LOAD]] to <vscale x 2 x float>
+; CHECK-INTERLEAVE1-NEXT: [[TMP2:%.*]] = getelementptr half, ptr [[B]], i64 [[INDEX]]
+; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 2 x half>, ptr [[TMP2]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP13:%.*]] = fpext <vscale x 2 x half> [[WIDE_LOAD1]] to <vscale x 2 x float>
+; CHECK-INTERLEAVE1-NEXT: [[TMP8:%.*]] = fmul <vscale x 2 x float> [[TMP13]], [[TMP5]]
+; CHECK-INTERLEAVE1-NEXT: [[TMP9]] = fadd reassoc <vscale x 2 x float> [[TMP8]], [[VEC_PHI]]
+; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT1]] = add nuw i64 [[INDEX]], [[TMP3]]
+; CHECK-INTERLEAVE1-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT1]], [[N_VEC]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK-INTERLEAVE1: [[MIDDLE_BLOCK]]:
+; CHECK-INTERLEAVE1-NEXT: [[TMP11:%.*]] = call reassoc float @llvm.vector.reduce.fadd.nxv2f32(float -0.000000e+00, <vscale x 2 x float> [[TMP9]])
+; CHECK-INTERLEAVE1-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-INTERLEAVE1: [[SCALAR_PH]]:
+; CHECK-INTERLEAVE1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP11]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
+; CHECK-INTERLEAVE1-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-INTERLEAVE1: [[FOR_BODY]]:
+; CHECK-INTERLEAVE1-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[ACCUM:%.*]] = phi float [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[GEP_A:%.*]] = getelementptr half, ptr [[A]], i64 [[IV]]
+; CHECK-INTERLEAVE1-NEXT: [[LOAD_A:%.*]] = load half, ptr [[GEP_A]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[EXT_A:%.*]] = fpext half [[LOAD_A]] to float
+; CHECK-INTERLEAVE1-NEXT: [[GEP_B:%.*]] = getelementptr half, ptr [[B]], i64 [[IV]]
+; CHECK-INTERLEAVE1-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[EXT_B:%.*]] = fpext half [[LOAD_B]] to float
+; CHECK-INTERLEAVE1-NEXT: [[MUL:%.*]] = fmul float [[EXT_B]], [[EXT_A]]
+; CHECK-INTERLEAVE1-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add i64 [[IV]], 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
+; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP6]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK-INTERLEAVE1: [[FOR_EXIT]]:
+; CHECK-INTERLEAVE1-NEXT: [[TMP7:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP11]], %[[MIDDLE_BLOCK]] ]
+; CHECK-INTERLEAVE1-NEXT: ret float [[TMP7]]
+;
+; CHECK-INTERLEAVED-LABEL: define float @fdotp(
+; CHECK-INTERLEAVED-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-INTERLEAVED-NEXT: [[ENTRY:.*]]:
+; CHECK-INTERLEAVED-NEXT: [[TMP10:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVED-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP10]], 2
+; CHECK-INTERLEAVED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK-INTERLEAVED: [[VECTOR_PH]]:
+; CHECK-INTERLEAVED-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVED-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 4
+; CHECK-INTERLEAVED-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
+; CHECK-INTERLEAVED-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
+; CHECK-INTERLEAVED-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-INTERLEAVED: [[VECTOR_BODY]]:
+; CHECK-INTERLEAVED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT1:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 2 x float> [ insertelement (<vscale x 2 x float> splat (float -0.000000e+00), float 0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[TMP18:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[VEC_PHI1:%.*]] = phi <vscale x 2 x float> [ splat (float -0.000000e+00), %[[VECTOR_PH]] ], [ [[TMP19:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[TMP0:%.*]] = getelementptr half, ptr [[A]], i64 [[INDEX]]
+; CHECK-INTERLEAVED-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVED-NEXT: [[TMP6:%.*]] = shl nuw i64 [[TMP5]], 1
+; CHECK-INTERLEAVED-NEXT: [[TMP7:%.*]] = getelementptr half, ptr [[TMP0]], i64 [[TMP6]]
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 2 x half>, ptr [[TMP0]], align 1
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD2:%.*]] = load <vscale x 2 x half>, ptr [[TMP7]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP8:%.*]] = fpext <vscale x 2 x half> [[WIDE_LOAD]] to <vscale x 2 x float>
+; CHECK-INTERLEAVED-NEXT: [[TMP9:%.*]] = fpext <vscale x 2 x half> [[WIDE_LOAD2]] to <vscale x 2 x float>
+; CHECK-INTERLEAVED-NEXT: [[TMP4:%.*]] = getelementptr half, ptr [[B]], i64 [[INDEX]]
+; CHECK-INTERLEAVED-NEXT: [[TMP22:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVED-NEXT: [[TMP23:%.*]] = shl nuw i64 [[TMP22]], 1
+; CHECK-INTERLEAVED-NEXT: [[TMP13:%.*]] = getelementptr half, ptr [[TMP4]], i64 [[TMP23]]
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD3:%.*]] = load <vscale x 2 x half>, ptr [[TMP4]], align 1
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD4:%.*]] = load <vscale x 2 x half>, ptr [[TMP13]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP14:%.*]] = fpext <vscale x 2 x half> [[WIDE_LOAD3]] to <vscale x 2 x float>
+; CHECK-INTERLEAVED-NEXT: [[TMP15:%.*]] = fpext <vscale x 2 x half> [[WIDE_LOAD4]] to <vscale x 2 x float>
+; CHECK-INTERLEAVED-NEXT: [[TMP16:%.*]] = fmul <vscale x 2 x float> [[TMP14]], [[TMP8]]
+; CHECK-INTERLEAVED-NEXT: [[TMP17:%.*]] = fmul <vscale x 2 x float> [[TMP15]], [[TMP9]]
+; CHECK-INTERLEAVED-NEXT: [[TMP18]] = fadd reassoc <vscale x 2 x float> [[TMP16]], [[VEC_PHI]]
+; CHECK-INTERLEAVED-NEXT: [[TMP19]] = fadd reassoc <vscale x 2 x float> [[TMP17]], [[VEC_PHI1]]
+; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT1]] = add nuw i64 [[INDEX]], [[TMP3]]
+; CHECK-INTERLEAVED-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT1]], [[N_VEC]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[TMP20]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK-INTERLEAVED: [[MIDDLE_BLOCK]]:
+; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc <vscale x 2 x float> [[TMP19]], [[TMP18]]
+; CHECK-INTERLEAVED-NEXT: [[TMP21:%.*]] = call reassoc float @llvm.vector.reduce.fadd.nxv2f32(float -0.000000e+00, <vscale x 2 x float> [[BIN_RDX]])
+; CHECK-INTERLEAVED-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-INTERLEAVED: [[SCALAR_PH]]:
+; CHECK-INTERLEAVED-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-INTERLEAVED-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP21]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
+; CHECK-INTERLEAVED-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-INTERLEAVED: [[FOR_BODY]]:
+; CHECK-INTERLEAVED-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[ACCUM:%.*]] = phi float [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[GEP_A:%.*]] = getelementptr half, ptr [[A]], i64 [[IV]]
+; CHECK-INTERLEAVED-NEXT: [[LOAD_A:%.*]] = load half, ptr [[GEP_A]], align 1
+; CHECK-INTERLEAVED-NEXT: [[EXT_A:%.*]] = fpext half [[LOAD_A]] to float
+; CHECK-INTERLEAVED-NEXT: [[GEP_B:%.*]] = getelementptr half, ptr [[B]], i64 [[IV]]
+; CHECK-INTERLEAVED-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
+; CHECK-INTERLEAVED-NEXT: [[EXT_B:%.*]] = fpext half [[LOAD_B]] to float
+; CHECK-INTERLEAVED-NEXT: [[MUL:%.*]] = fmul float [[EXT_B]], [[EXT_A]]
+; CHECK-INTERLEAVED-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add i64 [[IV]], 1
+; CHECK-INTERLEAVED-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
+; CHECK-INTERLEAVED-NEXT: br i1 [[TMP12]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK-INTERLEAVED: [[FOR_EXIT]]:
+; CHECK-INTERLEAVED-NEXT: [[TMP11:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP21]], %[[MIDDLE_BLOCK]] ]
+; CHECK-INTERLEAVED-NEXT: ret float [[TMP11]]
+;
+; CHECK-MAXBW-LABEL: define float @fdotp(
+; CHECK-MAXBW-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-MAXBW-NEXT: [[ENTRY:.*]]:
+; CHECK-MAXBW-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-MAXBW-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP4]], 1
+; CHECK-MAXBW-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
+; CHECK-MAXBW-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK-MAXBW: [[VECTOR_PH]]:
+; CHECK-MAXBW-NEXT: [[TMP6:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-MAXBW-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP6]], 2
+; CHECK-MAXBW-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
+; CHECK-MAXBW-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
+; CHECK-MAXBW-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-MAXBW: [[VECTOR_BODY]]:
+; CHECK-MAXBW-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 2 x float> [ insertelement (<vscale x 2 x float> splat (float -0.000000e+00), float 0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[TMP10:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[TMP0:%.*]] = getelementptr half, ptr [[A]], i64 [[INDEX]]
+; CHECK-MAXBW-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 2 x half>, ptr [[TMP0]], align 1
+; CHECK-MAXBW-NEXT: [[TMP5:%.*]] = fpext <vscale x 2 x half> [[WIDE_LOAD]] to <vscale x 2 x float>
+; CHECK-MAXBW-NEXT: [[TMP2:%.*]] = getelementptr half, ptr [[B]], i64 [[INDEX]]
+; CHECK-MAXBW-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 2 x half>, ptr [[TMP2]], align 1
+; CHECK-MAXBW-NEXT: [[TMP7:%.*]] = fpext <vscale x 2 x half> [[WIDE_LOAD1]] to <vscale x 2 x float>
+; CHECK-MAXBW-NEXT: [[TMP8:%.*]] = fmul <vscale x 2 x float> [[TMP7]], [[TMP5]]
+; CHECK-MAXBW-NEXT: [[TMP10]] = fadd reassoc <vscale x 2 x float> [[TMP8]], [[VEC_PHI]]
+; CHECK-MAXBW-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
+; CHECK-MAXBW-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-MAXBW-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK-MAXBW: [[MIDDLE_BLOCK]]:
+; CHECK-MAXBW-NEXT: [[TMP11:%.*]] = call reassoc float @llvm.vector.reduce.fadd.nxv2f32(float -0.000000e+00, <vscale x 2 x float> [[TMP10]])
+; CHECK-MAXBW-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
+; CHECK-MAXBW-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-MAXBW: [[SCALAR_PH]]:
+; CHECK-MAXBW-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-MAXBW-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP11]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
+; CHECK-MAXBW-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-MAXBW: [[FOR_BODY]]:
+; CHECK-MAXBW-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[ACCUM:%.*]] = phi float [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[FOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[GEP_A:%.*]] = getelementptr half, ptr [[A]], i64 [[IV]]
+; CHECK-MAXBW-NEXT: [[LOAD_A:%.*]] = load half, ptr [[GEP_A]], align 1
+; CHECK-MAXBW-NEXT: [[EXT_A:%.*]] = fpext half [[LOAD_A]] to float
+; CHECK-MAXBW-NEXT: [[GEP_B:%.*]] = getelementptr half, ptr [[B]], i64 [[IV]]
+; CHECK-MAXBW-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
+; CHECK-MAXBW-NEXT: [[EXT_B:%.*]] = fpext half [[LOAD_B]] to float
+; CHECK-MAXBW-NEXT: [[MUL:%.*]] = fmul float [[EXT_B]], [[EXT_A]]
+; CHECK-MAXBW-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[ACCUM]]
+; CHECK-MAXBW-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-MAXBW-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
+; CHECK-MAXBW-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK-MAXBW: [[FOR_EXIT]]:
+; CHECK-MAXBW-NEXT: [[ADD_LCSSA:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP11]], %[[MIDDLE_BLOCK]] ]
+; CHECK-MAXBW-NEXT: ret float [[ADD_LCSSA]]
+;
+entry:
+ br label %for.body
+
+for.body: ; preds = %for.body, %entry
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+ %accum = phi float [ 0.0, %entry ], [ %add, %for.body ]
+ %gep.a = getelementptr half, ptr %a, i64 %iv
+ %load.a = load half, ptr %gep.a, align 1
+ %ext.a = fpext half %load.a to float
+ %gep.b = getelementptr half, ptr %b, i64 %iv
+ %load.b = load half, ptr %gep.b, align 1
+ %ext.b = fpext half %load.b to float
+ %mul = fmul float %ext.b, %ext.a
+ %add = fadd reassoc float %mul, %accum
+ %iv.next = add i64 %iv, 1
+ %exitcond.not = icmp eq i64 %iv.next, 1024
+ br i1 %exitcond.not, label %for.exit, label %for.body
+
+for.exit: ; preds = %for.body
+ ret float %add
+}
>From ab009b0fba546024686ec179959e1ca162b5fab5 Mon Sep 17 00:00:00 2001
From: Damian Heaton <Damian.Heaton at arm.com>
Date: Tue, 21 Oct 2025 15:30:57 +0000
Subject: [PATCH 2/9] Remove extraneous changes & add 'not_' tests
---
.../Transforms/Vectorize/LoopVectorize.cpp | 8 +-
.../AArch64/partial-reduce-fdot-product.ll | 956 ++++++++++++++++++
2 files changed, 959 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index c5dbc464fb826..b166b4a4aacff 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -5387,16 +5387,14 @@ LoopVectorizationCostModel::getReductionPatternCost(Instruction *I,
// it is not we return an invalid cost specifying the orignal cost method
// should be used.
Instruction *RetI = I;
- if (match(RetI, m_ZExtOrSExt(m_Value())) || match(RetI, m_FPExt(m_Value()))) {
+ if (match(RetI, m_ZExtOrSExt(m_Value()))) {
if (!RetI->hasOneUser())
return std::nullopt;
RetI = RetI->user_back();
}
- if ((match(RetI, m_OneUse(m_Mul(m_Value(), m_Value()))) &&
- RetI->user_back()->getOpcode() == Instruction::Add) ||
- (match(RetI, m_OneUse(m_FMul(m_Value(), m_Value()))) &&
- RetI->user_back()->getOpcode() == Instruction::FAdd)) {
+ if (match(RetI, m_OneUse(m_Mul(m_Value(), m_Value()))) &&
+ RetI->user_back()->getOpcode() == Instruction::Add) {
RetI = RetI->user_back();
}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fdot-product.ll b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fdot-product.ll
index e441ffb7dbc95..b36ccbfdb2086 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fdot-product.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fdot-product.ll
@@ -201,3 +201,959 @@ for.body: ; preds = %for.body, %entry
for.exit: ; preds = %for.body
ret float %add
}
+
+define double @not_fdotp_different_types(ptr %a, ptr %b) #0 {
+; CHECK-INTERLEAVE1-LABEL: define double @not_fdotp_different_types(
+; CHECK-INTERLEAVE1-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
+; CHECK-INTERLEAVE1-NEXT: [[ENTRY:.*:]]
+; CHECK-INTERLEAVE1-NEXT: br label %[[VECTOR_PH:.*]]
+; CHECK-INTERLEAVE1: [[VECTOR_PH]]:
+; CHECK-INTERLEAVE1-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-INTERLEAVE1: [[VECTOR_BODY]]:
+; CHECK-INTERLEAVE1-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[IV_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[VEC_PHI:%.*]] = phi <8 x double> [ <double 0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[GEP_A:%.*]] = getelementptr half, ptr [[A]], i64 [[IV]]
+; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD:%.*]] = load <8 x half>, ptr [[GEP_A]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP1:%.*]] = fpext <8 x half> [[WIDE_LOAD]] to <8 x double>
+; CHECK-INTERLEAVE1-NEXT: [[GEP_B:%.*]] = getelementptr float, ptr [[B]], i64 [[IV]]
+; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD1:%.*]] = load <8 x float>, ptr [[GEP_B]], align 2
+; CHECK-INTERLEAVE1-NEXT: [[TMP3:%.*]] = fpext <8 x float> [[WIDE_LOAD1]] to <8 x double>
+; CHECK-INTERLEAVE1-NEXT: [[TMP4:%.*]] = fmul <8 x double> [[TMP3]], [[TMP1]]
+; CHECK-INTERLEAVE1-NEXT: [[TMP5]] = fadd reassoc <8 x double> [[TMP4]], [[VEC_PHI]]
+; CHECK-INTERLEAVE1-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 8
+; CHECK-INTERLEAVE1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
+; CHECK-INTERLEAVE1-NEXT: br i1 [[EXITCOND_NOT]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK-INTERLEAVE1: [[MIDDLE_BLOCK]]:
+; CHECK-INTERLEAVE1-NEXT: [[ADD_LCSSA:%.*]] = call reassoc double @llvm.vector.reduce.fadd.v8f64(double -0.000000e+00, <8 x double> [[TMP5]])
+; CHECK-INTERLEAVE1-NEXT: br label %[[FOR_EXIT:.*]]
+; CHECK-INTERLEAVE1: [[FOR_EXIT]]:
+; CHECK-INTERLEAVE1-NEXT: ret double [[ADD_LCSSA]]
+;
+; CHECK-INTERLEAVED-LABEL: define double @not_fdotp_different_types(
+; CHECK-INTERLEAVED-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
+; CHECK-INTERLEAVED-NEXT: [[ENTRY:.*:]]
+; CHECK-INTERLEAVED-NEXT: br label %[[VECTOR_PH:.*]]
+; CHECK-INTERLEAVED: [[VECTOR_PH]]:
+; CHECK-INTERLEAVED-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-INTERLEAVED: [[VECTOR_BODY]]:
+; CHECK-INTERLEAVED-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[IV_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[VEC_PHI:%.*]] = phi <8 x double> [ <double 0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %[[VECTOR_PH]] ], [ [[TMP10:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[VEC_PHI1:%.*]] = phi <8 x double> [ splat (double -0.000000e+00), %[[VECTOR_PH]] ], [ [[TMP11:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[GEP_A:%.*]] = getelementptr half, ptr [[A]], i64 [[IV]]
+; CHECK-INTERLEAVED-NEXT: [[TMP1:%.*]] = getelementptr half, ptr [[GEP_A]], i32 8
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD:%.*]] = load <8 x half>, ptr [[GEP_A]], align 1
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD2:%.*]] = load <8 x half>, ptr [[TMP1]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP2:%.*]] = fpext <8 x half> [[WIDE_LOAD]] to <8 x double>
+; CHECK-INTERLEAVED-NEXT: [[TMP3:%.*]] = fpext <8 x half> [[WIDE_LOAD2]] to <8 x double>
+; CHECK-INTERLEAVED-NEXT: [[GEP_B:%.*]] = getelementptr float, ptr [[B]], i64 [[IV]]
+; CHECK-INTERLEAVED-NEXT: [[TMP5:%.*]] = getelementptr float, ptr [[GEP_B]], i32 8
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD3:%.*]] = load <8 x float>, ptr [[GEP_B]], align 2
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD4:%.*]] = load <8 x float>, ptr [[TMP5]], align 2
+; CHECK-INTERLEAVED-NEXT: [[TMP6:%.*]] = fpext <8 x float> [[WIDE_LOAD3]] to <8 x double>
+; CHECK-INTERLEAVED-NEXT: [[TMP7:%.*]] = fpext <8 x float> [[WIDE_LOAD4]] to <8 x double>
+; CHECK-INTERLEAVED-NEXT: [[TMP8:%.*]] = fmul <8 x double> [[TMP6]], [[TMP2]]
+; CHECK-INTERLEAVED-NEXT: [[TMP9:%.*]] = fmul <8 x double> [[TMP7]], [[TMP3]]
+; CHECK-INTERLEAVED-NEXT: [[TMP10]] = fadd reassoc <8 x double> [[TMP8]], [[VEC_PHI]]
+; CHECK-INTERLEAVED-NEXT: [[TMP11]] = fadd reassoc <8 x double> [[TMP9]], [[VEC_PHI1]]
+; CHECK-INTERLEAVED-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 16
+; CHECK-INTERLEAVED-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
+; CHECK-INTERLEAVED-NEXT: br i1 [[EXITCOND_NOT]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK-INTERLEAVED: [[MIDDLE_BLOCK]]:
+; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc <8 x double> [[TMP11]], [[TMP10]]
+; CHECK-INTERLEAVED-NEXT: [[ADD_LCSSA:%.*]] = call reassoc double @llvm.vector.reduce.fadd.v8f64(double -0.000000e+00, <8 x double> [[BIN_RDX]])
+; CHECK-INTERLEAVED-NEXT: br label %[[FOR_EXIT:.*]]
+; CHECK-INTERLEAVED: [[FOR_EXIT]]:
+; CHECK-INTERLEAVED-NEXT: ret double [[ADD_LCSSA]]
+;
+; CHECK-MAXBW-LABEL: define double @not_fdotp_different_types(
+; CHECK-MAXBW-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
+; CHECK-MAXBW-NEXT: [[ENTRY:.*]]:
+; CHECK-MAXBW-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-MAXBW-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 3
+; CHECK-MAXBW-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
+; CHECK-MAXBW-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK-MAXBW: [[VECTOR_PH]]:
+; CHECK-MAXBW-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-MAXBW-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 8
+; CHECK-MAXBW-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
+; CHECK-MAXBW-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
+; CHECK-MAXBW-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-MAXBW: [[VECTOR_BODY]]:
+; CHECK-MAXBW-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 8 x double> [ insertelement (<vscale x 8 x double> splat (double -0.000000e+00), double 0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[TMP9:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[TMP4:%.*]] = getelementptr half, ptr [[A]], i64 [[INDEX]]
+; CHECK-MAXBW-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 8 x half>, ptr [[TMP4]], align 1
+; CHECK-MAXBW-NEXT: [[TMP5:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD]] to <vscale x 8 x double>
+; CHECK-MAXBW-NEXT: [[TMP6:%.*]] = getelementptr float, ptr [[B]], i64 [[INDEX]]
+; CHECK-MAXBW-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 8 x float>, ptr [[TMP6]], align 2
+; CHECK-MAXBW-NEXT: [[TMP7:%.*]] = fpext <vscale x 8 x float> [[WIDE_LOAD1]] to <vscale x 8 x double>
+; CHECK-MAXBW-NEXT: [[TMP8:%.*]] = fmul <vscale x 8 x double> [[TMP7]], [[TMP5]]
+; CHECK-MAXBW-NEXT: [[TMP9]] = fadd reassoc <vscale x 8 x double> [[TMP8]], [[VEC_PHI]]
+; CHECK-MAXBW-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
+; CHECK-MAXBW-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-MAXBW-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; CHECK-MAXBW: [[MIDDLE_BLOCK]]:
+; CHECK-MAXBW-NEXT: [[TMP11:%.*]] = call reassoc double @llvm.vector.reduce.fadd.nxv8f64(double -0.000000e+00, <vscale x 8 x double> [[TMP9]])
+; CHECK-MAXBW-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
+; CHECK-MAXBW-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-MAXBW: [[SCALAR_PH]]:
+; CHECK-MAXBW-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-MAXBW-NEXT: [[BC_MERGE_RDX:%.*]] = phi double [ [[TMP11]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
+; CHECK-MAXBW-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-MAXBW: [[FOR_BODY]]:
+; CHECK-MAXBW-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[ACCUM:%.*]] = phi double [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[FOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[GEP_A:%.*]] = getelementptr half, ptr [[A]], i64 [[IV]]
+; CHECK-MAXBW-NEXT: [[LOAD_A:%.*]] = load half, ptr [[GEP_A]], align 1
+; CHECK-MAXBW-NEXT: [[EXT_A:%.*]] = fpext half [[LOAD_A]] to double
+; CHECK-MAXBW-NEXT: [[GEP_B:%.*]] = getelementptr float, ptr [[B]], i64 [[IV]]
+; CHECK-MAXBW-NEXT: [[LOAD_B:%.*]] = load float, ptr [[GEP_B]], align 2
+; CHECK-MAXBW-NEXT: [[EXT_B:%.*]] = fpext float [[LOAD_B]] to double
+; CHECK-MAXBW-NEXT: [[MUL:%.*]] = fmul double [[EXT_B]], [[EXT_A]]
+; CHECK-MAXBW-NEXT: [[ADD]] = fadd reassoc double [[MUL]], [[ACCUM]]
+; CHECK-MAXBW-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-MAXBW-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
+; CHECK-MAXBW-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
+; CHECK-MAXBW: [[FOR_EXIT]]:
+; CHECK-MAXBW-NEXT: [[ADD_LCSSA:%.*]] = phi double [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP11]], %[[MIDDLE_BLOCK]] ]
+; CHECK-MAXBW-NEXT: ret double [[ADD_LCSSA]]
+;
+entry:
+ br label %for.body
+
+for.body: ; preds = %for.body, %entry
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+ %accum = phi double [ 0.0, %entry ], [ %add, %for.body ]
+ %gep.a = getelementptr half, ptr %a, i64 %iv
+ %load.a = load half, ptr %gep.a, align 1
+ %ext.a = fpext half %load.a to double
+ %gep.b = getelementptr float, ptr %b, i64 %iv
+ %load.b = load float, ptr %gep.b, align 2
+ %ext.b = fpext float %load.b to double
+ %mul = fmul double %ext.b, %ext.a
+ %add = fadd reassoc double %mul, %accum
+ %iv.next = add i64 %iv, 1
+ %exitcond.not = icmp eq i64 %iv.next, 1024
+ br i1 %exitcond.not, label %for.exit, label %for.body
+
+for.exit: ; preds = %for.body
+ ret double %add
+}
+
+define float @not_fdotp_not_phi(ptr %a, ptr %b) #0 {
+; CHECK-INTERLEAVE1-LABEL: define float @not_fdotp_not_phi(
+; CHECK-INTERLEAVE1-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
+; CHECK-INTERLEAVE1-NEXT: [[ENTRY:.*]]:
+; CHECK-INTERLEAVE1-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVE1-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 3
+; CHECK-INTERLEAVE1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK-INTERLEAVE1: [[VECTOR_PH]]:
+; CHECK-INTERLEAVE1-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVE1-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 8
+; CHECK-INTERLEAVE1-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
+; CHECK-INTERLEAVE1-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
+; CHECK-INTERLEAVE1-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-INTERLEAVE1: [[VECTOR_BODY]]:
+; CHECK-INTERLEAVE1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[TMP4:%.*]] = getelementptr half, ptr [[A]], i64 [[INDEX]]
+; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 8 x half>, ptr [[TMP4]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP5:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD]] to <vscale x 8 x float>
+; CHECK-INTERLEAVE1-NEXT: [[TMP6:%.*]] = getelementptr half, ptr [[B]], i64 [[INDEX]]
+; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 8 x half>, ptr [[TMP6]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP7:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD1]] to <vscale x 8 x float>
+; CHECK-INTERLEAVE1-NEXT: [[TMP8:%.*]] = fmul <vscale x 8 x float> [[TMP7]], [[TMP5]]
+; CHECK-INTERLEAVE1-NEXT: [[TMP9:%.*]] = fadd reassoc <vscale x 8 x float> [[TMP8]], [[TMP7]]
+; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
+; CHECK-INTERLEAVE1-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; CHECK-INTERLEAVE1: [[MIDDLE_BLOCK]]:
+; CHECK-INTERLEAVE1-NEXT: [[TMP11:%.*]] = call i32 @llvm.vscale.i32()
+; CHECK-INTERLEAVE1-NEXT: [[TMP12:%.*]] = mul nuw i32 [[TMP11]], 8
+; CHECK-INTERLEAVE1-NEXT: [[TMP13:%.*]] = sub i32 [[TMP12]], 1
+; CHECK-INTERLEAVE1-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <vscale x 8 x float> [[TMP9]], i32 [[TMP13]]
+; CHECK-INTERLEAVE1-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-INTERLEAVE1: [[SCALAR_PH]]:
+; CHECK-INTERLEAVE1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[SCALAR_RECUR_INIT:%.*]] = phi float [ [[VECTOR_RECUR_EXTRACT]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
+; CHECK-INTERLEAVE1-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-INTERLEAVE1: [[FOR_BODY]]:
+; CHECK-INTERLEAVE1-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[ACCUM:%.*]] = phi float [ [[SCALAR_RECUR_INIT]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[GEP_A:%.*]] = getelementptr half, ptr [[A]], i64 [[IV]]
+; CHECK-INTERLEAVE1-NEXT: [[LOAD_A:%.*]] = load half, ptr [[GEP_A]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[EXT_A:%.*]] = fpext half [[LOAD_A]] to float
+; CHECK-INTERLEAVE1-NEXT: [[GEP_B:%.*]] = getelementptr half, ptr [[B]], i64 [[IV]]
+; CHECK-INTERLEAVE1-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[EXT_B:%.*]] = fpext half [[LOAD_B]] to float
+; CHECK-INTERLEAVE1-NEXT: [[MUL:%.*]] = fmul float [[EXT_B]], [[EXT_A]]
+; CHECK-INTERLEAVE1-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[EXT_B]]
+; CHECK-INTERLEAVE1-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-INTERLEAVE1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
+; CHECK-INTERLEAVE1-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
+; CHECK-INTERLEAVE1: [[FOR_EXIT]]:
+; CHECK-INTERLEAVE1-NEXT: [[ADD_LCSSA:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[VECTOR_RECUR_EXTRACT]], %[[MIDDLE_BLOCK]] ]
+; CHECK-INTERLEAVE1-NEXT: ret float [[ADD_LCSSA]]
+;
+; CHECK-INTERLEAVED-LABEL: define float @not_fdotp_not_phi(
+; CHECK-INTERLEAVED-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
+; CHECK-INTERLEAVED-NEXT: [[ENTRY:.*]]:
+; CHECK-INTERLEAVED-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVED-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 4
+; CHECK-INTERLEAVED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK-INTERLEAVED: [[VECTOR_PH]]:
+; CHECK-INTERLEAVED-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVED-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 16
+; CHECK-INTERLEAVED-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
+; CHECK-INTERLEAVED-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
+; CHECK-INTERLEAVED-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-INTERLEAVED: [[VECTOR_BODY]]:
+; CHECK-INTERLEAVED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[TMP4:%.*]] = getelementptr half, ptr [[A]], i64 [[INDEX]]
+; CHECK-INTERLEAVED-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVED-NEXT: [[TMP6:%.*]] = shl nuw i64 [[TMP5]], 3
+; CHECK-INTERLEAVED-NEXT: [[TMP7:%.*]] = getelementptr half, ptr [[TMP4]], i64 [[TMP6]]
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 8 x half>, ptr [[TMP7]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP8:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD]] to <vscale x 8 x float>
+; CHECK-INTERLEAVED-NEXT: [[TMP9:%.*]] = getelementptr half, ptr [[B]], i64 [[INDEX]]
+; CHECK-INTERLEAVED-NEXT: [[TMP10:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVED-NEXT: [[TMP11:%.*]] = shl nuw i64 [[TMP10]], 3
+; CHECK-INTERLEAVED-NEXT: [[TMP12:%.*]] = getelementptr half, ptr [[TMP9]], i64 [[TMP11]]
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 8 x half>, ptr [[TMP12]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP13:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD1]] to <vscale x 8 x float>
+; CHECK-INTERLEAVED-NEXT: [[TMP14:%.*]] = fmul <vscale x 8 x float> [[TMP13]], [[TMP8]]
+; CHECK-INTERLEAVED-NEXT: [[TMP15:%.*]] = fadd reassoc <vscale x 8 x float> [[TMP14]], [[TMP13]]
+; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
+; CHECK-INTERLEAVED-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; CHECK-INTERLEAVED: [[MIDDLE_BLOCK]]:
+; CHECK-INTERLEAVED-NEXT: [[TMP17:%.*]] = call i32 @llvm.vscale.i32()
+; CHECK-INTERLEAVED-NEXT: [[TMP18:%.*]] = mul nuw i32 [[TMP17]], 8
+; CHECK-INTERLEAVED-NEXT: [[TMP19:%.*]] = sub i32 [[TMP18]], 1
+; CHECK-INTERLEAVED-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <vscale x 8 x float> [[TMP15]], i32 [[TMP19]]
+; CHECK-INTERLEAVED-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-INTERLEAVED: [[SCALAR_PH]]:
+; CHECK-INTERLEAVED-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-INTERLEAVED-NEXT: [[SCALAR_RECUR_INIT:%.*]] = phi float [ [[VECTOR_RECUR_EXTRACT]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
+; CHECK-INTERLEAVED-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-INTERLEAVED: [[FOR_BODY]]:
+; CHECK-INTERLEAVED-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[ACCUM:%.*]] = phi float [ [[SCALAR_RECUR_INIT]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[GEP_A:%.*]] = getelementptr half, ptr [[A]], i64 [[IV]]
+; CHECK-INTERLEAVED-NEXT: [[LOAD_A:%.*]] = load half, ptr [[GEP_A]], align 1
+; CHECK-INTERLEAVED-NEXT: [[EXT_A:%.*]] = fpext half [[LOAD_A]] to float
+; CHECK-INTERLEAVED-NEXT: [[GEP_B:%.*]] = getelementptr half, ptr [[B]], i64 [[IV]]
+; CHECK-INTERLEAVED-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
+; CHECK-INTERLEAVED-NEXT: [[EXT_B:%.*]] = fpext half [[LOAD_B]] to float
+; CHECK-INTERLEAVED-NEXT: [[MUL:%.*]] = fmul float [[EXT_B]], [[EXT_A]]
+; CHECK-INTERLEAVED-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[EXT_B]]
+; CHECK-INTERLEAVED-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-INTERLEAVED-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
+; CHECK-INTERLEAVED-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
+; CHECK-INTERLEAVED: [[FOR_EXIT]]:
+; CHECK-INTERLEAVED-NEXT: [[ADD_LCSSA:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[VECTOR_RECUR_EXTRACT]], %[[MIDDLE_BLOCK]] ]
+; CHECK-INTERLEAVED-NEXT: ret float [[ADD_LCSSA]]
+;
+; CHECK-MAXBW-LABEL: define float @not_fdotp_not_phi(
+; CHECK-MAXBW-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
+; CHECK-MAXBW-NEXT: [[ENTRY:.*]]:
+; CHECK-MAXBW-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-MAXBW-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 3
+; CHECK-MAXBW-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
+; CHECK-MAXBW-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK-MAXBW: [[VECTOR_PH]]:
+; CHECK-MAXBW-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-MAXBW-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 8
+; CHECK-MAXBW-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
+; CHECK-MAXBW-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
+; CHECK-MAXBW-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-MAXBW: [[VECTOR_BODY]]:
+; CHECK-MAXBW-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[TMP4:%.*]] = getelementptr half, ptr [[A]], i64 [[INDEX]]
+; CHECK-MAXBW-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 8 x half>, ptr [[TMP4]], align 1
+; CHECK-MAXBW-NEXT: [[TMP5:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD]] to <vscale x 8 x float>
+; CHECK-MAXBW-NEXT: [[TMP6:%.*]] = getelementptr half, ptr [[B]], i64 [[INDEX]]
+; CHECK-MAXBW-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 8 x half>, ptr [[TMP6]], align 1
+; CHECK-MAXBW-NEXT: [[TMP7:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD1]] to <vscale x 8 x float>
+; CHECK-MAXBW-NEXT: [[TMP8:%.*]] = fmul <vscale x 8 x float> [[TMP7]], [[TMP5]]
+; CHECK-MAXBW-NEXT: [[TMP9:%.*]] = fadd reassoc <vscale x 8 x float> [[TMP8]], [[TMP7]]
+; CHECK-MAXBW-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
+; CHECK-MAXBW-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-MAXBW-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
+; CHECK-MAXBW: [[MIDDLE_BLOCK]]:
+; CHECK-MAXBW-NEXT: [[TMP11:%.*]] = call i32 @llvm.vscale.i32()
+; CHECK-MAXBW-NEXT: [[TMP12:%.*]] = mul nuw i32 [[TMP11]], 8
+; CHECK-MAXBW-NEXT: [[TMP13:%.*]] = sub i32 [[TMP12]], 1
+; CHECK-MAXBW-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <vscale x 8 x float> [[TMP9]], i32 [[TMP13]]
+; CHECK-MAXBW-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
+; CHECK-MAXBW-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-MAXBW: [[SCALAR_PH]]:
+; CHECK-MAXBW-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-MAXBW-NEXT: [[SCALAR_RECUR_INIT:%.*]] = phi float [ [[VECTOR_RECUR_EXTRACT]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
+; CHECK-MAXBW-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-MAXBW: [[FOR_BODY]]:
+; CHECK-MAXBW-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[ACCUM:%.*]] = phi float [ [[SCALAR_RECUR_INIT]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[FOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[GEP_A:%.*]] = getelementptr half, ptr [[A]], i64 [[IV]]
+; CHECK-MAXBW-NEXT: [[LOAD_A:%.*]] = load half, ptr [[GEP_A]], align 1
+; CHECK-MAXBW-NEXT: [[EXT_A:%.*]] = fpext half [[LOAD_A]] to float
+; CHECK-MAXBW-NEXT: [[GEP_B:%.*]] = getelementptr half, ptr [[B]], i64 [[IV]]
+; CHECK-MAXBW-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
+; CHECK-MAXBW-NEXT: [[EXT_B:%.*]] = fpext half [[LOAD_B]] to float
+; CHECK-MAXBW-NEXT: [[MUL:%.*]] = fmul float [[EXT_B]], [[EXT_A]]
+; CHECK-MAXBW-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[EXT_B]]
+; CHECK-MAXBW-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-MAXBW-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
+; CHECK-MAXBW-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
+; CHECK-MAXBW: [[FOR_EXIT]]:
+; CHECK-MAXBW-NEXT: [[ADD_LCSSA:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[VECTOR_RECUR_EXTRACT]], %[[MIDDLE_BLOCK]] ]
+; CHECK-MAXBW-NEXT: ret float [[ADD_LCSSA]]
+;
+entry:
+ br label %for.body
+
+for.body: ; preds = %for.body, %entry
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+ %accum = phi float [ 0.0, %entry ], [ %add, %for.body ]
+ %gep.a = getelementptr half, ptr %a, i64 %iv
+ %load.a = load half, ptr %gep.a, align 1
+ %ext.a = fpext half %load.a to float
+ %gep.b = getelementptr half, ptr %b, i64 %iv
+ %load.b = load half, ptr %gep.b, align 1
+ %ext.b = fpext half %load.b to float
+ %mul = fmul float %ext.b, %ext.a
+ %add = fadd reassoc float %mul, %ext.b
+ %iv.next = add i64 %iv, 1
+ %exitcond.not = icmp eq i64 %iv.next, 1024
+ br i1 %exitcond.not, label %for.exit, label %for.body
+
+for.exit: ; preds = %for.body
+ ret float %add
+}
+
+define void @not_fdotp_not_phi2(ptr %matrix, i32 %n) #0 {
+; CHECK-INTERLEAVE1-LABEL: define void @not_fdotp_not_phi2(
+; CHECK-INTERLEAVE1-SAME: ptr [[MATRIX:%.*]], i32 [[N:%.*]]) #[[ATTR0]] {
+; CHECK-INTERLEAVE1-NEXT: [[ENTRY:.*]]:
+; CHECK-INTERLEAVE1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[N]], 0
+; CHECK-INTERLEAVE1-NEXT: br i1 [[CMP]], label %[[FOR_PREHEADER:.*]], label %[[EXIT:.*]]
+; CHECK-INTERLEAVE1: [[FOR_PREHEADER]]:
+; CHECK-INTERLEAVE1-NEXT: [[LOAD_A:%.*]] = load half, ptr null, align 1
+; CHECK-INTERLEAVE1-NEXT: [[LOAD_A1:%.*]] = load half, ptr inttoptr (i64 1 to ptr), align 1
+; CHECK-INTERLEAVE1-NEXT: [[A_EXT:%.*]] = fpext half [[LOAD_A]] to float
+; CHECK-INTERLEAVE1-NEXT: [[A_EXT1:%.*]] = fpext half [[LOAD_A1]] to float
+; CHECK-INTERLEAVE1-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64
+; CHECK-INTERLEAVE1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 4
+; CHECK-INTERLEAVE1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK-INTERLEAVE1: [[VECTOR_PH]]:
+; CHECK-INTERLEAVE1-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 4
+; CHECK-INTERLEAVE1-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]]
+; CHECK-INTERLEAVE1-NEXT: [[TMP1:%.*]] = trunc i64 [[N_VEC]] to i32
+; CHECK-INTERLEAVE1-NEXT: [[TMP2:%.*]] = mul i64 [[N_VEC]], 32
+; CHECK-INTERLEAVE1-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[MATRIX]], i64 [[TMP2]]
+; CHECK-INTERLEAVE1-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x float> poison, float [[A_EXT]], i64 0
+; CHECK-INTERLEAVE1-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x float> [[BROADCAST_SPLATINSERT]], <4 x float> poison, <4 x i32> zeroinitializer
+; CHECK-INTERLEAVE1-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <4 x float> poison, float [[A_EXT1]], i64 0
+; CHECK-INTERLEAVE1-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x float> [[BROADCAST_SPLATINSERT1]], <4 x float> poison, <4 x i32> zeroinitializer
+; CHECK-INTERLEAVE1-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-INTERLEAVE1: [[VECTOR_BODY]]:
+; CHECK-INTERLEAVE1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[VEC_PHI:%.*]] = phi <4 x float> [ <float 0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %[[VECTOR_PH]] ], [ [[TMP37:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 32
+; CHECK-INTERLEAVE1-NEXT: [[TMP4:%.*]] = add i64 [[OFFSET_IDX]], 0
+; CHECK-INTERLEAVE1-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 32
+; CHECK-INTERLEAVE1-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 64
+; CHECK-INTERLEAVE1-NEXT: [[TMP7:%.*]] = add i64 [[OFFSET_IDX]], 96
+; CHECK-INTERLEAVE1-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[MATRIX]], i64 [[TMP4]]
+; CHECK-INTERLEAVE1-NEXT: [[NEXT_GEP3:%.*]] = getelementptr i8, ptr [[MATRIX]], i64 [[TMP5]]
+; CHECK-INTERLEAVE1-NEXT: [[NEXT_GEP4:%.*]] = getelementptr i8, ptr [[MATRIX]], i64 [[TMP6]]
+; CHECK-INTERLEAVE1-NEXT: [[NEXT_GEP5:%.*]] = getelementptr i8, ptr [[MATRIX]], i64 [[TMP7]]
+; CHECK-INTERLEAVE1-NEXT: [[TMP8:%.*]] = getelementptr half, ptr [[NEXT_GEP]], i64 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP9:%.*]] = getelementptr half, ptr [[NEXT_GEP3]], i64 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP10:%.*]] = getelementptr half, ptr [[NEXT_GEP4]], i64 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP11:%.*]] = getelementptr half, ptr [[NEXT_GEP5]], i64 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP12:%.*]] = getelementptr half, ptr [[NEXT_GEP]], i64 2
+; CHECK-INTERLEAVE1-NEXT: [[TMP13:%.*]] = getelementptr half, ptr [[NEXT_GEP3]], i64 2
+; CHECK-INTERLEAVE1-NEXT: [[TMP14:%.*]] = getelementptr half, ptr [[NEXT_GEP4]], i64 2
+; CHECK-INTERLEAVE1-NEXT: [[TMP15:%.*]] = getelementptr half, ptr [[NEXT_GEP5]], i64 2
+; CHECK-INTERLEAVE1-NEXT: [[TMP16:%.*]] = load half, ptr [[TMP8]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP17:%.*]] = load half, ptr [[TMP9]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP18:%.*]] = load half, ptr [[TMP10]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP19:%.*]] = load half, ptr [[TMP11]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP20:%.*]] = insertelement <4 x half> poison, half [[TMP16]], i32 0
+; CHECK-INTERLEAVE1-NEXT: [[TMP21:%.*]] = insertelement <4 x half> [[TMP20]], half [[TMP17]], i32 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP22:%.*]] = insertelement <4 x half> [[TMP21]], half [[TMP18]], i32 2
+; CHECK-INTERLEAVE1-NEXT: [[TMP23:%.*]] = insertelement <4 x half> [[TMP22]], half [[TMP19]], i32 3
+; CHECK-INTERLEAVE1-NEXT: [[TMP24:%.*]] = fpext <4 x half> [[TMP23]] to <4 x float>
+; CHECK-INTERLEAVE1-NEXT: [[TMP25:%.*]] = fmul <4 x float> [[BROADCAST_SPLAT]], [[TMP24]]
+; CHECK-INTERLEAVE1-NEXT: [[TMP26:%.*]] = fadd reassoc <4 x float> [[TMP25]], [[VEC_PHI]]
+; CHECK-INTERLEAVE1-NEXT: [[TMP27:%.*]] = load half, ptr [[TMP12]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP28:%.*]] = load half, ptr [[TMP13]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP29:%.*]] = load half, ptr [[TMP14]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP30:%.*]] = load half, ptr [[TMP15]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP31:%.*]] = insertelement <4 x half> poison, half [[TMP27]], i32 0
+; CHECK-INTERLEAVE1-NEXT: [[TMP32:%.*]] = insertelement <4 x half> [[TMP31]], half [[TMP28]], i32 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP33:%.*]] = insertelement <4 x half> [[TMP32]], half [[TMP29]], i32 2
+; CHECK-INTERLEAVE1-NEXT: [[TMP34:%.*]] = insertelement <4 x half> [[TMP33]], half [[TMP30]], i32 3
+; CHECK-INTERLEAVE1-NEXT: [[TMP35:%.*]] = fpext <4 x half> [[TMP34]] to <4 x float>
+; CHECK-INTERLEAVE1-NEXT: [[TMP36:%.*]] = fmul <4 x float> [[BROADCAST_SPLAT2]], [[TMP35]]
+; CHECK-INTERLEAVE1-NEXT: [[TMP37]] = fadd reassoc <4 x float> [[TMP36]], [[TMP26]]
+; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
+; CHECK-INTERLEAVE1-NEXT: [[TMP38:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP38]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
+; CHECK-INTERLEAVE1: [[MIDDLE_BLOCK]]:
+; CHECK-INTERLEAVE1-NEXT: [[TMP39:%.*]] = call reassoc float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[TMP37]])
+; CHECK-INTERLEAVE1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-INTERLEAVE1: [[SCALAR_PH]]:
+; CHECK-INTERLEAVE1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[TMP1]], %[[MIDDLE_BLOCK]] ], [ 0, %[[FOR_PREHEADER]] ]
+; CHECK-INTERLEAVE1-NEXT: [[BC_RESUME_VAL6:%.*]] = phi ptr [ [[TMP3]], %[[MIDDLE_BLOCK]] ], [ [[MATRIX]], %[[FOR_PREHEADER]] ]
+; CHECK-INTERLEAVE1-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP39]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[FOR_PREHEADER]] ]
+; CHECK-INTERLEAVE1-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-INTERLEAVE1: [[FOR_BODY]]:
+; CHECK-INTERLEAVE1-NEXT: [[IV:%.*]] = phi i32 [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]
+; CHECK-INTERLEAVE1-NEXT: [[PTR:%.*]] = phi ptr [ [[SCEVGEP:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL6]], %[[SCALAR_PH]] ]
+; CHECK-INTERLEAVE1-NEXT: [[ACCUM:%.*]] = phi float [ [[ADD_1:%.*]], %[[FOR_BODY]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ]
+; CHECK-INTERLEAVE1-NEXT: [[GEP_B:%.*]] = getelementptr half, ptr [[PTR]], i64 1
+; CHECK-INTERLEAVE1-NEXT: [[GEP_B1:%.*]] = getelementptr half, ptr [[PTR]], i64 2
+; CHECK-INTERLEAVE1-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[B_EXT:%.*]] = fpext half [[LOAD_B]] to float
+; CHECK-INTERLEAVE1-NEXT: [[MUL:%.*]] = fmul float [[A_EXT]], [[B_EXT]]
+; CHECK-INTERLEAVE1-NEXT: [[ADD:%.*]] = fadd reassoc float [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVE1-NEXT: [[LOAD_B1:%.*]] = load half, ptr [[GEP_B1]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[B_EXT1:%.*]] = fpext half [[LOAD_B1]] to float
+; CHECK-INTERLEAVE1-NEXT: [[MUL_1:%.*]] = fmul float [[A_EXT1]], [[B_EXT1]]
+; CHECK-INTERLEAVE1-NEXT: [[ADD_1]] = fadd reassoc float [[MUL_1]], [[ADD]]
+; CHECK-INTERLEAVE1-NEXT: [[SCEVGEP]] = getelementptr half, ptr [[PTR]], i64 16
+; CHECK-INTERLEAVE1-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
+; CHECK-INTERLEAVE1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[IV_NEXT]], [[N]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
+; CHECK-INTERLEAVE1: [[FOR_EXIT]]:
+; CHECK-INTERLEAVE1-NEXT: [[ADD_FLOAT:%.*]] = phi float [ [[ADD_1]], %[[FOR_BODY]] ], [ [[TMP39]], %[[MIDDLE_BLOCK]] ]
+; CHECK-INTERLEAVE1-NEXT: br label %[[EXIT]]
+; CHECK-INTERLEAVE1: [[EXIT]]:
+; CHECK-INTERLEAVE1-NEXT: [[RESULT:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[ADD_FLOAT]], %[[FOR_EXIT]] ]
+; CHECK-INTERLEAVE1-NEXT: store float [[RESULT]], ptr [[MATRIX]], align 4
+; CHECK-INTERLEAVE1-NEXT: ret void
+;
+; CHECK-INTERLEAVED-LABEL: define void @not_fdotp_not_phi2(
+; CHECK-INTERLEAVED-SAME: ptr [[MATRIX:%.*]], i32 [[N:%.*]]) #[[ATTR0]] {
+; CHECK-INTERLEAVED-NEXT: [[ENTRY:.*]]:
+; CHECK-INTERLEAVED-NEXT: [[CMP:%.*]] = icmp sgt i32 [[N]], 0
+; CHECK-INTERLEAVED-NEXT: br i1 [[CMP]], label %[[FOR_PREHEADER:.*]], label %[[EXIT:.*]]
+; CHECK-INTERLEAVED: [[FOR_PREHEADER]]:
+; CHECK-INTERLEAVED-NEXT: [[LOAD_A:%.*]] = load half, ptr null, align 1
+; CHECK-INTERLEAVED-NEXT: [[LOAD_A1:%.*]] = load half, ptr inttoptr (i64 1 to ptr), align 1
+; CHECK-INTERLEAVED-NEXT: [[A_EXT:%.*]] = fpext half [[LOAD_A]] to float
+; CHECK-INTERLEAVED-NEXT: [[A_EXT1:%.*]] = fpext half [[LOAD_A1]] to float
+; CHECK-INTERLEAVED-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64
+; CHECK-INTERLEAVED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 8
+; CHECK-INTERLEAVED-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK-INTERLEAVED: [[VECTOR_PH]]:
+; CHECK-INTERLEAVED-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 8
+; CHECK-INTERLEAVED-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]]
+; CHECK-INTERLEAVED-NEXT: [[TMP1:%.*]] = trunc i64 [[N_VEC]] to i32
+; CHECK-INTERLEAVED-NEXT: [[TMP2:%.*]] = mul i64 [[N_VEC]], 32
+; CHECK-INTERLEAVED-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[MATRIX]], i64 [[TMP2]]
+; CHECK-INTERLEAVED-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x float> poison, float [[A_EXT]], i64 0
+; CHECK-INTERLEAVED-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x float> [[BROADCAST_SPLATINSERT]], <4 x float> poison, <4 x i32> zeroinitializer
+; CHECK-INTERLEAVED-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <4 x float> poison, float [[A_EXT1]], i64 0
+; CHECK-INTERLEAVED-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x float> [[BROADCAST_SPLATINSERT1]], <4 x float> poison, <4 x i32> zeroinitializer
+; CHECK-INTERLEAVED-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-INTERLEAVED: [[VECTOR_BODY]]:
+; CHECK-INTERLEAVED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[VEC_PHI:%.*]] = phi <4 x float> [ <float 0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %[[VECTOR_PH]] ], [ [[TMP70:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[VEC_PHI3:%.*]] = phi <4 x float> [ splat (float -0.000000e+00), %[[VECTOR_PH]] ], [ [[TMP71:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 32
+; CHECK-INTERLEAVED-NEXT: [[TMP4:%.*]] = add i64 [[OFFSET_IDX]], 0
+; CHECK-INTERLEAVED-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 32
+; CHECK-INTERLEAVED-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 64
+; CHECK-INTERLEAVED-NEXT: [[TMP7:%.*]] = add i64 [[OFFSET_IDX]], 96
+; CHECK-INTERLEAVED-NEXT: [[TMP8:%.*]] = add i64 [[OFFSET_IDX]], 128
+; CHECK-INTERLEAVED-NEXT: [[TMP9:%.*]] = add i64 [[OFFSET_IDX]], 160
+; CHECK-INTERLEAVED-NEXT: [[TMP10:%.*]] = add i64 [[OFFSET_IDX]], 192
+; CHECK-INTERLEAVED-NEXT: [[TMP11:%.*]] = add i64 [[OFFSET_IDX]], 224
+; CHECK-INTERLEAVED-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[MATRIX]], i64 [[TMP4]]
+; CHECK-INTERLEAVED-NEXT: [[NEXT_GEP4:%.*]] = getelementptr i8, ptr [[MATRIX]], i64 [[TMP5]]
+; CHECK-INTERLEAVED-NEXT: [[NEXT_GEP5:%.*]] = getelementptr i8, ptr [[MATRIX]], i64 [[TMP6]]
+; CHECK-INTERLEAVED-NEXT: [[NEXT_GEP6:%.*]] = getelementptr i8, ptr [[MATRIX]], i64 [[TMP7]]
+; CHECK-INTERLEAVED-NEXT: [[NEXT_GEP7:%.*]] = getelementptr i8, ptr [[MATRIX]], i64 [[TMP8]]
+; CHECK-INTERLEAVED-NEXT: [[NEXT_GEP8:%.*]] = getelementptr i8, ptr [[MATRIX]], i64 [[TMP9]]
+; CHECK-INTERLEAVED-NEXT: [[NEXT_GEP9:%.*]] = getelementptr i8, ptr [[MATRIX]], i64 [[TMP10]]
+; CHECK-INTERLEAVED-NEXT: [[NEXT_GEP10:%.*]] = getelementptr i8, ptr [[MATRIX]], i64 [[TMP11]]
+; CHECK-INTERLEAVED-NEXT: [[TMP12:%.*]] = getelementptr half, ptr [[NEXT_GEP]], i64 1
+; CHECK-INTERLEAVED-NEXT: [[TMP13:%.*]] = getelementptr half, ptr [[NEXT_GEP4]], i64 1
+; CHECK-INTERLEAVED-NEXT: [[TMP14:%.*]] = getelementptr half, ptr [[NEXT_GEP5]], i64 1
+; CHECK-INTERLEAVED-NEXT: [[TMP15:%.*]] = getelementptr half, ptr [[NEXT_GEP6]], i64 1
+; CHECK-INTERLEAVED-NEXT: [[TMP16:%.*]] = getelementptr half, ptr [[NEXT_GEP7]], i64 1
+; CHECK-INTERLEAVED-NEXT: [[TMP17:%.*]] = getelementptr half, ptr [[NEXT_GEP8]], i64 1
+; CHECK-INTERLEAVED-NEXT: [[TMP18:%.*]] = getelementptr half, ptr [[NEXT_GEP9]], i64 1
+; CHECK-INTERLEAVED-NEXT: [[TMP19:%.*]] = getelementptr half, ptr [[NEXT_GEP10]], i64 1
+; CHECK-INTERLEAVED-NEXT: [[TMP20:%.*]] = getelementptr half, ptr [[NEXT_GEP]], i64 2
+; CHECK-INTERLEAVED-NEXT: [[TMP21:%.*]] = getelementptr half, ptr [[NEXT_GEP4]], i64 2
+; CHECK-INTERLEAVED-NEXT: [[TMP22:%.*]] = getelementptr half, ptr [[NEXT_GEP5]], i64 2
+; CHECK-INTERLEAVED-NEXT: [[TMP23:%.*]] = getelementptr half, ptr [[NEXT_GEP6]], i64 2
+; CHECK-INTERLEAVED-NEXT: [[TMP24:%.*]] = getelementptr half, ptr [[NEXT_GEP7]], i64 2
+; CHECK-INTERLEAVED-NEXT: [[TMP25:%.*]] = getelementptr half, ptr [[NEXT_GEP8]], i64 2
+; CHECK-INTERLEAVED-NEXT: [[TMP26:%.*]] = getelementptr half, ptr [[NEXT_GEP9]], i64 2
+; CHECK-INTERLEAVED-NEXT: [[TMP27:%.*]] = getelementptr half, ptr [[NEXT_GEP10]], i64 2
+; CHECK-INTERLEAVED-NEXT: [[TMP28:%.*]] = load half, ptr [[TMP12]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP29:%.*]] = load half, ptr [[TMP13]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP30:%.*]] = load half, ptr [[TMP14]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP31:%.*]] = load half, ptr [[TMP15]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP32:%.*]] = insertelement <4 x half> poison, half [[TMP28]], i32 0
+; CHECK-INTERLEAVED-NEXT: [[TMP33:%.*]] = insertelement <4 x half> [[TMP32]], half [[TMP29]], i32 1
+; CHECK-INTERLEAVED-NEXT: [[TMP34:%.*]] = insertelement <4 x half> [[TMP33]], half [[TMP30]], i32 2
+; CHECK-INTERLEAVED-NEXT: [[TMP35:%.*]] = insertelement <4 x half> [[TMP34]], half [[TMP31]], i32 3
+; CHECK-INTERLEAVED-NEXT: [[TMP36:%.*]] = load half, ptr [[TMP16]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP37:%.*]] = load half, ptr [[TMP17]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP38:%.*]] = load half, ptr [[TMP18]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP39:%.*]] = load half, ptr [[TMP19]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP40:%.*]] = insertelement <4 x half> poison, half [[TMP36]], i32 0
+; CHECK-INTERLEAVED-NEXT: [[TMP41:%.*]] = insertelement <4 x half> [[TMP40]], half [[TMP37]], i32 1
+; CHECK-INTERLEAVED-NEXT: [[TMP42:%.*]] = insertelement <4 x half> [[TMP41]], half [[TMP38]], i32 2
+; CHECK-INTERLEAVED-NEXT: [[TMP43:%.*]] = insertelement <4 x half> [[TMP42]], half [[TMP39]], i32 3
+; CHECK-INTERLEAVED-NEXT: [[TMP44:%.*]] = fpext <4 x half> [[TMP35]] to <4 x float>
+; CHECK-INTERLEAVED-NEXT: [[TMP45:%.*]] = fpext <4 x half> [[TMP43]] to <4 x float>
+; CHECK-INTERLEAVED-NEXT: [[TMP46:%.*]] = fmul <4 x float> [[BROADCAST_SPLAT]], [[TMP44]]
+; CHECK-INTERLEAVED-NEXT: [[TMP47:%.*]] = fmul <4 x float> [[BROADCAST_SPLAT]], [[TMP45]]
+; CHECK-INTERLEAVED-NEXT: [[TMP48:%.*]] = fadd reassoc <4 x float> [[TMP46]], [[VEC_PHI]]
+; CHECK-INTERLEAVED-NEXT: [[TMP49:%.*]] = fadd reassoc <4 x float> [[TMP47]], [[VEC_PHI3]]
+; CHECK-INTERLEAVED-NEXT: [[TMP50:%.*]] = load half, ptr [[TMP20]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP51:%.*]] = load half, ptr [[TMP21]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP52:%.*]] = load half, ptr [[TMP22]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP53:%.*]] = load half, ptr [[TMP23]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP54:%.*]] = insertelement <4 x half> poison, half [[TMP50]], i32 0
+; CHECK-INTERLEAVED-NEXT: [[TMP55:%.*]] = insertelement <4 x half> [[TMP54]], half [[TMP51]], i32 1
+; CHECK-INTERLEAVED-NEXT: [[TMP56:%.*]] = insertelement <4 x half> [[TMP55]], half [[TMP52]], i32 2
+; CHECK-INTERLEAVED-NEXT: [[TMP57:%.*]] = insertelement <4 x half> [[TMP56]], half [[TMP53]], i32 3
+; CHECK-INTERLEAVED-NEXT: [[TMP58:%.*]] = load half, ptr [[TMP24]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP59:%.*]] = load half, ptr [[TMP25]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP60:%.*]] = load half, ptr [[TMP26]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP61:%.*]] = load half, ptr [[TMP27]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP62:%.*]] = insertelement <4 x half> poison, half [[TMP58]], i32 0
+; CHECK-INTERLEAVED-NEXT: [[TMP63:%.*]] = insertelement <4 x half> [[TMP62]], half [[TMP59]], i32 1
+; CHECK-INTERLEAVED-NEXT: [[TMP64:%.*]] = insertelement <4 x half> [[TMP63]], half [[TMP60]], i32 2
+; CHECK-INTERLEAVED-NEXT: [[TMP65:%.*]] = insertelement <4 x half> [[TMP64]], half [[TMP61]], i32 3
+; CHECK-INTERLEAVED-NEXT: [[TMP66:%.*]] = fpext <4 x half> [[TMP57]] to <4 x float>
+; CHECK-INTERLEAVED-NEXT: [[TMP67:%.*]] = fpext <4 x half> [[TMP65]] to <4 x float>
+; CHECK-INTERLEAVED-NEXT: [[TMP68:%.*]] = fmul <4 x float> [[BROADCAST_SPLAT2]], [[TMP66]]
+; CHECK-INTERLEAVED-NEXT: [[TMP69:%.*]] = fmul <4 x float> [[BROADCAST_SPLAT2]], [[TMP67]]
+; CHECK-INTERLEAVED-NEXT: [[TMP70]] = fadd reassoc <4 x float> [[TMP68]], [[TMP48]]
+; CHECK-INTERLEAVED-NEXT: [[TMP71]] = fadd reassoc <4 x float> [[TMP69]], [[TMP49]]
+; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
+; CHECK-INTERLEAVED-NEXT: [[TMP72:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[TMP72]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
+; CHECK-INTERLEAVED: [[MIDDLE_BLOCK]]:
+; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc <4 x float> [[TMP71]], [[TMP70]]
+; CHECK-INTERLEAVED-NEXT: [[TMP73:%.*]] = call reassoc float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[BIN_RDX]])
+; CHECK-INTERLEAVED-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-INTERLEAVED: [[SCALAR_PH]]:
+; CHECK-INTERLEAVED-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[TMP1]], %[[MIDDLE_BLOCK]] ], [ 0, %[[FOR_PREHEADER]] ]
+; CHECK-INTERLEAVED-NEXT: [[BC_RESUME_VAL11:%.*]] = phi ptr [ [[TMP3]], %[[MIDDLE_BLOCK]] ], [ [[MATRIX]], %[[FOR_PREHEADER]] ]
+; CHECK-INTERLEAVED-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP73]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[FOR_PREHEADER]] ]
+; CHECK-INTERLEAVED-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-INTERLEAVED: [[FOR_BODY]]:
+; CHECK-INTERLEAVED-NEXT: [[IV:%.*]] = phi i32 [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]
+; CHECK-INTERLEAVED-NEXT: [[PTR:%.*]] = phi ptr [ [[SCEVGEP:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL11]], %[[SCALAR_PH]] ]
+; CHECK-INTERLEAVED-NEXT: [[ACCUM:%.*]] = phi float [ [[ADD_1:%.*]], %[[FOR_BODY]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ]
+; CHECK-INTERLEAVED-NEXT: [[GEP_B:%.*]] = getelementptr half, ptr [[PTR]], i64 1
+; CHECK-INTERLEAVED-NEXT: [[GEP_B1:%.*]] = getelementptr half, ptr [[PTR]], i64 2
+; CHECK-INTERLEAVED-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
+; CHECK-INTERLEAVED-NEXT: [[B_EXT:%.*]] = fpext half [[LOAD_B]] to float
+; CHECK-INTERLEAVED-NEXT: [[MUL:%.*]] = fmul float [[A_EXT]], [[B_EXT]]
+; CHECK-INTERLEAVED-NEXT: [[ADD:%.*]] = fadd reassoc float [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVED-NEXT: [[LOAD_B1:%.*]] = load half, ptr [[GEP_B1]], align 1
+; CHECK-INTERLEAVED-NEXT: [[B_EXT1:%.*]] = fpext half [[LOAD_B1]] to float
+; CHECK-INTERLEAVED-NEXT: [[MUL_1:%.*]] = fmul float [[A_EXT1]], [[B_EXT1]]
+; CHECK-INTERLEAVED-NEXT: [[ADD_1]] = fadd reassoc float [[MUL_1]], [[ADD]]
+; CHECK-INTERLEAVED-NEXT: [[SCEVGEP]] = getelementptr half, ptr [[PTR]], i64 16
+; CHECK-INTERLEAVED-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
+; CHECK-INTERLEAVED-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[IV_NEXT]], [[N]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
+; CHECK-INTERLEAVED: [[FOR_EXIT]]:
+; CHECK-INTERLEAVED-NEXT: [[ADD_FLOAT:%.*]] = phi float [ [[ADD_1]], %[[FOR_BODY]] ], [ [[TMP73]], %[[MIDDLE_BLOCK]] ]
+; CHECK-INTERLEAVED-NEXT: br label %[[EXIT]]
+; CHECK-INTERLEAVED: [[EXIT]]:
+; CHECK-INTERLEAVED-NEXT: [[RESULT:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[ADD_FLOAT]], %[[FOR_EXIT]] ]
+; CHECK-INTERLEAVED-NEXT: store float [[RESULT]], ptr [[MATRIX]], align 4
+; CHECK-INTERLEAVED-NEXT: ret void
+;
+; CHECK-MAXBW-LABEL: define void @not_fdotp_not_phi2(
+; CHECK-MAXBW-SAME: ptr [[MATRIX:%.*]], i32 [[N:%.*]]) #[[ATTR0]] {
+; CHECK-MAXBW-NEXT: [[ENTRY:.*]]:
+; CHECK-MAXBW-NEXT: [[CMP:%.*]] = icmp sgt i32 [[N]], 0
+; CHECK-MAXBW-NEXT: br i1 [[CMP]], label %[[FOR_PREHEADER:.*]], label %[[EXIT:.*]]
+; CHECK-MAXBW: [[FOR_PREHEADER]]:
+; CHECK-MAXBW-NEXT: [[LOAD_A:%.*]] = load half, ptr null, align 1
+; CHECK-MAXBW-NEXT: [[LOAD_A1:%.*]] = load half, ptr inttoptr (i64 1 to ptr), align 1
+; CHECK-MAXBW-NEXT: [[A_EXT:%.*]] = fpext half [[LOAD_A]] to float
+; CHECK-MAXBW-NEXT: [[A_EXT1:%.*]] = fpext half [[LOAD_A1]] to float
+; CHECK-MAXBW-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64
+; CHECK-MAXBW-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 4
+; CHECK-MAXBW-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK-MAXBW: [[VECTOR_PH]]:
+; CHECK-MAXBW-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 4
+; CHECK-MAXBW-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]]
+; CHECK-MAXBW-NEXT: [[TMP1:%.*]] = trunc i64 [[N_VEC]] to i32
+; CHECK-MAXBW-NEXT: [[TMP2:%.*]] = mul i64 [[N_VEC]], 32
+; CHECK-MAXBW-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[MATRIX]], i64 [[TMP2]]
+; CHECK-MAXBW-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x float> poison, float [[A_EXT]], i64 0
+; CHECK-MAXBW-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x float> [[BROADCAST_SPLATINSERT]], <4 x float> poison, <4 x i32> zeroinitializer
+; CHECK-MAXBW-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <4 x float> poison, float [[A_EXT1]], i64 0
+; CHECK-MAXBW-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x float> [[BROADCAST_SPLATINSERT1]], <4 x float> poison, <4 x i32> zeroinitializer
+; CHECK-MAXBW-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-MAXBW: [[VECTOR_BODY]]:
+; CHECK-MAXBW-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[VEC_PHI:%.*]] = phi <4 x float> [ <float 0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %[[VECTOR_PH]] ], [ [[TMP37:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 32
+; CHECK-MAXBW-NEXT: [[TMP4:%.*]] = add i64 [[OFFSET_IDX]], 0
+; CHECK-MAXBW-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 32
+; CHECK-MAXBW-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 64
+; CHECK-MAXBW-NEXT: [[TMP7:%.*]] = add i64 [[OFFSET_IDX]], 96
+; CHECK-MAXBW-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[MATRIX]], i64 [[TMP4]]
+; CHECK-MAXBW-NEXT: [[NEXT_GEP3:%.*]] = getelementptr i8, ptr [[MATRIX]], i64 [[TMP5]]
+; CHECK-MAXBW-NEXT: [[NEXT_GEP4:%.*]] = getelementptr i8, ptr [[MATRIX]], i64 [[TMP6]]
+; CHECK-MAXBW-NEXT: [[NEXT_GEP5:%.*]] = getelementptr i8, ptr [[MATRIX]], i64 [[TMP7]]
+; CHECK-MAXBW-NEXT: [[TMP8:%.*]] = getelementptr half, ptr [[NEXT_GEP]], i64 1
+; CHECK-MAXBW-NEXT: [[TMP9:%.*]] = getelementptr half, ptr [[NEXT_GEP3]], i64 1
+; CHECK-MAXBW-NEXT: [[TMP10:%.*]] = getelementptr half, ptr [[NEXT_GEP4]], i64 1
+; CHECK-MAXBW-NEXT: [[TMP11:%.*]] = getelementptr half, ptr [[NEXT_GEP5]], i64 1
+; CHECK-MAXBW-NEXT: [[TMP12:%.*]] = getelementptr half, ptr [[NEXT_GEP]], i64 2
+; CHECK-MAXBW-NEXT: [[TMP13:%.*]] = getelementptr half, ptr [[NEXT_GEP3]], i64 2
+; CHECK-MAXBW-NEXT: [[TMP14:%.*]] = getelementptr half, ptr [[NEXT_GEP4]], i64 2
+; CHECK-MAXBW-NEXT: [[TMP15:%.*]] = getelementptr half, ptr [[NEXT_GEP5]], i64 2
+; CHECK-MAXBW-NEXT: [[TMP16:%.*]] = load half, ptr [[TMP8]], align 1
+; CHECK-MAXBW-NEXT: [[TMP17:%.*]] = load half, ptr [[TMP9]], align 1
+; CHECK-MAXBW-NEXT: [[TMP18:%.*]] = load half, ptr [[TMP10]], align 1
+; CHECK-MAXBW-NEXT: [[TMP19:%.*]] = load half, ptr [[TMP11]], align 1
+; CHECK-MAXBW-NEXT: [[TMP20:%.*]] = insertelement <4 x half> poison, half [[TMP16]], i32 0
+; CHECK-MAXBW-NEXT: [[TMP21:%.*]] = insertelement <4 x half> [[TMP20]], half [[TMP17]], i32 1
+; CHECK-MAXBW-NEXT: [[TMP22:%.*]] = insertelement <4 x half> [[TMP21]], half [[TMP18]], i32 2
+; CHECK-MAXBW-NEXT: [[TMP23:%.*]] = insertelement <4 x half> [[TMP22]], half [[TMP19]], i32 3
+; CHECK-MAXBW-NEXT: [[TMP24:%.*]] = fpext <4 x half> [[TMP23]] to <4 x float>
+; CHECK-MAXBW-NEXT: [[TMP25:%.*]] = fmul <4 x float> [[BROADCAST_SPLAT]], [[TMP24]]
+; CHECK-MAXBW-NEXT: [[TMP26:%.*]] = fadd reassoc <4 x float> [[TMP25]], [[VEC_PHI]]
+; CHECK-MAXBW-NEXT: [[TMP27:%.*]] = load half, ptr [[TMP12]], align 1
+; CHECK-MAXBW-NEXT: [[TMP28:%.*]] = load half, ptr [[TMP13]], align 1
+; CHECK-MAXBW-NEXT: [[TMP29:%.*]] = load half, ptr [[TMP14]], align 1
+; CHECK-MAXBW-NEXT: [[TMP30:%.*]] = load half, ptr [[TMP15]], align 1
+; CHECK-MAXBW-NEXT: [[TMP31:%.*]] = insertelement <4 x half> poison, half [[TMP27]], i32 0
+; CHECK-MAXBW-NEXT: [[TMP32:%.*]] = insertelement <4 x half> [[TMP31]], half [[TMP28]], i32 1
+; CHECK-MAXBW-NEXT: [[TMP33:%.*]] = insertelement <4 x half> [[TMP32]], half [[TMP29]], i32 2
+; CHECK-MAXBW-NEXT: [[TMP34:%.*]] = insertelement <4 x half> [[TMP33]], half [[TMP30]], i32 3
+; CHECK-MAXBW-NEXT: [[TMP35:%.*]] = fpext <4 x half> [[TMP34]] to <4 x float>
+; CHECK-MAXBW-NEXT: [[TMP36:%.*]] = fmul <4 x float> [[BROADCAST_SPLAT2]], [[TMP35]]
+; CHECK-MAXBW-NEXT: [[TMP37]] = fadd reassoc <4 x float> [[TMP36]], [[TMP26]]
+; CHECK-MAXBW-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
+; CHECK-MAXBW-NEXT: [[TMP38:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-MAXBW-NEXT: br i1 [[TMP38]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
+; CHECK-MAXBW: [[MIDDLE_BLOCK]]:
+; CHECK-MAXBW-NEXT: [[TMP39:%.*]] = call reassoc float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[TMP37]])
+; CHECK-MAXBW-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]
+; CHECK-MAXBW-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-MAXBW: [[SCALAR_PH]]:
+; CHECK-MAXBW-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[TMP1]], %[[MIDDLE_BLOCK]] ], [ 0, %[[FOR_PREHEADER]] ]
+; CHECK-MAXBW-NEXT: [[BC_RESUME_VAL6:%.*]] = phi ptr [ [[TMP3]], %[[MIDDLE_BLOCK]] ], [ [[MATRIX]], %[[FOR_PREHEADER]] ]
+; CHECK-MAXBW-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP39]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[FOR_PREHEADER]] ]
+; CHECK-MAXBW-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-MAXBW: [[FOR_BODY]]:
+; CHECK-MAXBW-NEXT: [[IV:%.*]] = phi i32 [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]
+; CHECK-MAXBW-NEXT: [[PTR:%.*]] = phi ptr [ [[SCEVGEP:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL6]], %[[SCALAR_PH]] ]
+; CHECK-MAXBW-NEXT: [[ACCUM:%.*]] = phi float [ [[ADD_1:%.*]], %[[FOR_BODY]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ]
+; CHECK-MAXBW-NEXT: [[GEP_B:%.*]] = getelementptr half, ptr [[PTR]], i64 1
+; CHECK-MAXBW-NEXT: [[GEP_B1:%.*]] = getelementptr half, ptr [[PTR]], i64 2
+; CHECK-MAXBW-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
+; CHECK-MAXBW-NEXT: [[B_EXT:%.*]] = fpext half [[LOAD_B]] to float
+; CHECK-MAXBW-NEXT: [[MUL:%.*]] = fmul float [[A_EXT]], [[B_EXT]]
+; CHECK-MAXBW-NEXT: [[ADD:%.*]] = fadd reassoc float [[MUL]], [[ACCUM]]
+; CHECK-MAXBW-NEXT: [[LOAD_B1:%.*]] = load half, ptr [[GEP_B1]], align 1
+; CHECK-MAXBW-NEXT: [[B_EXT1:%.*]] = fpext half [[LOAD_B1]] to float
+; CHECK-MAXBW-NEXT: [[MUL_1:%.*]] = fmul float [[A_EXT1]], [[B_EXT1]]
+; CHECK-MAXBW-NEXT: [[ADD_1]] = fadd reassoc float [[MUL_1]], [[ADD]]
+; CHECK-MAXBW-NEXT: [[SCEVGEP]] = getelementptr half, ptr [[PTR]], i64 16
+; CHECK-MAXBW-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
+; CHECK-MAXBW-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[IV_NEXT]], [[N]]
+; CHECK-MAXBW-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]]
+; CHECK-MAXBW: [[FOR_EXIT]]:
+; CHECK-MAXBW-NEXT: [[ADD_FLOAT:%.*]] = phi float [ [[ADD_1]], %[[FOR_BODY]] ], [ [[TMP39]], %[[MIDDLE_BLOCK]] ]
+; CHECK-MAXBW-NEXT: br label %[[EXIT]]
+; CHECK-MAXBW: [[EXIT]]:
+; CHECK-MAXBW-NEXT: [[RESULT:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[ADD_FLOAT]], %[[FOR_EXIT]] ]
+; CHECK-MAXBW-NEXT: store float [[RESULT]], ptr [[MATRIX]], align 4
+; CHECK-MAXBW-NEXT: ret void
+;
+entry:
+ %cmp = icmp sgt i32 %n, 0
+ br i1 %cmp, label %for.preheader, label %exit
+
+for.preheader: ; preds = %entry
+ %load.a = load half, ptr inttoptr (i64 0 to ptr), align 1
+ %load.a1 = load half, ptr inttoptr (i64 1 to ptr), align 1
+ %a.ext = fpext half %load.a to float
+ %a.ext1 = fpext half %load.a1 to float
+ br label %for.body
+
+for.body: ; preds = %for.preheader, %for.body
+ %iv = phi i32 [ %iv.next, %for.body ], [ 0, %for.preheader ]
+ %ptr = phi ptr [ %scevgep, %for.body ], [ %matrix, %for.preheader ]
+ %accum = phi float [ %add.1, %for.body ], [ 0.0, %for.preheader ]
+ %gep.b = getelementptr half, ptr %ptr, i64 1
+ %gep.b1 = getelementptr half, ptr %ptr, i64 2
+ %load.b = load half, ptr %gep.b, align 1
+ %b.ext = fpext half %load.b to float
+ %mul = fmul float %a.ext, %b.ext
+ %add = fadd reassoc float %mul, %accum
+ %load.b1 = load half, ptr %gep.b1, align 1
+ %b.ext1 = fpext half %load.b1 to float
+ %mul.1 = fmul float %a.ext1, %b.ext1
+ %add.1 = fadd reassoc float %mul.1, %add
+ %scevgep = getelementptr half, ptr %ptr, i64 16
+ %iv.next = add nuw nsw i32 %iv, 1
+ %exitcond.not = icmp eq i32 %iv.next, %n
+ br i1 %exitcond.not, label %for.exit, label %for.body
+
+for.exit: ; preds = %for.body
+ %add.float = phi float [ %add.1, %for.body ]
+ br label %exit
+
+exit: ; preds = %for.exit, %entry
+ %result = phi float [ 0.000000e+00, %entry ], [ %add.float, %for.exit ]
+ store float %result, ptr %matrix, align 4
+ ret void
+}
+
+define float @not_fdotp_ext_outside_plan(ptr %a, half %b, i64 %n) #0 {
+; CHECK-INTERLEAVE1-LABEL: define float @not_fdotp_ext_outside_plan(
+; CHECK-INTERLEAVE1-SAME: ptr [[A:%.*]], half [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {
+; CHECK-INTERLEAVE1-NEXT: [[ENTRY:.*]]:
+; CHECK-INTERLEAVE1-NEXT: [[CMP:%.*]] = icmp eq i64 [[N]], 0
+; CHECK-INTERLEAVE1-NEXT: br i1 [[CMP]], label %[[EXIT:.*]], label %[[FOR_PH:.*]]
+; CHECK-INTERLEAVE1: [[FOR_PH]]:
+; CHECK-INTERLEAVE1-NEXT: [[EXT_B:%.*]] = fpext half [[B]] to float
+; CHECK-INTERLEAVE1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 8
+; CHECK-INTERLEAVE1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK-INTERLEAVE1: [[VECTOR_PH]]:
+; CHECK-INTERLEAVE1-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 8
+; CHECK-INTERLEAVE1-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
+; CHECK-INTERLEAVE1-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <8 x float> poison, float [[EXT_B]], i64 0
+; CHECK-INTERLEAVE1-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <8 x float> [[BROADCAST_SPLATINSERT]], <8 x float> poison, <8 x i32> zeroinitializer
+; CHECK-INTERLEAVE1-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-INTERLEAVE1: [[VECTOR_BODY]]:
+; CHECK-INTERLEAVE1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[VEC_PHI:%.*]] = phi <8 x float> [ <float 0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %[[VECTOR_PH]] ], [ [[TMP3:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[TMP0:%.*]] = getelementptr inbounds half, ptr [[A]], i64 [[INDEX]]
+; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD:%.*]] = load <8 x half>, ptr [[TMP0]], align 2
+; CHECK-INTERLEAVE1-NEXT: [[TMP1:%.*]] = fpext <8 x half> [[WIDE_LOAD]] to <8 x float>
+; CHECK-INTERLEAVE1-NEXT: [[TMP2:%.*]] = fmul <8 x float> [[TMP1]], [[BROADCAST_SPLAT]]
+; CHECK-INTERLEAVE1-NEXT: [[TMP3]] = fadd reassoc <8 x float> [[TMP2]], [[VEC_PHI]]
+; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
+; CHECK-INTERLEAVE1-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
+; CHECK-INTERLEAVE1: [[MIDDLE_BLOCK]]:
+; CHECK-INTERLEAVE1-NEXT: [[TMP5:%.*]] = call reassoc float @llvm.vector.reduce.fadd.v8f32(float -0.000000e+00, <8 x float> [[TMP3]])
+; CHECK-INTERLEAVE1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[CMP_N]], label %[[EXIT_LOOPEXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-INTERLEAVE1: [[SCALAR_PH]]:
+; CHECK-INTERLEAVE1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[FOR_PH]] ]
+; CHECK-INTERLEAVE1-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP5]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[FOR_PH]] ]
+; CHECK-INTERLEAVE1-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-INTERLEAVE1: [[FOR_BODY]]:
+; CHECK-INTERLEAVE1-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[ACCUM:%.*]] = phi float [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[GEP_A:%.*]] = getelementptr inbounds half, ptr [[A]], i64 [[IV]]
+; CHECK-INTERLEAVE1-NEXT: [[LOAD_A:%.*]] = load half, ptr [[GEP_A]], align 2
+; CHECK-INTERLEAVE1-NEXT: [[EXT_A:%.*]] = fpext half [[LOAD_A]] to float
+; CHECK-INTERLEAVE1-NEXT: [[MUL:%.*]] = fmul float [[EXT_A]], [[EXT_B]]
+; CHECK-INTERLEAVE1-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVE1-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-INTERLEAVE1-NEXT: [[CMP_1:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[CMP_1]], label %[[EXIT_LOOPEXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]]
+; CHECK-INTERLEAVE1: [[EXIT_LOOPEXIT]]:
+; CHECK-INTERLEAVE1-NEXT: [[ADD_LCSSA:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP5]], %[[MIDDLE_BLOCK]] ]
+; CHECK-INTERLEAVE1-NEXT: br label %[[EXIT]]
+; CHECK-INTERLEAVE1: [[EXIT]]:
+; CHECK-INTERLEAVE1-NEXT: [[RESULT:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[ADD_LCSSA]], %[[EXIT_LOOPEXIT]] ]
+; CHECK-INTERLEAVE1-NEXT: ret float [[RESULT]]
+;
+; CHECK-INTERLEAVED-LABEL: define float @not_fdotp_ext_outside_plan(
+; CHECK-INTERLEAVED-SAME: ptr [[A:%.*]], half [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {
+; CHECK-INTERLEAVED-NEXT: [[ENTRY:.*]]:
+; CHECK-INTERLEAVED-NEXT: [[CMP:%.*]] = icmp eq i64 [[N]], 0
+; CHECK-INTERLEAVED-NEXT: br i1 [[CMP]], label %[[EXIT:.*]], label %[[FOR_PH:.*]]
+; CHECK-INTERLEAVED: [[FOR_PH]]:
+; CHECK-INTERLEAVED-NEXT: [[EXT_B:%.*]] = fpext half [[B]] to float
+; CHECK-INTERLEAVED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 16
+; CHECK-INTERLEAVED-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK-INTERLEAVED: [[VECTOR_PH]]:
+; CHECK-INTERLEAVED-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 16
+; CHECK-INTERLEAVED-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
+; CHECK-INTERLEAVED-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <8 x float> poison, float [[EXT_B]], i64 0
+; CHECK-INTERLEAVED-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <8 x float> [[BROADCAST_SPLATINSERT]], <8 x float> poison, <8 x i32> zeroinitializer
+; CHECK-INTERLEAVED-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-INTERLEAVED: [[VECTOR_BODY]]:
+; CHECK-INTERLEAVED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[VEC_PHI:%.*]] = phi <8 x float> [ <float 0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %[[VECTOR_PH]] ], [ [[TMP6:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[VEC_PHI1:%.*]] = phi <8 x float> [ splat (float -0.000000e+00), %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[TMP0:%.*]] = getelementptr inbounds half, ptr [[A]], i64 [[INDEX]]
+; CHECK-INTERLEAVED-NEXT: [[TMP1:%.*]] = getelementptr inbounds half, ptr [[TMP0]], i32 8
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD:%.*]] = load <8 x half>, ptr [[TMP0]], align 2
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD2:%.*]] = load <8 x half>, ptr [[TMP1]], align 2
+; CHECK-INTERLEAVED-NEXT: [[TMP2:%.*]] = fpext <8 x half> [[WIDE_LOAD]] to <8 x float>
+; CHECK-INTERLEAVED-NEXT: [[TMP3:%.*]] = fpext <8 x half> [[WIDE_LOAD2]] to <8 x float>
+; CHECK-INTERLEAVED-NEXT: [[TMP4:%.*]] = fmul <8 x float> [[TMP2]], [[BROADCAST_SPLAT]]
+; CHECK-INTERLEAVED-NEXT: [[TMP5:%.*]] = fmul <8 x float> [[TMP3]], [[BROADCAST_SPLAT]]
+; CHECK-INTERLEAVED-NEXT: [[TMP6]] = fadd reassoc <8 x float> [[TMP4]], [[VEC_PHI]]
+; CHECK-INTERLEAVED-NEXT: [[TMP7]] = fadd reassoc <8 x float> [[TMP5]], [[VEC_PHI1]]
+; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16
+; CHECK-INTERLEAVED-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
+; CHECK-INTERLEAVED: [[MIDDLE_BLOCK]]:
+; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc <8 x float> [[TMP7]], [[TMP6]]
+; CHECK-INTERLEAVED-NEXT: [[TMP9:%.*]] = call reassoc float @llvm.vector.reduce.fadd.v8f32(float -0.000000e+00, <8 x float> [[BIN_RDX]])
+; CHECK-INTERLEAVED-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[CMP_N]], label %[[EXIT_LOOPEXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-INTERLEAVED: [[SCALAR_PH]]:
+; CHECK-INTERLEAVED-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[FOR_PH]] ]
+; CHECK-INTERLEAVED-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP9]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[FOR_PH]] ]
+; CHECK-INTERLEAVED-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-INTERLEAVED: [[FOR_BODY]]:
+; CHECK-INTERLEAVED-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[ACCUM:%.*]] = phi float [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[GEP_A:%.*]] = getelementptr inbounds half, ptr [[A]], i64 [[IV]]
+; CHECK-INTERLEAVED-NEXT: [[LOAD_A:%.*]] = load half, ptr [[GEP_A]], align 2
+; CHECK-INTERLEAVED-NEXT: [[EXT_A:%.*]] = fpext half [[LOAD_A]] to float
+; CHECK-INTERLEAVED-NEXT: [[MUL:%.*]] = fmul float [[EXT_A]], [[EXT_B]]
+; CHECK-INTERLEAVED-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVED-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-INTERLEAVED-NEXT: [[CMP_1:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[CMP_1]], label %[[EXIT_LOOPEXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]]
+; CHECK-INTERLEAVED: [[EXIT_LOOPEXIT]]:
+; CHECK-INTERLEAVED-NEXT: [[ADD_LCSSA:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP9]], %[[MIDDLE_BLOCK]] ]
+; CHECK-INTERLEAVED-NEXT: br label %[[EXIT]]
+; CHECK-INTERLEAVED: [[EXIT]]:
+; CHECK-INTERLEAVED-NEXT: [[RESULT:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[ADD_LCSSA]], %[[EXIT_LOOPEXIT]] ]
+; CHECK-INTERLEAVED-NEXT: ret float [[RESULT]]
+;
+; CHECK-MAXBW-LABEL: define float @not_fdotp_ext_outside_plan(
+; CHECK-MAXBW-SAME: ptr [[A:%.*]], half [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {
+; CHECK-MAXBW-NEXT: [[ENTRY:.*]]:
+; CHECK-MAXBW-NEXT: [[CMP:%.*]] = icmp eq i64 [[N]], 0
+; CHECK-MAXBW-NEXT: br i1 [[CMP]], label %[[EXIT:.*]], label %[[FOR_PH:.*]]
+; CHECK-MAXBW: [[FOR_PH]]:
+; CHECK-MAXBW-NEXT: [[EXT_B:%.*]] = fpext half [[B]] to float
+; CHECK-MAXBW-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-MAXBW-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 3
+; CHECK-MAXBW-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], [[TMP1]]
+; CHECK-MAXBW-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK-MAXBW: [[VECTOR_PH]]:
+; CHECK-MAXBW-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-MAXBW-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 8
+; CHECK-MAXBW-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], [[TMP3]]
+; CHECK-MAXBW-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
+; CHECK-MAXBW-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 8 x float> poison, float [[EXT_B]], i64 0
+; CHECK-MAXBW-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 8 x float> [[BROADCAST_SPLATINSERT]], <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
+; CHECK-MAXBW-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-MAXBW: [[VECTOR_BODY]]:
+; CHECK-MAXBW-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 8 x float> [ insertelement (<vscale x 8 x float> splat (float -0.000000e+00), float 0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[TMP4:%.*]] = getelementptr inbounds half, ptr [[A]], i64 [[INDEX]]
+; CHECK-MAXBW-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 8 x half>, ptr [[TMP4]], align 2
+; CHECK-MAXBW-NEXT: [[TMP5:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD]] to <vscale x 8 x float>
+; CHECK-MAXBW-NEXT: [[TMP6:%.*]] = fmul <vscale x 8 x float> [[TMP5]], [[BROADCAST_SPLAT]]
+; CHECK-MAXBW-NEXT: [[TMP7]] = fadd reassoc <vscale x 8 x float> [[TMP6]], [[VEC_PHI]]
+; CHECK-MAXBW-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
+; CHECK-MAXBW-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-MAXBW-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]
+; CHECK-MAXBW: [[MIDDLE_BLOCK]]:
+; CHECK-MAXBW-NEXT: [[TMP9:%.*]] = call reassoc float @llvm.vector.reduce.fadd.nxv8f32(float -0.000000e+00, <vscale x 8 x float> [[TMP7]])
+; CHECK-MAXBW-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
+; CHECK-MAXBW-NEXT: br i1 [[CMP_N]], label %[[EXIT_LOOPEXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-MAXBW: [[SCALAR_PH]]:
+; CHECK-MAXBW-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[FOR_PH]] ]
+; CHECK-MAXBW-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP9]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[FOR_PH]] ]
+; CHECK-MAXBW-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-MAXBW: [[FOR_BODY]]:
+; CHECK-MAXBW-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[ACCUM:%.*]] = phi float [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[FOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[GEP_A:%.*]] = getelementptr inbounds half, ptr [[A]], i64 [[IV]]
+; CHECK-MAXBW-NEXT: [[LOAD_A:%.*]] = load half, ptr [[GEP_A]], align 2
+; CHECK-MAXBW-NEXT: [[EXT_A:%.*]] = fpext half [[LOAD_A]] to float
+; CHECK-MAXBW-NEXT: [[MUL:%.*]] = fmul float [[EXT_A]], [[EXT_B]]
+; CHECK-MAXBW-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[ACCUM]]
+; CHECK-MAXBW-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-MAXBW-NEXT: [[CMP_1:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
+; CHECK-MAXBW-NEXT: br i1 [[CMP_1]], label %[[EXIT_LOOPEXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]]
+; CHECK-MAXBW: [[EXIT_LOOPEXIT]]:
+; CHECK-MAXBW-NEXT: [[ADD_LCSSA:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP9]], %[[MIDDLE_BLOCK]] ]
+; CHECK-MAXBW-NEXT: br label %[[EXIT]]
+; CHECK-MAXBW: [[EXIT]]:
+; CHECK-MAXBW-NEXT: [[RESULT:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[ADD_LCSSA]], %[[EXIT_LOOPEXIT]] ]
+; CHECK-MAXBW-NEXT: ret float [[RESULT]]
+;
+entry:
+ %cmp = icmp eq i64 %n, 0
+ br i1 %cmp, label %exit, label %for.ph
+
+for.ph: ; preds = %entry
+ %ext.b = fpext half %b to float
+ br label %for.body
+
+for.body: ; preds = %for.body.lr.ph, %for.body
+ %iv = phi i64 [ 0, %for.ph ], [ %iv.next, %for.body ]
+ %accum = phi float [ 0.0, %for.ph ], [ %add, %for.body ]
+ %gep.a = getelementptr inbounds half, ptr %a, i64 %iv
+ %load.a = load half, ptr %gep.a, align 2
+ %ext.a = fpext half %load.a to float
+ %mul = fmul float %ext.a, %ext.b
+ %add = fadd reassoc float %mul, %accum
+ %iv.next = add nuw nsw i64 %iv, 1
+ %cmp.1 = icmp eq i64 %iv.next, %n
+ br i1 %cmp.1, label %exit, label %for.body
+
+exit: ; preds = %for.cond.cleanup.loopexit, %entry
+ %result = phi float [ 0.0, %entry ], [ %add, %for.body ]
+ ret float %result
+}
+
+
+;.
+; CHECK-INTERLEAVE1: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
+; CHECK-INTERLEAVE1: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
+; CHECK-INTERLEAVE1: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
+; CHECK-INTERLEAVE1: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]], [[META2]]}
+; CHECK-INTERLEAVE1: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
+; CHECK-INTERLEAVE1: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]}
+; CHECK-INTERLEAVE1: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]}
+; CHECK-INTERLEAVE1: [[LOOP7]] = distinct !{[[LOOP7]], [[META2]], [[META1]]}
+; CHECK-INTERLEAVE1: [[LOOP8]] = distinct !{[[LOOP8]], [[META1]], [[META2]]}
+; CHECK-INTERLEAVE1: [[LOOP9]] = distinct !{[[LOOP9]], [[META2]], [[META1]]}
+;.
+; CHECK-INTERLEAVED: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
+; CHECK-INTERLEAVED: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
+; CHECK-INTERLEAVED: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
+; CHECK-INTERLEAVED: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]], [[META2]]}
+; CHECK-INTERLEAVED: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
+; CHECK-INTERLEAVED: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]}
+; CHECK-INTERLEAVED: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]}
+; CHECK-INTERLEAVED: [[LOOP7]] = distinct !{[[LOOP7]], [[META2]], [[META1]]}
+; CHECK-INTERLEAVED: [[LOOP8]] = distinct !{[[LOOP8]], [[META1]], [[META2]]}
+; CHECK-INTERLEAVED: [[LOOP9]] = distinct !{[[LOOP9]], [[META2]], [[META1]]}
+;.
+; CHECK-MAXBW: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
+; CHECK-MAXBW: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
+; CHECK-MAXBW: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
+; CHECK-MAXBW: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
+; CHECK-MAXBW: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
+; CHECK-MAXBW: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]}
+; CHECK-MAXBW: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]}
+; CHECK-MAXBW: [[LOOP7]] = distinct !{[[LOOP7]], [[META2]], [[META1]]}
+; CHECK-MAXBW: [[LOOP8]] = distinct !{[[LOOP8]], [[META1]], [[META2]]}
+; CHECK-MAXBW: [[LOOP9]] = distinct !{[[LOOP9]], [[META2]], [[META1]]}
+; CHECK-MAXBW: [[LOOP10]] = distinct !{[[LOOP10]], [[META1]], [[META2]]}
+; CHECK-MAXBW: [[LOOP11]] = distinct !{[[LOOP11]], [[META2]], [[META1]]}
+;.
>From 1fa4ff34523b794533139e49865516dbd3c445fb Mon Sep 17 00:00:00 2001
From: Damian Heaton <Damian.Heaton at arm.com>
Date: Thu, 6 Nov 2025 11:43:25 +0000
Subject: [PATCH 3/9] Remove extend cost for fdot and fix for Invalid costs
---
llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp | 8 ++++++++
llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h | 6 ++++++
2 files changed, 14 insertions(+)
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
index 9c58dc5e0132f..4cf369aeef925 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -5881,6 +5881,14 @@ InstructionCost AArch64TTIImpl::getPartialReductionCost(
return Cost;
}
+ // f16 -> f32 is natively supported for fdot
+ if (ST->isSVEorStreamingSVEAvailable() && ST->hasSVE2p1() &&
+ Opcode == Instruction::FAdd) {
+ if (AccumLT.second.getScalarType() == MVT::f32 &&
+ InputLT.second.getScalarType() == MVT::f16)
+ return Cost;
+ }
+
// Add additional cost for the extends that would need to be inserted.
return Cost + 2;
}
diff --git a/llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h b/llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
index 07dfe31eea46d..49858bf47b93c 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
+++ b/llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
@@ -533,6 +533,12 @@ m_c_Mul(const Op0_t &Op0, const Op1_t &Op1) {
return m_c_Binary<Instruction::Mul, Op0_t, Op1_t>(Op0, Op1);
}
+template <typename Op0_t, typename Op1_t>
+inline AllRecipe_match<Instruction::FMul, Op0_t, Op1_t>
+m_FMul(const Op0_t &Op0, const Op1_t &Op1) {
+ return m_Binary<Instruction::FMul, Op0_t, Op1_t>(Op0, Op1);
+}
+
/// Match a binary AND operation.
template <typename Op0_t, typename Op1_t>
inline AllRecipe_commutative_match<Instruction::And, Op0_t, Op1_t>
>From 2bf7669232ba53e764dae0917fea3d01faf5a5c0 Mon Sep 17 00:00:00 2001
From: Damian Heaton <Damian.Heaton at arm.com>
Date: Thu, 6 Nov 2025 14:03:02 +0000
Subject: [PATCH 4/9] Remove global check lines & correct feature check
---
.../AArch64/AArch64TargetTransformInfo.cpp | 3 +-
.../AArch64/partial-reduce-fdot-product.ll | 38 -------------------
2 files changed, 1 insertion(+), 40 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
index 4cf369aeef925..fd2b608df51a0 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -5882,8 +5882,7 @@ InstructionCost AArch64TTIImpl::getPartialReductionCost(
}
// f16 -> f32 is natively supported for fdot
- if (ST->isSVEorStreamingSVEAvailable() && ST->hasSVE2p1() &&
- Opcode == Instruction::FAdd) {
+ if (Opcode == Instruction::FAdd && (ST->hasSME2() || ST->hasSVE2p1())) {
if (AccumLT.second.getScalarType() == MVT::f32 &&
InputLT.second.getScalarType() == MVT::f16)
return Cost;
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fdot-product.ll b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fdot-product.ll
index b36ccbfdb2086..a82a60d2039c9 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fdot-product.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fdot-product.ll
@@ -1119,41 +1119,3 @@ exit: ; preds = %for.cond.cleanup.loopexit, %ent
%result = phi float [ 0.0, %entry ], [ %add, %for.body ]
ret float %result
}
-
-
-;.
-; CHECK-INTERLEAVE1: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
-; CHECK-INTERLEAVE1: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
-; CHECK-INTERLEAVE1: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
-; CHECK-INTERLEAVE1: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]], [[META2]]}
-; CHECK-INTERLEAVE1: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
-; CHECK-INTERLEAVE1: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]}
-; CHECK-INTERLEAVE1: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]}
-; CHECK-INTERLEAVE1: [[LOOP7]] = distinct !{[[LOOP7]], [[META2]], [[META1]]}
-; CHECK-INTERLEAVE1: [[LOOP8]] = distinct !{[[LOOP8]], [[META1]], [[META2]]}
-; CHECK-INTERLEAVE1: [[LOOP9]] = distinct !{[[LOOP9]], [[META2]], [[META1]]}
-;.
-; CHECK-INTERLEAVED: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
-; CHECK-INTERLEAVED: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
-; CHECK-INTERLEAVED: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
-; CHECK-INTERLEAVED: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]], [[META2]]}
-; CHECK-INTERLEAVED: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
-; CHECK-INTERLEAVED: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]}
-; CHECK-INTERLEAVED: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]}
-; CHECK-INTERLEAVED: [[LOOP7]] = distinct !{[[LOOP7]], [[META2]], [[META1]]}
-; CHECK-INTERLEAVED: [[LOOP8]] = distinct !{[[LOOP8]], [[META1]], [[META2]]}
-; CHECK-INTERLEAVED: [[LOOP9]] = distinct !{[[LOOP9]], [[META2]], [[META1]]}
-;.
-; CHECK-MAXBW: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
-; CHECK-MAXBW: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
-; CHECK-MAXBW: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
-; CHECK-MAXBW: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
-; CHECK-MAXBW: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
-; CHECK-MAXBW: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]}
-; CHECK-MAXBW: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]}
-; CHECK-MAXBW: [[LOOP7]] = distinct !{[[LOOP7]], [[META2]], [[META1]]}
-; CHECK-MAXBW: [[LOOP8]] = distinct !{[[LOOP8]], [[META1]], [[META2]]}
-; CHECK-MAXBW: [[LOOP9]] = distinct !{[[LOOP9]], [[META2]], [[META1]]}
-; CHECK-MAXBW: [[LOOP10]] = distinct !{[[LOOP10]], [[META1]], [[META2]]}
-; CHECK-MAXBW: [[LOOP11]] = distinct !{[[LOOP11]], [[META2]], [[META1]]}
-;.
>From 179f3cbe9fd95682852b00646cde10f44507dce4 Mon Sep 17 00:00:00 2001
From: Damian Heaton <Damian.Heaton at arm.com>
Date: Mon, 17 Nov 2025 15:49:22 +0000
Subject: [PATCH 5/9] Fix formatting and refine tests
---
.../Transforms/Vectorize/LoopVectorize.cpp | 1 +
.../AArch64/partial-reduce-fdot-product.ll | 1637 ++++++++++++++---
2 files changed, 1428 insertions(+), 210 deletions(-)
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index b166b4a4aacff..351a4a2fea5b4 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -8301,6 +8301,7 @@ VPRecipeBuilder::tryToCreatePartialReduction(VPInstruction *Reduction,
vputils::getVFScaleFactor(Accumulator->getDefiningRecipe()) &&
"all accumulators in chain must have same scale factor");
+ unsigned ReductionOpcode = Reduction->getOpcode();
auto *ReductionI = Reduction->getUnderlyingInstr();
if (Reduction->getOpcode() == Instruction::FAdd &&
!ReductionI->hasAllowReassoc())
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fdot-product.ll b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fdot-product.ll
index a82a60d2039c9..8536cca61d164 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fdot-product.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fdot-product.ll
@@ -6,8 +6,8 @@
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-none-unknown-elf"
-define float @fdotp(ptr %a, ptr %b) #0 {
-; CHECK-INTERLEAVE1-LABEL: define float @fdotp(
+define float @fdotp_f16_f32(ptr %a, ptr %b) #0 {
+; CHECK-INTERLEAVE1-LABEL: define float @fdotp_f16_f32(
; CHECK-INTERLEAVE1-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-INTERLEAVE1-NEXT: [[ENTRY:.*]]:
; CHECK-INTERLEAVE1-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64()
@@ -27,172 +27,957 @@ define float @fdotp(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 2 x half>, ptr [[TMP0]], align 1
; CHECK-INTERLEAVE1-NEXT: [[TMP5:%.*]] = fpext <vscale x 2 x half> [[WIDE_LOAD]] to <vscale x 2 x float>
; CHECK-INTERLEAVE1-NEXT: [[TMP2:%.*]] = getelementptr half, ptr [[B]], i64 [[INDEX]]
-; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 2 x half>, ptr [[TMP2]], align 1
-; CHECK-INTERLEAVE1-NEXT: [[TMP13:%.*]] = fpext <vscale x 2 x half> [[WIDE_LOAD1]] to <vscale x 2 x float>
-; CHECK-INTERLEAVE1-NEXT: [[TMP8:%.*]] = fmul <vscale x 2 x float> [[TMP13]], [[TMP5]]
-; CHECK-INTERLEAVE1-NEXT: [[TMP9]] = fadd reassoc <vscale x 2 x float> [[TMP8]], [[VEC_PHI]]
-; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT1]] = add nuw i64 [[INDEX]], [[TMP3]]
-; CHECK-INTERLEAVE1-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT1]], [[N_VEC]]
-; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD1:%.*]] = load <8 x half>, ptr [[TMP2]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP3:%.*]] = fpext <8 x half> [[WIDE_LOAD1]] to <8 x float>
+; CHECK-INTERLEAVE1-NEXT: [[TMP4:%.*]] = fmul <8 x float> [[TMP3]], [[TMP1]]
+; CHECK-INTERLEAVE1-NEXT: [[PARTIAL_REDUCE]] = call <4 x float> @llvm.vector.partial.reduce.fadd.v4f32.v8f32(<4 x float> [[VEC_PHI]], <8 x float> [[TMP4]])
+; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
+; CHECK-INTERLEAVE1-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
+; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK-INTERLEAVE1: [[MIDDLE_BLOCK]]:
+; CHECK-INTERLEAVE1-NEXT: [[TMP6:%.*]] = call reassoc float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[PARTIAL_REDUCE]])
+; CHECK-INTERLEAVE1-NEXT: br label %[[FOR_EXIT:.*]]
+; CHECK-INTERLEAVE1: [[FOR_EXIT]]:
+; CHECK-INTERLEAVE1-NEXT: ret float [[TMP6]]
+;
+; CHECK-INTERLEAVED-LABEL: define float @fdotp_f16_f32(
+; CHECK-INTERLEAVED-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-INTERLEAVED-NEXT: [[ENTRY:.*]]:
+; CHECK-INTERLEAVED-NEXT: [[TMP10:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVED-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP10]], 2
+; CHECK-INTERLEAVED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK-INTERLEAVED: [[VECTOR_PH]]:
+; CHECK-INTERLEAVED-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVED-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 4
+; CHECK-INTERLEAVED-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
+; CHECK-INTERLEAVED-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
+; CHECK-INTERLEAVED-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-INTERLEAVED: [[VECTOR_BODY]]:
+; CHECK-INTERLEAVED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT1:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 2 x float> [ insertelement (<vscale x 2 x float> splat (float -0.000000e+00), float 0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[TMP18:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[VEC_PHI1:%.*]] = phi <vscale x 2 x float> [ splat (float -0.000000e+00), %[[VECTOR_PH]] ], [ [[TMP19:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[TMP0:%.*]] = getelementptr half, ptr [[A]], i64 [[INDEX]]
+; CHECK-INTERLEAVED-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVED-NEXT: [[TMP6:%.*]] = shl nuw i64 [[TMP5]], 1
+; CHECK-INTERLEAVED-NEXT: [[TMP7:%.*]] = getelementptr half, ptr [[TMP0]], i64 [[TMP6]]
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 2 x half>, ptr [[TMP0]], align 1
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD2:%.*]] = load <vscale x 2 x half>, ptr [[TMP7]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP8:%.*]] = fpext <vscale x 2 x half> [[WIDE_LOAD]] to <vscale x 2 x float>
+; CHECK-INTERLEAVED-NEXT: [[TMP9:%.*]] = fpext <vscale x 2 x half> [[WIDE_LOAD2]] to <vscale x 2 x float>
+; CHECK-INTERLEAVED-NEXT: [[TMP4:%.*]] = getelementptr half, ptr [[B]], i64 [[INDEX]]
+; CHECK-INTERLEAVED-NEXT: [[TMP5:%.*]] = getelementptr half, ptr [[TMP4]], i32 8
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD3:%.*]] = load <8 x half>, ptr [[TMP4]], align 1
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD4:%.*]] = load <8 x half>, ptr [[TMP5]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP6:%.*]] = fpext <8 x half> [[WIDE_LOAD3]] to <8 x float>
+; CHECK-INTERLEAVED-NEXT: [[TMP7:%.*]] = fpext <8 x half> [[WIDE_LOAD4]] to <8 x float>
+; CHECK-INTERLEAVED-NEXT: [[TMP8:%.*]] = fmul <8 x float> [[TMP6]], [[TMP2]]
+; CHECK-INTERLEAVED-NEXT: [[TMP9:%.*]] = fmul <8 x float> [[TMP7]], [[TMP3]]
+; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE]] = call <4 x float> @llvm.vector.partial.reduce.fadd.v4f32.v8f32(<4 x float> [[VEC_PHI]], <8 x float> [[TMP8]])
+; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE5]] = call <4 x float> @llvm.vector.partial.reduce.fadd.v4f32.v8f32(<4 x float> [[VEC_PHI1]], <8 x float> [[TMP9]])
+; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16
+; CHECK-INTERLEAVED-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
+; CHECK-INTERLEAVED-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK-INTERLEAVED: [[MIDDLE_BLOCK]]:
+; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc <vscale x 2 x float> [[TMP19]], [[TMP18]]
+; CHECK-INTERLEAVED-NEXT: [[TMP21:%.*]] = call reassoc float @llvm.vector.reduce.fadd.nxv2f32(float -0.000000e+00, <vscale x 2 x float> [[BIN_RDX]])
+; CHECK-INTERLEAVED-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-INTERLEAVED: [[SCALAR_PH]]:
+; CHECK-INTERLEAVED-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-INTERLEAVED-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP21]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
+; CHECK-INTERLEAVED-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-INTERLEAVED: [[FOR_BODY]]:
+; CHECK-INTERLEAVED-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[ACCUM:%.*]] = phi float [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[GEP_A:%.*]] = getelementptr half, ptr [[A]], i64 [[IV]]
+; CHECK-INTERLEAVED-NEXT: [[LOAD_A:%.*]] = load half, ptr [[GEP_A]], align 1
+; CHECK-INTERLEAVED-NEXT: [[EXT_A:%.*]] = fpext half [[LOAD_A]] to float
+; CHECK-INTERLEAVED-NEXT: [[GEP_B:%.*]] = getelementptr half, ptr [[B]], i64 [[IV]]
+; CHECK-INTERLEAVED-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
+; CHECK-INTERLEAVED-NEXT: [[EXT_B:%.*]] = fpext half [[LOAD_B]] to float
+; CHECK-INTERLEAVED-NEXT: [[MUL:%.*]] = fmul float [[EXT_B]], [[EXT_A]]
+; CHECK-INTERLEAVED-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add i64 [[IV]], 1
+; CHECK-INTERLEAVED-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
+; CHECK-INTERLEAVED-NEXT: br i1 [[TMP12]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK-INTERLEAVED: [[FOR_EXIT]]:
+; CHECK-INTERLEAVED-NEXT: [[TMP11:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP21]], %[[MIDDLE_BLOCK]] ]
+; CHECK-INTERLEAVED-NEXT: ret float [[TMP11]]
+;
+; CHECK-MAXBW-LABEL: define float @fdotp_f16_f32(
+; CHECK-MAXBW-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-MAXBW-NEXT: [[ENTRY:.*]]:
+; CHECK-MAXBW-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-MAXBW-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 3
+; CHECK-MAXBW-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
+; CHECK-MAXBW-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK-MAXBW: [[VECTOR_PH]]:
+; CHECK-MAXBW-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-MAXBW-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 8
+; CHECK-MAXBW-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
+; CHECK-MAXBW-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
+; CHECK-MAXBW-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-MAXBW: [[VECTOR_BODY]]:
+; CHECK-MAXBW-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x float> [ insertelement (<vscale x 4 x float> splat (float -0.000000e+00), float 0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[TMP4:%.*]] = getelementptr half, ptr [[A]], i64 [[INDEX]]
+; CHECK-MAXBW-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 8 x half>, ptr [[TMP4]], align 1
+; CHECK-MAXBW-NEXT: [[TMP5:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD]] to <vscale x 8 x float>
+; CHECK-MAXBW-NEXT: [[TMP6:%.*]] = getelementptr half, ptr [[B]], i64 [[INDEX]]
+; CHECK-MAXBW-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 8 x half>, ptr [[TMP6]], align 1
+; CHECK-MAXBW-NEXT: [[TMP7:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD1]] to <vscale x 8 x float>
+; CHECK-MAXBW-NEXT: [[TMP8:%.*]] = fmul <vscale x 8 x float> [[TMP7]], [[TMP5]]
+; CHECK-MAXBW-NEXT: [[PARTIAL_REDUCE]] = call <vscale x 4 x float> @llvm.vector.partial.reduce.fadd.nxv4f32.nxv8f32(<vscale x 4 x float> [[VEC_PHI]], <vscale x 8 x float> [[TMP8]])
+; CHECK-MAXBW-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
+; CHECK-MAXBW-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-MAXBW-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK-MAXBW: [[MIDDLE_BLOCK]]:
+; CHECK-MAXBW-NEXT: [[TMP11:%.*]] = call reassoc float @llvm.vector.reduce.fadd.nxv2f32(float -0.000000e+00, <vscale x 2 x float> [[TMP10]])
+; CHECK-MAXBW-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
+; CHECK-MAXBW-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-MAXBW: [[SCALAR_PH]]:
+; CHECK-MAXBW-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-MAXBW-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP11]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
+; CHECK-MAXBW-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-MAXBW: [[FOR_BODY]]:
+; CHECK-MAXBW-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[ACCUM:%.*]] = phi float [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[FOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[GEP_A:%.*]] = getelementptr half, ptr [[A]], i64 [[IV]]
+; CHECK-MAXBW-NEXT: [[LOAD_A:%.*]] = load half, ptr [[GEP_A]], align 1
+; CHECK-MAXBW-NEXT: [[EXT_A:%.*]] = fpext half [[LOAD_A]] to float
+; CHECK-MAXBW-NEXT: [[GEP_B:%.*]] = getelementptr half, ptr [[B]], i64 [[IV]]
+; CHECK-MAXBW-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
+; CHECK-MAXBW-NEXT: [[EXT_B:%.*]] = fpext half [[LOAD_B]] to float
+; CHECK-MAXBW-NEXT: [[MUL:%.*]] = fmul float [[EXT_B]], [[EXT_A]]
+; CHECK-MAXBW-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[ACCUM]]
+; CHECK-MAXBW-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-MAXBW-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
+; CHECK-MAXBW-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK-MAXBW: [[FOR_EXIT]]:
+; CHECK-MAXBW-NEXT: [[ADD_LCSSA:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP11]], %[[MIDDLE_BLOCK]] ]
+; CHECK-MAXBW-NEXT: ret float [[ADD_LCSSA]]
+;
+; CHECK-INTERLEAVE1-SVE2P1-LABEL: define float @fdotp_f16_f32(
+; CHECK-INTERLEAVE1-SVE2P1-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ENTRY:.*:]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br label %[[VECTOR_PH:.*]]
+; CHECK-INTERLEAVE1-SVE2P1: [[VECTOR_PH]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-INTERLEAVE1-SVE2P1: [[VECTOR_BODY]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[VEC_PHI:%.*]] = phi <4 x float> [ <float 0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP0:%.*]] = getelementptr half, ptr [[A]], i64 [[INDEX]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[WIDE_LOAD:%.*]] = load <8 x half>, ptr [[TMP0]], align 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP1:%.*]] = fpext <8 x half> [[WIDE_LOAD]] to <8 x float>
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP2:%.*]] = getelementptr half, ptr [[B]], i64 [[INDEX]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[WIDE_LOAD1:%.*]] = load <8 x half>, ptr [[TMP2]], align 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP3:%.*]] = fpext <8 x half> [[WIDE_LOAD1]] to <8 x float>
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP4:%.*]] = fmul <8 x float> [[TMP3]], [[TMP1]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[PARTIAL_REDUCE]] = call <4 x float> @llvm.vector.partial.reduce.fadd.v4f32.v8f32(<4 x float> [[VEC_PHI]], <8 x float> [[TMP4]])
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK-INTERLEAVE1-SVE2P1: [[MIDDLE_BLOCK]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP6:%.*]] = call reassoc float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[PARTIAL_REDUCE]])
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br label %[[FOR_EXIT:.*]]
+; CHECK-INTERLEAVE1-SVE2P1: [[FOR_EXIT]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: ret float [[TMP6]]
+entry:
+ br label %for.body
+
+for.body: ; preds = %for.body, %entry
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+ %accum = phi float [ 0.0, %entry ], [ %add, %for.body ]
+ %gep.a = getelementptr half, ptr %a, i64 %iv
+ %load.a = load half, ptr %gep.a, align 1
+ %ext.a = fpext half %load.a to float
+ %gep.b = getelementptr half, ptr %b, i64 %iv
+ %load.b = load half, ptr %gep.b, align 1
+ %ext.b = fpext half %load.b to float
+ %mul = fmul float %ext.b, %ext.a
+ %add = fadd reassoc float %mul, %accum
+ %iv.next = add i64 %iv, 1
+ %exitcond.not = icmp eq i64 %iv.next, 1024
+ br i1 %exitcond.not, label %for.exit, label %for.body
+
+for.exit: ; preds = %for.body
+ ret float %add
+}
+
+define double @fdotp_f16_f64(ptr %a, ptr %b) #0 {
+; CHECK-INTERLEAVE1-LABEL: define double @fdotp_f16_f64(
+; CHECK-INTERLEAVE1-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
+; CHECK-INTERLEAVE1-NEXT: [[ENTRY:.*:]]
+; CHECK-INTERLEAVE1-NEXT: br label %[[VECTOR_PH:.*]]
+; CHECK-INTERLEAVE1: [[VECTOR_PH]]:
+; CHECK-INTERLEAVE1-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-INTERLEAVE1: [[VECTOR_BODY]]:
+; CHECK-INTERLEAVE1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[VEC_PHI:%.*]] = phi <2 x double> [ <double 0.000000e+00, double -0.000000e+00>, %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[TMP0:%.*]] = getelementptr half, ptr [[A]], i64 [[INDEX]]
+; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD:%.*]] = load <8 x half>, ptr [[TMP0]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP1:%.*]] = fpext <8 x half> [[WIDE_LOAD]] to <8 x double>
+; CHECK-INTERLEAVE1-NEXT: [[TMP2:%.*]] = getelementptr half, ptr [[B]], i64 [[INDEX]]
+; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD1:%.*]] = load <8 x half>, ptr [[TMP2]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP3:%.*]] = fpext <8 x half> [[WIDE_LOAD1]] to <8 x double>
+; CHECK-INTERLEAVE1-NEXT: [[TMP4:%.*]] = fmul <8 x double> [[TMP3]], [[TMP1]]
+; CHECK-INTERLEAVE1-NEXT: [[PARTIAL_REDUCE]] = call <2 x double> @llvm.vector.partial.reduce.fadd.v2f64.v8f64(<2 x double> [[VEC_PHI]], <8 x double> [[TMP4]])
+; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
+; CHECK-INTERLEAVE1-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
+; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK-INTERLEAVE1: [[MIDDLE_BLOCK]]:
+; CHECK-INTERLEAVE1-NEXT: [[TMP6:%.*]] = call reassoc double @llvm.vector.reduce.fadd.v2f64(double -0.000000e+00, <2 x double> [[PARTIAL_REDUCE]])
+; CHECK-INTERLEAVE1-NEXT: br label %[[FOR_EXIT:.*]]
+; CHECK-INTERLEAVE1: [[FOR_EXIT]]:
+; CHECK-INTERLEAVE1-NEXT: ret double [[TMP6]]
+;
+; CHECK-INTERLEAVED-LABEL: define double @fdotp_f16_f64(
+; CHECK-INTERLEAVED-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
+; CHECK-INTERLEAVED-NEXT: [[ENTRY:.*:]]
+; CHECK-INTERLEAVED-NEXT: br label %[[VECTOR_PH:.*]]
+; CHECK-INTERLEAVED: [[VECTOR_PH]]:
+; CHECK-INTERLEAVED-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-INTERLEAVED: [[VECTOR_BODY]]:
+; CHECK-INTERLEAVED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[VEC_PHI:%.*]] = phi <2 x double> [ <double 0.000000e+00, double -0.000000e+00>, %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[VEC_PHI1:%.*]] = phi <2 x double> [ splat (double -0.000000e+00), %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE5:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[TMP0:%.*]] = getelementptr half, ptr [[A]], i64 [[INDEX]]
+; CHECK-INTERLEAVED-NEXT: [[TMP1:%.*]] = getelementptr half, ptr [[TMP0]], i32 8
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD:%.*]] = load <8 x half>, ptr [[TMP0]], align 1
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD2:%.*]] = load <8 x half>, ptr [[TMP1]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP2:%.*]] = fpext <8 x half> [[WIDE_LOAD]] to <8 x double>
+; CHECK-INTERLEAVED-NEXT: [[TMP3:%.*]] = fpext <8 x half> [[WIDE_LOAD2]] to <8 x double>
+; CHECK-INTERLEAVED-NEXT: [[TMP4:%.*]] = getelementptr half, ptr [[B]], i64 [[INDEX]]
+; CHECK-INTERLEAVED-NEXT: [[TMP5:%.*]] = getelementptr half, ptr [[TMP4]], i32 8
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD3:%.*]] = load <8 x half>, ptr [[TMP4]], align 1
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD4:%.*]] = load <8 x half>, ptr [[TMP5]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP6:%.*]] = fpext <8 x half> [[WIDE_LOAD3]] to <8 x double>
+; CHECK-INTERLEAVED-NEXT: [[TMP7:%.*]] = fpext <8 x half> [[WIDE_LOAD4]] to <8 x double>
+; CHECK-INTERLEAVED-NEXT: [[TMP8:%.*]] = fmul <8 x double> [[TMP6]], [[TMP2]]
+; CHECK-INTERLEAVED-NEXT: [[TMP9:%.*]] = fmul <8 x double> [[TMP7]], [[TMP3]]
+; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE]] = call <2 x double> @llvm.vector.partial.reduce.fadd.v2f64.v8f64(<2 x double> [[VEC_PHI]], <8 x double> [[TMP8]])
+; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE5]] = call <2 x double> @llvm.vector.partial.reduce.fadd.v2f64.v8f64(<2 x double> [[VEC_PHI1]], <8 x double> [[TMP9]])
+; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16
+; CHECK-INTERLEAVED-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
+; CHECK-INTERLEAVED-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK-INTERLEAVED: [[MIDDLE_BLOCK]]:
+; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc <2 x double> [[PARTIAL_REDUCE5]], [[PARTIAL_REDUCE]]
+; CHECK-INTERLEAVED-NEXT: [[TMP11:%.*]] = call reassoc double @llvm.vector.reduce.fadd.v2f64(double -0.000000e+00, <2 x double> [[BIN_RDX]])
+; CHECK-INTERLEAVED-NEXT: br label %[[FOR_EXIT:.*]]
+; CHECK-INTERLEAVED: [[FOR_EXIT]]:
+; CHECK-INTERLEAVED-NEXT: ret double [[TMP11]]
+;
+; CHECK-MAXBW-LABEL: define double @fdotp_f16_f64(
+; CHECK-MAXBW-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
+; CHECK-MAXBW-NEXT: [[ENTRY:.*]]:
+; CHECK-MAXBW-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-MAXBW-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 3
+; CHECK-MAXBW-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
+; CHECK-MAXBW-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK-MAXBW: [[VECTOR_PH]]:
+; CHECK-MAXBW-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-MAXBW-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 8
+; CHECK-MAXBW-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
+; CHECK-MAXBW-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
+; CHECK-MAXBW-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-MAXBW: [[VECTOR_BODY]]:
+; CHECK-MAXBW-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 2 x double> [ insertelement (<vscale x 2 x double> splat (double -0.000000e+00), double 0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[TMP4:%.*]] = getelementptr half, ptr [[A]], i64 [[INDEX]]
+; CHECK-MAXBW-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 8 x half>, ptr [[TMP4]], align 1
+; CHECK-MAXBW-NEXT: [[TMP5:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD]] to <vscale x 8 x double>
+; CHECK-MAXBW-NEXT: [[TMP6:%.*]] = getelementptr half, ptr [[B]], i64 [[INDEX]]
+; CHECK-MAXBW-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 8 x half>, ptr [[TMP6]], align 1
+; CHECK-MAXBW-NEXT: [[TMP7:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD1]] to <vscale x 8 x double>
+; CHECK-MAXBW-NEXT: [[TMP8:%.*]] = fmul <vscale x 8 x double> [[TMP7]], [[TMP5]]
+; CHECK-MAXBW-NEXT: [[PARTIAL_REDUCE]] = call <vscale x 2 x double> @llvm.vector.partial.reduce.fadd.nxv2f64.nxv8f64(<vscale x 2 x double> [[VEC_PHI]], <vscale x 8 x double> [[TMP8]])
+; CHECK-MAXBW-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
+; CHECK-MAXBW-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-MAXBW-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; CHECK-MAXBW: [[MIDDLE_BLOCK]]:
+; CHECK-MAXBW-NEXT: [[TMP10:%.*]] = call reassoc double @llvm.vector.reduce.fadd.nxv2f64(double -0.000000e+00, <vscale x 2 x double> [[PARTIAL_REDUCE]])
+; CHECK-MAXBW-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
+; CHECK-MAXBW-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-MAXBW: [[SCALAR_PH]]:
+; CHECK-MAXBW-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-MAXBW-NEXT: [[BC_MERGE_RDX:%.*]] = phi double [ [[TMP10]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
+; CHECK-MAXBW-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-MAXBW: [[FOR_BODY]]:
+; CHECK-MAXBW-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[ACCUM:%.*]] = phi double [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[FOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[GEP_A:%.*]] = getelementptr half, ptr [[A]], i64 [[IV]]
+; CHECK-MAXBW-NEXT: [[LOAD_A:%.*]] = load half, ptr [[GEP_A]], align 1
+; CHECK-MAXBW-NEXT: [[EXT_A:%.*]] = fpext half [[LOAD_A]] to double
+; CHECK-MAXBW-NEXT: [[GEP_B:%.*]] = getelementptr half, ptr [[B]], i64 [[IV]]
+; CHECK-MAXBW-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
+; CHECK-MAXBW-NEXT: [[EXT_B:%.*]] = fpext half [[LOAD_B]] to double
+; CHECK-MAXBW-NEXT: [[MUL:%.*]] = fmul double [[EXT_B]], [[EXT_A]]
+; CHECK-MAXBW-NEXT: [[ADD]] = fadd reassoc double [[MUL]], [[ACCUM]]
+; CHECK-MAXBW-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-MAXBW-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
+; CHECK-MAXBW-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
+; CHECK-MAXBW: [[FOR_EXIT]]:
+; CHECK-MAXBW-NEXT: [[ADD_LCSSA:%.*]] = phi double [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP10]], %[[MIDDLE_BLOCK]] ]
+; CHECK-MAXBW-NEXT: ret double [[ADD_LCSSA]]
+;
+; CHECK-INTERLEAVE1-SVE2P1-LABEL: define double @fdotp_f16_f64(
+; CHECK-INTERLEAVE1-SVE2P1-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ENTRY:.*:]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br label %[[VECTOR_PH:.*]]
+; CHECK-INTERLEAVE1-SVE2P1: [[VECTOR_PH]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-INTERLEAVE1-SVE2P1: [[VECTOR_BODY]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[VEC_PHI:%.*]] = phi <2 x double> [ <double 0.000000e+00, double -0.000000e+00>, %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP0:%.*]] = getelementptr half, ptr [[A]], i64 [[INDEX]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[WIDE_LOAD:%.*]] = load <8 x half>, ptr [[TMP0]], align 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP1:%.*]] = fpext <8 x half> [[WIDE_LOAD]] to <8 x double>
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP2:%.*]] = getelementptr half, ptr [[B]], i64 [[INDEX]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[WIDE_LOAD1:%.*]] = load <8 x half>, ptr [[TMP2]], align 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP3:%.*]] = fpext <8 x half> [[WIDE_LOAD1]] to <8 x double>
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP4:%.*]] = fmul <8 x double> [[TMP3]], [[TMP1]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[PARTIAL_REDUCE]] = call <2 x double> @llvm.vector.partial.reduce.fadd.v2f64.v8f64(<2 x double> [[VEC_PHI]], <8 x double> [[TMP4]])
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK-INTERLEAVE1-SVE2P1: [[MIDDLE_BLOCK]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP6:%.*]] = call reassoc double @llvm.vector.reduce.fadd.v2f64(double -0.000000e+00, <2 x double> [[PARTIAL_REDUCE]])
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br label %[[FOR_EXIT:.*]]
+; CHECK-INTERLEAVE1-SVE2P1: [[FOR_EXIT]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: ret double [[TMP6]]
+entry:
+ br label %for.body
+
+for.body: ; preds = %for.body, %entry
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+ %accum = phi double [ 0.0, %entry ], [ %add, %for.body ]
+ %gep.a = getelementptr half, ptr %a, i64 %iv
+ %load.a = load half, ptr %gep.a, align 1
+ %ext.a = fpext half %load.a to double
+ %gep.b = getelementptr half, ptr %b, i64 %iv
+ %load.b = load half, ptr %gep.b, align 1
+ %ext.b = fpext half %load.b to double
+ %mul = fmul double %ext.b, %ext.a
+ %add = fadd reassoc double %mul, %accum
+ %iv.next = add i64 %iv, 1
+ %exitcond.not = icmp eq i64 %iv.next, 1024
+ br i1 %exitcond.not, label %for.exit, label %for.body
+
+for.exit: ; preds = %for.body
+ ret double %add
+}
+
+define double @fdotp_f32_f64(ptr %a, ptr %b) #0 {
+; CHECK-INTERLEAVE1-LABEL: define double @fdotp_f32_f64(
+; CHECK-INTERLEAVE1-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
+; CHECK-INTERLEAVE1-NEXT: [[ENTRY:.*:]]
+; CHECK-INTERLEAVE1-NEXT: br label %[[VECTOR_PH:.*]]
+; CHECK-INTERLEAVE1: [[VECTOR_PH]]:
+; CHECK-INTERLEAVE1-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-INTERLEAVE1: [[VECTOR_BODY]]:
+; CHECK-INTERLEAVE1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[VEC_PHI:%.*]] = phi <2 x double> [ <double 0.000000e+00, double -0.000000e+00>, %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[TMP0:%.*]] = getelementptr float, ptr [[A]], i64 [[INDEX]]
+; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP0]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP1:%.*]] = fpext <4 x float> [[WIDE_LOAD]] to <4 x double>
+; CHECK-INTERLEAVE1-NEXT: [[TMP2:%.*]] = getelementptr float, ptr [[B]], i64 [[INDEX]]
+; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x float>, ptr [[TMP2]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP3:%.*]] = fpext <4 x float> [[WIDE_LOAD1]] to <4 x double>
+; CHECK-INTERLEAVE1-NEXT: [[TMP4:%.*]] = fmul <4 x double> [[TMP3]], [[TMP1]]
+; CHECK-INTERLEAVE1-NEXT: [[PARTIAL_REDUCE]] = call <2 x double> @llvm.vector.partial.reduce.fadd.v2f64.v4f64(<2 x double> [[VEC_PHI]], <4 x double> [[TMP4]])
+; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
+; CHECK-INTERLEAVE1-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
+; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; CHECK-INTERLEAVE1: [[MIDDLE_BLOCK]]:
+; CHECK-INTERLEAVE1-NEXT: [[TMP6:%.*]] = call reassoc double @llvm.vector.reduce.fadd.v2f64(double -0.000000e+00, <2 x double> [[PARTIAL_REDUCE]])
+; CHECK-INTERLEAVE1-NEXT: br label %[[FOR_EXIT:.*]]
+; CHECK-INTERLEAVE1: [[FOR_EXIT]]:
+; CHECK-INTERLEAVE1-NEXT: ret double [[TMP6]]
+;
+; CHECK-INTERLEAVED-LABEL: define double @fdotp_f32_f64(
+; CHECK-INTERLEAVED-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
+; CHECK-INTERLEAVED-NEXT: [[ENTRY:.*:]]
+; CHECK-INTERLEAVED-NEXT: br label %[[VECTOR_PH:.*]]
+; CHECK-INTERLEAVED: [[VECTOR_PH]]:
+; CHECK-INTERLEAVED-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-INTERLEAVED: [[VECTOR_BODY]]:
+; CHECK-INTERLEAVED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[VEC_PHI:%.*]] = phi <2 x double> [ <double 0.000000e+00, double -0.000000e+00>, %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[VEC_PHI1:%.*]] = phi <2 x double> [ splat (double -0.000000e+00), %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE5:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[TMP0:%.*]] = getelementptr float, ptr [[A]], i64 [[INDEX]]
+; CHECK-INTERLEAVED-NEXT: [[TMP1:%.*]] = getelementptr float, ptr [[TMP0]], i32 4
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP0]], align 1
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD2:%.*]] = load <4 x float>, ptr [[TMP1]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP2:%.*]] = fpext <4 x float> [[WIDE_LOAD]] to <4 x double>
+; CHECK-INTERLEAVED-NEXT: [[TMP3:%.*]] = fpext <4 x float> [[WIDE_LOAD2]] to <4 x double>
+; CHECK-INTERLEAVED-NEXT: [[TMP4:%.*]] = getelementptr float, ptr [[B]], i64 [[INDEX]]
+; CHECK-INTERLEAVED-NEXT: [[TMP5:%.*]] = getelementptr float, ptr [[TMP4]], i32 4
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD3:%.*]] = load <4 x float>, ptr [[TMP4]], align 1
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x float>, ptr [[TMP5]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP6:%.*]] = fpext <4 x float> [[WIDE_LOAD3]] to <4 x double>
+; CHECK-INTERLEAVED-NEXT: [[TMP7:%.*]] = fpext <4 x float> [[WIDE_LOAD4]] to <4 x double>
+; CHECK-INTERLEAVED-NEXT: [[TMP8:%.*]] = fmul <4 x double> [[TMP6]], [[TMP2]]
+; CHECK-INTERLEAVED-NEXT: [[TMP9:%.*]] = fmul <4 x double> [[TMP7]], [[TMP3]]
+; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE]] = call <2 x double> @llvm.vector.partial.reduce.fadd.v2f64.v4f64(<2 x double> [[VEC_PHI]], <4 x double> [[TMP8]])
+; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE5]] = call <2 x double> @llvm.vector.partial.reduce.fadd.v2f64.v4f64(<2 x double> [[VEC_PHI1]], <4 x double> [[TMP9]])
+; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
+; CHECK-INTERLEAVED-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
+; CHECK-INTERLEAVED-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; CHECK-INTERLEAVED: [[MIDDLE_BLOCK]]:
+; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc <2 x double> [[PARTIAL_REDUCE5]], [[PARTIAL_REDUCE]]
+; CHECK-INTERLEAVED-NEXT: [[TMP11:%.*]] = call reassoc double @llvm.vector.reduce.fadd.v2f64(double -0.000000e+00, <2 x double> [[BIN_RDX]])
+; CHECK-INTERLEAVED-NEXT: br label %[[FOR_EXIT:.*]]
+; CHECK-INTERLEAVED: [[FOR_EXIT]]:
+; CHECK-INTERLEAVED-NEXT: ret double [[TMP11]]
+;
+; CHECK-MAXBW-LABEL: define double @fdotp_f32_f64(
+; CHECK-MAXBW-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
+; CHECK-MAXBW-NEXT: [[ENTRY:.*]]:
+; CHECK-MAXBW-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-MAXBW-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 2
+; CHECK-MAXBW-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
+; CHECK-MAXBW-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK-MAXBW: [[VECTOR_PH]]:
+; CHECK-MAXBW-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-MAXBW-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 4
+; CHECK-MAXBW-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
+; CHECK-MAXBW-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
+; CHECK-MAXBW-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-MAXBW: [[VECTOR_BODY]]:
+; CHECK-MAXBW-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 2 x double> [ insertelement (<vscale x 2 x double> splat (double -0.000000e+00), double 0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[TMP4:%.*]] = getelementptr float, ptr [[A]], i64 [[INDEX]]
+; CHECK-MAXBW-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x float>, ptr [[TMP4]], align 1
+; CHECK-MAXBW-NEXT: [[TMP5:%.*]] = fpext <vscale x 4 x float> [[WIDE_LOAD]] to <vscale x 4 x double>
+; CHECK-MAXBW-NEXT: [[TMP6:%.*]] = getelementptr float, ptr [[B]], i64 [[INDEX]]
+; CHECK-MAXBW-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 4 x float>, ptr [[TMP6]], align 1
+; CHECK-MAXBW-NEXT: [[TMP7:%.*]] = fpext <vscale x 4 x float> [[WIDE_LOAD1]] to <vscale x 4 x double>
+; CHECK-MAXBW-NEXT: [[TMP8:%.*]] = fmul <vscale x 4 x double> [[TMP7]], [[TMP5]]
+; CHECK-MAXBW-NEXT: [[PARTIAL_REDUCE]] = call <vscale x 2 x double> @llvm.vector.partial.reduce.fadd.nxv2f64.nxv4f64(<vscale x 2 x double> [[VEC_PHI]], <vscale x 4 x double> [[TMP8]])
+; CHECK-MAXBW-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
+; CHECK-MAXBW-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-MAXBW-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
+; CHECK-MAXBW: [[MIDDLE_BLOCK]]:
+; CHECK-MAXBW-NEXT: [[TMP10:%.*]] = call reassoc double @llvm.vector.reduce.fadd.nxv2f64(double -0.000000e+00, <vscale x 2 x double> [[PARTIAL_REDUCE]])
+; CHECK-MAXBW-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
+; CHECK-MAXBW-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-MAXBW: [[SCALAR_PH]]:
+; CHECK-MAXBW-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-MAXBW-NEXT: [[BC_MERGE_RDX:%.*]] = phi double [ [[TMP10]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
+; CHECK-MAXBW-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-MAXBW: [[FOR_BODY]]:
+; CHECK-MAXBW-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[ACCUM:%.*]] = phi double [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[FOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[GEP_A:%.*]] = getelementptr float, ptr [[A]], i64 [[IV]]
+; CHECK-MAXBW-NEXT: [[LOAD_A:%.*]] = load float, ptr [[GEP_A]], align 1
+; CHECK-MAXBW-NEXT: [[EXT_A:%.*]] = fpext float [[LOAD_A]] to double
+; CHECK-MAXBW-NEXT: [[GEP_B:%.*]] = getelementptr float, ptr [[B]], i64 [[IV]]
+; CHECK-MAXBW-NEXT: [[LOAD_B:%.*]] = load float, ptr [[GEP_B]], align 1
+; CHECK-MAXBW-NEXT: [[EXT_B:%.*]] = fpext float [[LOAD_B]] to double
+; CHECK-MAXBW-NEXT: [[MUL:%.*]] = fmul double [[EXT_B]], [[EXT_A]]
+; CHECK-MAXBW-NEXT: [[ADD]] = fadd reassoc double [[MUL]], [[ACCUM]]
+; CHECK-MAXBW-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-MAXBW-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
+; CHECK-MAXBW-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
+; CHECK-MAXBW: [[FOR_EXIT]]:
+; CHECK-MAXBW-NEXT: [[ADD_LCSSA:%.*]] = phi double [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP10]], %[[MIDDLE_BLOCK]] ]
+; CHECK-MAXBW-NEXT: ret double [[ADD_LCSSA]]
+;
+; CHECK-INTERLEAVE1-SVE2P1-LABEL: define double @fdotp_f32_f64(
+; CHECK-INTERLEAVE1-SVE2P1-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ENTRY:.*:]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br label %[[VECTOR_PH:.*]]
+; CHECK-INTERLEAVE1-SVE2P1: [[VECTOR_PH]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-INTERLEAVE1-SVE2P1: [[VECTOR_BODY]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[VEC_PHI:%.*]] = phi <2 x double> [ <double 0.000000e+00, double -0.000000e+00>, %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP0:%.*]] = getelementptr float, ptr [[A]], i64 [[INDEX]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP0]], align 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP1:%.*]] = fpext <4 x float> [[WIDE_LOAD]] to <4 x double>
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP2:%.*]] = getelementptr float, ptr [[B]], i64 [[INDEX]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x float>, ptr [[TMP2]], align 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP3:%.*]] = fpext <4 x float> [[WIDE_LOAD1]] to <4 x double>
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP4:%.*]] = fmul <4 x double> [[TMP3]], [[TMP1]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[PARTIAL_REDUCE]] = call <2 x double> @llvm.vector.partial.reduce.fadd.v2f64.v4f64(<2 x double> [[VEC_PHI]], <4 x double> [[TMP4]])
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; CHECK-INTERLEAVE1-SVE2P1: [[MIDDLE_BLOCK]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP6:%.*]] = call reassoc double @llvm.vector.reduce.fadd.v2f64(double -0.000000e+00, <2 x double> [[PARTIAL_REDUCE]])
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br label %[[FOR_EXIT:.*]]
+; CHECK-INTERLEAVE1-SVE2P1: [[FOR_EXIT]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: ret double [[TMP6]]
+entry:
+ br label %for.body
+
+for.body: ; preds = %for.body, %entry
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+ %accum = phi double [ 0.0, %entry ], [ %add, %for.body ]
+ %gep.a = getelementptr float, ptr %a, i64 %iv
+ %load.a = load float, ptr %gep.a, align 1
+ %ext.a = fpext float %load.a to double
+ %gep.b = getelementptr float, ptr %b, i64 %iv
+ %load.b = load float, ptr %gep.b, align 1
+ %ext.b = fpext float %load.b to double
+ %mul = fmul double %ext.b, %ext.a
+ %add = fadd reassoc double %mul, %accum
+ %iv.next = add i64 %iv, 1
+ %exitcond.not = icmp eq i64 %iv.next, 1024
+ br i1 %exitcond.not, label %for.exit, label %for.body
+
+for.exit: ; preds = %for.body
+ ret double %add
+}
+
+define half @fdotp_noext_f16(ptr %a, ptr %b) #0 {
+; CHECK-INTERLEAVE1-LABEL: define half @fdotp_noext_f16(
+; CHECK-INTERLEAVE1-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
+; CHECK-INTERLEAVE1-NEXT: [[ENTRY:.*]]:
+; CHECK-INTERLEAVE1-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVE1-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 3
+; CHECK-INTERLEAVE1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK-INTERLEAVE1: [[VECTOR_PH]]:
+; CHECK-INTERLEAVE1-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVE1-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 8
+; CHECK-INTERLEAVE1-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
+; CHECK-INTERLEAVE1-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
+; CHECK-INTERLEAVE1-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-INTERLEAVE1: [[VECTOR_BODY]]:
+; CHECK-INTERLEAVE1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 8 x half> [ insertelement (<vscale x 8 x half> splat (half 0xH8000), half 0xH0000, i32 0), %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[TMP4:%.*]] = getelementptr half, ptr [[A]], i64 [[INDEX]]
+; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 8 x half>, ptr [[TMP4]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP5:%.*]] = getelementptr half, ptr [[B]], i64 [[INDEX]]
+; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 8 x half>, ptr [[TMP5]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP6:%.*]] = fmul <vscale x 8 x half> [[WIDE_LOAD1]], [[WIDE_LOAD]]
+; CHECK-INTERLEAVE1-NEXT: [[TMP7]] = fadd reassoc <vscale x 8 x half> [[TMP6]], [[VEC_PHI]]
+; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
+; CHECK-INTERLEAVE1-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
+; CHECK-INTERLEAVE1: [[MIDDLE_BLOCK]]:
+; CHECK-INTERLEAVE1-NEXT: [[TMP9:%.*]] = call reassoc half @llvm.vector.reduce.fadd.nxv8f16(half 0xH8000, <vscale x 8 x half> [[TMP7]])
+; CHECK-INTERLEAVE1-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-INTERLEAVE1: [[SCALAR_PH]]:
+; CHECK-INTERLEAVE1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[BC_MERGE_RDX:%.*]] = phi half [ [[TMP9]], %[[MIDDLE_BLOCK]] ], [ 0xH0000, %[[ENTRY]] ]
+; CHECK-INTERLEAVE1-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-INTERLEAVE1: [[FOR_BODY]]:
+; CHECK-INTERLEAVE1-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[ACCUM:%.*]] = phi half [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[GEP_A:%.*]] = getelementptr half, ptr [[A]], i64 [[IV]]
+; CHECK-INTERLEAVE1-NEXT: [[LOAD_A:%.*]] = load half, ptr [[GEP_A]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[GEP_B:%.*]] = getelementptr half, ptr [[B]], i64 [[IV]]
+; CHECK-INTERLEAVE1-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[MUL:%.*]] = fmul half [[LOAD_B]], [[LOAD_A]]
+; CHECK-INTERLEAVE1-NEXT: [[ADD]] = fadd reassoc half [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVE1-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-INTERLEAVE1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
+; CHECK-INTERLEAVE1-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
+; CHECK-INTERLEAVE1: [[FOR_EXIT]]:
+; CHECK-INTERLEAVE1-NEXT: [[ADD_LCSSA:%.*]] = phi half [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP9]], %[[MIDDLE_BLOCK]] ]
+; CHECK-INTERLEAVE1-NEXT: ret half [[ADD_LCSSA]]
+;
+; CHECK-INTERLEAVED-LABEL: define half @fdotp_noext_f16(
+; CHECK-INTERLEAVED-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
+; CHECK-INTERLEAVED-NEXT: [[ENTRY:.*]]:
+; CHECK-INTERLEAVED-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVED-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 4
+; CHECK-INTERLEAVED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK-INTERLEAVED: [[VECTOR_PH]]:
+; CHECK-INTERLEAVED-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVED-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 16
+; CHECK-INTERLEAVED-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
+; CHECK-INTERLEAVED-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
+; CHECK-INTERLEAVED-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-INTERLEAVED: [[VECTOR_BODY]]:
+; CHECK-INTERLEAVED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 8 x half> [ insertelement (<vscale x 8 x half> splat (half 0xH8000), half 0xH0000, i32 0), %[[VECTOR_PH]] ], [ [[TMP14:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[VEC_PHI1:%.*]] = phi <vscale x 8 x half> [ splat (half 0xH8000), %[[VECTOR_PH]] ], [ [[TMP15:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[TMP4:%.*]] = getelementptr half, ptr [[A]], i64 [[INDEX]]
+; CHECK-INTERLEAVED-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVED-NEXT: [[TMP6:%.*]] = shl nuw i64 [[TMP5]], 3
+; CHECK-INTERLEAVED-NEXT: [[TMP7:%.*]] = getelementptr half, ptr [[TMP4]], i64 [[TMP6]]
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 8 x half>, ptr [[TMP4]], align 1
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD2:%.*]] = load <vscale x 8 x half>, ptr [[TMP7]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP8:%.*]] = getelementptr half, ptr [[B]], i64 [[INDEX]]
+; CHECK-INTERLEAVED-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVED-NEXT: [[TMP10:%.*]] = shl nuw i64 [[TMP9]], 3
+; CHECK-INTERLEAVED-NEXT: [[TMP11:%.*]] = getelementptr half, ptr [[TMP8]], i64 [[TMP10]]
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD3:%.*]] = load <vscale x 8 x half>, ptr [[TMP8]], align 1
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD4:%.*]] = load <vscale x 8 x half>, ptr [[TMP11]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP12:%.*]] = fmul <vscale x 8 x half> [[WIDE_LOAD3]], [[WIDE_LOAD]]
+; CHECK-INTERLEAVED-NEXT: [[TMP13:%.*]] = fmul <vscale x 8 x half> [[WIDE_LOAD4]], [[WIDE_LOAD2]]
+; CHECK-INTERLEAVED-NEXT: [[TMP14]] = fadd reassoc <vscale x 8 x half> [[TMP12]], [[VEC_PHI]]
+; CHECK-INTERLEAVED-NEXT: [[TMP15]] = fadd reassoc <vscale x 8 x half> [[TMP13]], [[VEC_PHI1]]
+; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
+; CHECK-INTERLEAVED-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
+; CHECK-INTERLEAVED: [[MIDDLE_BLOCK]]:
+; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc <vscale x 8 x half> [[TMP15]], [[TMP14]]
+; CHECK-INTERLEAVED-NEXT: [[TMP17:%.*]] = call reassoc half @llvm.vector.reduce.fadd.nxv8f16(half 0xH8000, <vscale x 8 x half> [[BIN_RDX]])
+; CHECK-INTERLEAVED-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-INTERLEAVED: [[SCALAR_PH]]:
+; CHECK-INTERLEAVED-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-INTERLEAVED-NEXT: [[BC_MERGE_RDX:%.*]] = phi half [ [[TMP17]], %[[MIDDLE_BLOCK]] ], [ 0xH0000, %[[ENTRY]] ]
+; CHECK-INTERLEAVED-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-INTERLEAVED: [[FOR_BODY]]:
+; CHECK-INTERLEAVED-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[ACCUM:%.*]] = phi half [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[GEP_A:%.*]] = getelementptr half, ptr [[A]], i64 [[IV]]
+; CHECK-INTERLEAVED-NEXT: [[LOAD_A:%.*]] = load half, ptr [[GEP_A]], align 1
+; CHECK-INTERLEAVED-NEXT: [[GEP_B:%.*]] = getelementptr half, ptr [[B]], i64 [[IV]]
+; CHECK-INTERLEAVED-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
+; CHECK-INTERLEAVED-NEXT: [[MUL:%.*]] = fmul half [[LOAD_B]], [[LOAD_A]]
+; CHECK-INTERLEAVED-NEXT: [[ADD]] = fadd reassoc half [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVED-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-INTERLEAVED-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
+; CHECK-INTERLEAVED-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
+; CHECK-INTERLEAVED: [[FOR_EXIT]]:
+; CHECK-INTERLEAVED-NEXT: [[ADD_LCSSA:%.*]] = phi half [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP17]], %[[MIDDLE_BLOCK]] ]
+; CHECK-INTERLEAVED-NEXT: ret half [[ADD_LCSSA]]
+;
+; CHECK-MAXBW-LABEL: define half @fdotp_noext_f16(
+; CHECK-MAXBW-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
+; CHECK-MAXBW-NEXT: [[ENTRY:.*]]:
+; CHECK-MAXBW-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-MAXBW-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 3
+; CHECK-MAXBW-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
+; CHECK-MAXBW-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK-MAXBW: [[VECTOR_PH]]:
+; CHECK-MAXBW-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-MAXBW-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 8
+; CHECK-MAXBW-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
+; CHECK-MAXBW-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
+; CHECK-MAXBW-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-MAXBW: [[VECTOR_BODY]]:
+; CHECK-MAXBW-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 8 x half> [ insertelement (<vscale x 8 x half> splat (half 0xH8000), half 0xH0000, i32 0), %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[TMP4:%.*]] = getelementptr half, ptr [[A]], i64 [[INDEX]]
+; CHECK-MAXBW-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 8 x half>, ptr [[TMP4]], align 1
+; CHECK-MAXBW-NEXT: [[TMP5:%.*]] = getelementptr half, ptr [[B]], i64 [[INDEX]]
+; CHECK-MAXBW-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 8 x half>, ptr [[TMP5]], align 1
+; CHECK-MAXBW-NEXT: [[TMP6:%.*]] = fmul <vscale x 8 x half> [[WIDE_LOAD1]], [[WIDE_LOAD]]
+; CHECK-MAXBW-NEXT: [[TMP7]] = fadd reassoc <vscale x 8 x half> [[TMP6]], [[VEC_PHI]]
+; CHECK-MAXBW-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
+; CHECK-MAXBW-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-MAXBW-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
+; CHECK-MAXBW: [[MIDDLE_BLOCK]]:
+; CHECK-MAXBW-NEXT: [[TMP9:%.*]] = call reassoc half @llvm.vector.reduce.fadd.nxv8f16(half 0xH8000, <vscale x 8 x half> [[TMP7]])
+; CHECK-MAXBW-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
+; CHECK-MAXBW-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-MAXBW: [[SCALAR_PH]]:
+; CHECK-MAXBW-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-MAXBW-NEXT: [[BC_MERGE_RDX:%.*]] = phi half [ [[TMP9]], %[[MIDDLE_BLOCK]] ], [ 0xH0000, %[[ENTRY]] ]
+; CHECK-MAXBW-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-MAXBW: [[FOR_BODY]]:
+; CHECK-MAXBW-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[ACCUM:%.*]] = phi half [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[FOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[GEP_A:%.*]] = getelementptr half, ptr [[A]], i64 [[IV]]
+; CHECK-MAXBW-NEXT: [[LOAD_A:%.*]] = load half, ptr [[GEP_A]], align 1
+; CHECK-MAXBW-NEXT: [[GEP_B:%.*]] = getelementptr half, ptr [[B]], i64 [[IV]]
+; CHECK-MAXBW-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
+; CHECK-MAXBW-NEXT: [[MUL:%.*]] = fmul half [[LOAD_B]], [[LOAD_A]]
+; CHECK-MAXBW-NEXT: [[ADD]] = fadd reassoc half [[MUL]], [[ACCUM]]
+; CHECK-MAXBW-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-MAXBW-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
+; CHECK-MAXBW-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]]
+; CHECK-MAXBW: [[FOR_EXIT]]:
+; CHECK-MAXBW-NEXT: [[ADD_LCSSA:%.*]] = phi half [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP9]], %[[MIDDLE_BLOCK]] ]
+; CHECK-MAXBW-NEXT: ret half [[ADD_LCSSA]]
+;
+; CHECK-INTERLEAVE1-SVE2P1-LABEL: define half @fdotp_noext_f16(
+; CHECK-INTERLEAVE1-SVE2P1-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ENTRY:.*]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 3
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK-INTERLEAVE1-SVE2P1: [[VECTOR_PH]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 8
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-INTERLEAVE1-SVE2P1: [[VECTOR_BODY]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 8 x half> [ insertelement (<vscale x 8 x half> splat (half 0xH8000), half 0xH0000, i32 0), %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP4:%.*]] = getelementptr half, ptr [[A]], i64 [[INDEX]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 8 x half>, ptr [[TMP4]], align 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP5:%.*]] = getelementptr half, ptr [[B]], i64 [[INDEX]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 8 x half>, ptr [[TMP5]], align 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP6:%.*]] = fmul <vscale x 8 x half> [[WIDE_LOAD1]], [[WIDE_LOAD]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP7]] = fadd reassoc <vscale x 8 x half> [[TMP6]], [[VEC_PHI]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
+; CHECK-INTERLEAVE1-SVE2P1: [[MIDDLE_BLOCK]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP9:%.*]] = call reassoc half @llvm.vector.reduce.fadd.nxv8f16(half 0xH8000, <vscale x 8 x half> [[TMP7]])
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-INTERLEAVE1-SVE2P1: [[SCALAR_PH]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[BC_MERGE_RDX:%.*]] = phi half [ [[TMP9]], %[[MIDDLE_BLOCK]] ], [ 0xH0000, %[[ENTRY]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-INTERLEAVE1-SVE2P1: [[FOR_BODY]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ACCUM:%.*]] = phi half [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[GEP_A:%.*]] = getelementptr half, ptr [[A]], i64 [[IV]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[LOAD_A:%.*]] = load half, ptr [[GEP_A]], align 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[GEP_B:%.*]] = getelementptr half, ptr [[B]], i64 [[IV]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[MUL:%.*]] = fmul half [[LOAD_B]], [[LOAD_A]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ADD]] = fadd reassoc half [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
+; CHECK-INTERLEAVE1-SVE2P1: [[FOR_EXIT]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ADD_LCSSA:%.*]] = phi half [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP9]], %[[MIDDLE_BLOCK]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: ret half [[ADD_LCSSA]]
+entry:
+ br label %for.body
+
+for.body: ; preds = %for.body, %entry
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+ %accum = phi half [ 0.0, %entry ], [ %add, %for.body ]
+ %gep.a = getelementptr half, ptr %a, i64 %iv
+ %load.a = load half, ptr %gep.a, align 1
+ %gep.b = getelementptr half, ptr %b, i64 %iv
+ %load.b = load half, ptr %gep.b, align 1
+ %mul = fmul half %load.b, %load.a
+ %add = fadd reassoc half %mul, %accum
+ %iv.next = add i64 %iv, 1
+ %exitcond.not = icmp eq i64 %iv.next, 1024
+ br i1 %exitcond.not, label %for.exit, label %for.body
+
+for.exit: ; preds = %for.body
+ ret half %add
+}
+
+define float @fdotp_noext_f32(ptr %a, ptr %b) #0 {
+; CHECK-INTERLEAVE1-LABEL: define float @fdotp_noext_f32(
+; CHECK-INTERLEAVE1-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
+; CHECK-INTERLEAVE1-NEXT: [[ENTRY:.*]]:
+; CHECK-INTERLEAVE1-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVE1-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 2
+; CHECK-INTERLEAVE1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK-INTERLEAVE1: [[VECTOR_PH]]:
+; CHECK-INTERLEAVE1-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVE1-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 4
+; CHECK-INTERLEAVE1-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
+; CHECK-INTERLEAVE1-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
+; CHECK-INTERLEAVE1-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-INTERLEAVE1: [[VECTOR_BODY]]:
+; CHECK-INTERLEAVE1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x float> [ insertelement (<vscale x 4 x float> splat (float -0.000000e+00), float 0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[TMP4:%.*]] = getelementptr float, ptr [[A]], i64 [[INDEX]]
+; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x float>, ptr [[TMP4]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP5:%.*]] = getelementptr float, ptr [[B]], i64 [[INDEX]]
+; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 4 x float>, ptr [[TMP5]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP6:%.*]] = fmul <vscale x 4 x float> [[WIDE_LOAD1]], [[WIDE_LOAD]]
+; CHECK-INTERLEAVE1-NEXT: [[TMP7]] = fadd reassoc <vscale x 4 x float> [[TMP6]], [[VEC_PHI]]
+; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
+; CHECK-INTERLEAVE1-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
; CHECK-INTERLEAVE1: [[MIDDLE_BLOCK]]:
-; CHECK-INTERLEAVE1-NEXT: [[TMP11:%.*]] = call reassoc float @llvm.vector.reduce.fadd.nxv2f32(float -0.000000e+00, <vscale x 2 x float> [[TMP9]])
+; CHECK-INTERLEAVE1-NEXT: [[TMP9:%.*]] = call reassoc float @llvm.vector.reduce.fadd.nxv4f32(float -0.000000e+00, <vscale x 4 x float> [[TMP7]])
; CHECK-INTERLEAVE1-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
; CHECK-INTERLEAVE1-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
; CHECK-INTERLEAVE1: [[SCALAR_PH]]:
; CHECK-INTERLEAVE1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
-; CHECK-INTERLEAVE1-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP11]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP9]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
; CHECK-INTERLEAVE1-NEXT: br label %[[FOR_BODY:.*]]
; CHECK-INTERLEAVE1: [[FOR_BODY]]:
-; CHECK-INTERLEAVE1-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
; CHECK-INTERLEAVE1-NEXT: [[ACCUM:%.*]] = phi float [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[FOR_BODY]] ]
-; CHECK-INTERLEAVE1-NEXT: [[GEP_A:%.*]] = getelementptr half, ptr [[A]], i64 [[IV]]
-; CHECK-INTERLEAVE1-NEXT: [[LOAD_A:%.*]] = load half, ptr [[GEP_A]], align 1
-; CHECK-INTERLEAVE1-NEXT: [[EXT_A:%.*]] = fpext half [[LOAD_A]] to float
-; CHECK-INTERLEAVE1-NEXT: [[GEP_B:%.*]] = getelementptr half, ptr [[B]], i64 [[IV]]
-; CHECK-INTERLEAVE1-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
-; CHECK-INTERLEAVE1-NEXT: [[EXT_B:%.*]] = fpext half [[LOAD_B]] to float
-; CHECK-INTERLEAVE1-NEXT: [[MUL:%.*]] = fmul float [[EXT_B]], [[EXT_A]]
+; CHECK-INTERLEAVE1-NEXT: [[GEP_A:%.*]] = getelementptr float, ptr [[A]], i64 [[IV]]
+; CHECK-INTERLEAVE1-NEXT: [[LOAD_A:%.*]] = load float, ptr [[GEP_A]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[GEP_B:%.*]] = getelementptr float, ptr [[B]], i64 [[IV]]
+; CHECK-INTERLEAVE1-NEXT: [[LOAD_B:%.*]] = load float, ptr [[GEP_B]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[MUL:%.*]] = fmul float [[LOAD_B]], [[LOAD_A]]
; CHECK-INTERLEAVE1-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[ACCUM]]
-; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add i64 [[IV]], 1
-; CHECK-INTERLEAVE1-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
-; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP6]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK-INTERLEAVE1-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-INTERLEAVE1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
+; CHECK-INTERLEAVE1-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
; CHECK-INTERLEAVE1: [[FOR_EXIT]]:
-; CHECK-INTERLEAVE1-NEXT: [[TMP7:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP11]], %[[MIDDLE_BLOCK]] ]
-; CHECK-INTERLEAVE1-NEXT: ret float [[TMP7]]
+; CHECK-INTERLEAVE1-NEXT: [[ADD_LCSSA:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP9]], %[[MIDDLE_BLOCK]] ]
+; CHECK-INTERLEAVE1-NEXT: ret float [[ADD_LCSSA]]
;
-; CHECK-INTERLEAVED-LABEL: define float @fdotp(
-; CHECK-INTERLEAVED-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-INTERLEAVED-LABEL: define float @fdotp_noext_f32(
+; CHECK-INTERLEAVED-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
; CHECK-INTERLEAVED-NEXT: [[ENTRY:.*]]:
-; CHECK-INTERLEAVED-NEXT: [[TMP10:%.*]] = call i64 @llvm.vscale.i64()
-; CHECK-INTERLEAVED-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP10]], 2
+; CHECK-INTERLEAVED-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVED-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 3
; CHECK-INTERLEAVED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
; CHECK-INTERLEAVED-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK-INTERLEAVED: [[VECTOR_PH]]:
; CHECK-INTERLEAVED-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
-; CHECK-INTERLEAVED-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 4
+; CHECK-INTERLEAVED-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 8
; CHECK-INTERLEAVED-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
; CHECK-INTERLEAVED-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
; CHECK-INTERLEAVED-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK-INTERLEAVED: [[VECTOR_BODY]]:
-; CHECK-INTERLEAVED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT1:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-INTERLEAVED-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 2 x float> [ insertelement (<vscale x 2 x float> splat (float -0.000000e+00), float 0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[TMP18:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-INTERLEAVED-NEXT: [[VEC_PHI1:%.*]] = phi <vscale x 2 x float> [ splat (float -0.000000e+00), %[[VECTOR_PH]] ], [ [[TMP19:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-INTERLEAVED-NEXT: [[TMP0:%.*]] = getelementptr half, ptr [[A]], i64 [[INDEX]]
+; CHECK-INTERLEAVED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x float> [ insertelement (<vscale x 4 x float> splat (float -0.000000e+00), float 0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[TMP14:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[VEC_PHI1:%.*]] = phi <vscale x 4 x float> [ splat (float -0.000000e+00), %[[VECTOR_PH]] ], [ [[TMP15:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[TMP4:%.*]] = getelementptr float, ptr [[A]], i64 [[INDEX]]
; CHECK-INTERLEAVED-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
-; CHECK-INTERLEAVED-NEXT: [[TMP6:%.*]] = shl nuw i64 [[TMP5]], 1
-; CHECK-INTERLEAVED-NEXT: [[TMP7:%.*]] = getelementptr half, ptr [[TMP0]], i64 [[TMP6]]
-; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 2 x half>, ptr [[TMP0]], align 1
-; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD2:%.*]] = load <vscale x 2 x half>, ptr [[TMP7]], align 1
-; CHECK-INTERLEAVED-NEXT: [[TMP8:%.*]] = fpext <vscale x 2 x half> [[WIDE_LOAD]] to <vscale x 2 x float>
-; CHECK-INTERLEAVED-NEXT: [[TMP9:%.*]] = fpext <vscale x 2 x half> [[WIDE_LOAD2]] to <vscale x 2 x float>
-; CHECK-INTERLEAVED-NEXT: [[TMP4:%.*]] = getelementptr half, ptr [[B]], i64 [[INDEX]]
-; CHECK-INTERLEAVED-NEXT: [[TMP22:%.*]] = call i64 @llvm.vscale.i64()
-; CHECK-INTERLEAVED-NEXT: [[TMP23:%.*]] = shl nuw i64 [[TMP22]], 1
-; CHECK-INTERLEAVED-NEXT: [[TMP13:%.*]] = getelementptr half, ptr [[TMP4]], i64 [[TMP23]]
-; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD3:%.*]] = load <vscale x 2 x half>, ptr [[TMP4]], align 1
-; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD4:%.*]] = load <vscale x 2 x half>, ptr [[TMP13]], align 1
-; CHECK-INTERLEAVED-NEXT: [[TMP14:%.*]] = fpext <vscale x 2 x half> [[WIDE_LOAD3]] to <vscale x 2 x float>
-; CHECK-INTERLEAVED-NEXT: [[TMP15:%.*]] = fpext <vscale x 2 x half> [[WIDE_LOAD4]] to <vscale x 2 x float>
-; CHECK-INTERLEAVED-NEXT: [[TMP16:%.*]] = fmul <vscale x 2 x float> [[TMP14]], [[TMP8]]
-; CHECK-INTERLEAVED-NEXT: [[TMP17:%.*]] = fmul <vscale x 2 x float> [[TMP15]], [[TMP9]]
-; CHECK-INTERLEAVED-NEXT: [[TMP18]] = fadd reassoc <vscale x 2 x float> [[TMP16]], [[VEC_PHI]]
-; CHECK-INTERLEAVED-NEXT: [[TMP19]] = fadd reassoc <vscale x 2 x float> [[TMP17]], [[VEC_PHI1]]
-; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT1]] = add nuw i64 [[INDEX]], [[TMP3]]
-; CHECK-INTERLEAVED-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT1]], [[N_VEC]]
-; CHECK-INTERLEAVED-NEXT: br i1 [[TMP20]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK-INTERLEAVED-NEXT: [[TMP6:%.*]] = shl nuw i64 [[TMP5]], 2
+; CHECK-INTERLEAVED-NEXT: [[TMP7:%.*]] = getelementptr float, ptr [[TMP4]], i64 [[TMP6]]
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x float>, ptr [[TMP4]], align 1
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD2:%.*]] = load <vscale x 4 x float>, ptr [[TMP7]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP8:%.*]] = getelementptr float, ptr [[B]], i64 [[INDEX]]
+; CHECK-INTERLEAVED-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVED-NEXT: [[TMP10:%.*]] = shl nuw i64 [[TMP9]], 2
+; CHECK-INTERLEAVED-NEXT: [[TMP11:%.*]] = getelementptr float, ptr [[TMP8]], i64 [[TMP10]]
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD3:%.*]] = load <vscale x 4 x float>, ptr [[TMP8]], align 1
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD4:%.*]] = load <vscale x 4 x float>, ptr [[TMP11]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP12:%.*]] = fmul <vscale x 4 x float> [[WIDE_LOAD3]], [[WIDE_LOAD]]
+; CHECK-INTERLEAVED-NEXT: [[TMP13:%.*]] = fmul <vscale x 4 x float> [[WIDE_LOAD4]], [[WIDE_LOAD2]]
+; CHECK-INTERLEAVED-NEXT: [[TMP14]] = fadd reassoc <vscale x 4 x float> [[TMP12]], [[VEC_PHI]]
+; CHECK-INTERLEAVED-NEXT: [[TMP15]] = fadd reassoc <vscale x 4 x float> [[TMP13]], [[VEC_PHI1]]
+; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
+; CHECK-INTERLEAVED-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
; CHECK-INTERLEAVED: [[MIDDLE_BLOCK]]:
-; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc <vscale x 2 x float> [[TMP19]], [[TMP18]]
-; CHECK-INTERLEAVED-NEXT: [[TMP21:%.*]] = call reassoc float @llvm.vector.reduce.fadd.nxv2f32(float -0.000000e+00, <vscale x 2 x float> [[BIN_RDX]])
+; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc <vscale x 4 x float> [[TMP15]], [[TMP14]]
+; CHECK-INTERLEAVED-NEXT: [[TMP17:%.*]] = call reassoc float @llvm.vector.reduce.fadd.nxv4f32(float -0.000000e+00, <vscale x 4 x float> [[BIN_RDX]])
; CHECK-INTERLEAVED-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
; CHECK-INTERLEAVED-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
; CHECK-INTERLEAVED: [[SCALAR_PH]]:
; CHECK-INTERLEAVED-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
-; CHECK-INTERLEAVED-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP21]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
+; CHECK-INTERLEAVED-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP17]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
; CHECK-INTERLEAVED-NEXT: br label %[[FOR_BODY:.*]]
; CHECK-INTERLEAVED: [[FOR_BODY]]:
-; CHECK-INTERLEAVED-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
; CHECK-INTERLEAVED-NEXT: [[ACCUM:%.*]] = phi float [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[FOR_BODY]] ]
-; CHECK-INTERLEAVED-NEXT: [[GEP_A:%.*]] = getelementptr half, ptr [[A]], i64 [[IV]]
-; CHECK-INTERLEAVED-NEXT: [[LOAD_A:%.*]] = load half, ptr [[GEP_A]], align 1
-; CHECK-INTERLEAVED-NEXT: [[EXT_A:%.*]] = fpext half [[LOAD_A]] to float
-; CHECK-INTERLEAVED-NEXT: [[GEP_B:%.*]] = getelementptr half, ptr [[B]], i64 [[IV]]
-; CHECK-INTERLEAVED-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
-; CHECK-INTERLEAVED-NEXT: [[EXT_B:%.*]] = fpext half [[LOAD_B]] to float
-; CHECK-INTERLEAVED-NEXT: [[MUL:%.*]] = fmul float [[EXT_B]], [[EXT_A]]
+; CHECK-INTERLEAVED-NEXT: [[GEP_A:%.*]] = getelementptr float, ptr [[A]], i64 [[IV]]
+; CHECK-INTERLEAVED-NEXT: [[LOAD_A:%.*]] = load float, ptr [[GEP_A]], align 1
+; CHECK-INTERLEAVED-NEXT: [[GEP_B:%.*]] = getelementptr float, ptr [[B]], i64 [[IV]]
+; CHECK-INTERLEAVED-NEXT: [[LOAD_B:%.*]] = load float, ptr [[GEP_B]], align 1
+; CHECK-INTERLEAVED-NEXT: [[MUL:%.*]] = fmul float [[LOAD_B]], [[LOAD_A]]
; CHECK-INTERLEAVED-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[ACCUM]]
-; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add i64 [[IV]], 1
-; CHECK-INTERLEAVED-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
-; CHECK-INTERLEAVED-NEXT: br i1 [[TMP12]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK-INTERLEAVED-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-INTERLEAVED-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
+; CHECK-INTERLEAVED-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
; CHECK-INTERLEAVED: [[FOR_EXIT]]:
-; CHECK-INTERLEAVED-NEXT: [[TMP11:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP21]], %[[MIDDLE_BLOCK]] ]
-; CHECK-INTERLEAVED-NEXT: ret float [[TMP11]]
+; CHECK-INTERLEAVED-NEXT: [[ADD_LCSSA:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP17]], %[[MIDDLE_BLOCK]] ]
+; CHECK-INTERLEAVED-NEXT: ret float [[ADD_LCSSA]]
;
-; CHECK-MAXBW-LABEL: define float @fdotp(
-; CHECK-MAXBW-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-MAXBW-LABEL: define float @fdotp_noext_f32(
+; CHECK-MAXBW-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
; CHECK-MAXBW-NEXT: [[ENTRY:.*]]:
-; CHECK-MAXBW-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64()
-; CHECK-MAXBW-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP4]], 1
+; CHECK-MAXBW-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-MAXBW-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 2
; CHECK-MAXBW-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
; CHECK-MAXBW-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK-MAXBW: [[VECTOR_PH]]:
-; CHECK-MAXBW-NEXT: [[TMP6:%.*]] = call i64 @llvm.vscale.i64()
-; CHECK-MAXBW-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP6]], 2
+; CHECK-MAXBW-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-MAXBW-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 4
; CHECK-MAXBW-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
; CHECK-MAXBW-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
; CHECK-MAXBW-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK-MAXBW: [[VECTOR_BODY]]:
; CHECK-MAXBW-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-MAXBW-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 2 x float> [ insertelement (<vscale x 2 x float> splat (float -0.000000e+00), float 0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[TMP10:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-MAXBW-NEXT: [[TMP0:%.*]] = getelementptr half, ptr [[A]], i64 [[INDEX]]
-; CHECK-MAXBW-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 2 x half>, ptr [[TMP0]], align 1
-; CHECK-MAXBW-NEXT: [[TMP5:%.*]] = fpext <vscale x 2 x half> [[WIDE_LOAD]] to <vscale x 2 x float>
-; CHECK-MAXBW-NEXT: [[TMP2:%.*]] = getelementptr half, ptr [[B]], i64 [[INDEX]]
-; CHECK-MAXBW-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 2 x half>, ptr [[TMP2]], align 1
-; CHECK-MAXBW-NEXT: [[TMP7:%.*]] = fpext <vscale x 2 x half> [[WIDE_LOAD1]] to <vscale x 2 x float>
-; CHECK-MAXBW-NEXT: [[TMP8:%.*]] = fmul <vscale x 2 x float> [[TMP7]], [[TMP5]]
-; CHECK-MAXBW-NEXT: [[TMP10]] = fadd reassoc <vscale x 2 x float> [[TMP8]], [[VEC_PHI]]
+; CHECK-MAXBW-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x float> [ insertelement (<vscale x 4 x float> splat (float -0.000000e+00), float 0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[TMP4:%.*]] = getelementptr float, ptr [[A]], i64 [[INDEX]]
+; CHECK-MAXBW-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x float>, ptr [[TMP4]], align 1
+; CHECK-MAXBW-NEXT: [[TMP5:%.*]] = getelementptr float, ptr [[B]], i64 [[INDEX]]
+; CHECK-MAXBW-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 4 x float>, ptr [[TMP5]], align 1
+; CHECK-MAXBW-NEXT: [[TMP6:%.*]] = fmul <vscale x 4 x float> [[WIDE_LOAD1]], [[WIDE_LOAD]]
+; CHECK-MAXBW-NEXT: [[TMP7]] = fadd reassoc <vscale x 4 x float> [[TMP6]], [[VEC_PHI]]
; CHECK-MAXBW-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
-; CHECK-MAXBW-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-MAXBW-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK-MAXBW-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-MAXBW-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]
; CHECK-MAXBW: [[MIDDLE_BLOCK]]:
-; CHECK-MAXBW-NEXT: [[TMP11:%.*]] = call reassoc float @llvm.vector.reduce.fadd.nxv2f32(float -0.000000e+00, <vscale x 2 x float> [[TMP10]])
+; CHECK-MAXBW-NEXT: [[TMP9:%.*]] = call reassoc float @llvm.vector.reduce.fadd.nxv4f32(float -0.000000e+00, <vscale x 4 x float> [[TMP7]])
; CHECK-MAXBW-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
; CHECK-MAXBW-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
; CHECK-MAXBW: [[SCALAR_PH]]:
; CHECK-MAXBW-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
-; CHECK-MAXBW-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP11]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
+; CHECK-MAXBW-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP9]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
; CHECK-MAXBW-NEXT: br label %[[FOR_BODY:.*]]
; CHECK-MAXBW: [[FOR_BODY]]:
; CHECK-MAXBW-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
; CHECK-MAXBW-NEXT: [[ACCUM:%.*]] = phi float [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[FOR_BODY]] ]
-; CHECK-MAXBW-NEXT: [[GEP_A:%.*]] = getelementptr half, ptr [[A]], i64 [[IV]]
-; CHECK-MAXBW-NEXT: [[LOAD_A:%.*]] = load half, ptr [[GEP_A]], align 1
-; CHECK-MAXBW-NEXT: [[EXT_A:%.*]] = fpext half [[LOAD_A]] to float
-; CHECK-MAXBW-NEXT: [[GEP_B:%.*]] = getelementptr half, ptr [[B]], i64 [[IV]]
-; CHECK-MAXBW-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
-; CHECK-MAXBW-NEXT: [[EXT_B:%.*]] = fpext half [[LOAD_B]] to float
-; CHECK-MAXBW-NEXT: [[MUL:%.*]] = fmul float [[EXT_B]], [[EXT_A]]
+; CHECK-MAXBW-NEXT: [[GEP_A:%.*]] = getelementptr float, ptr [[A]], i64 [[IV]]
+; CHECK-MAXBW-NEXT: [[LOAD_A:%.*]] = load float, ptr [[GEP_A]], align 1
+; CHECK-MAXBW-NEXT: [[GEP_B:%.*]] = getelementptr float, ptr [[B]], i64 [[IV]]
+; CHECK-MAXBW-NEXT: [[LOAD_B:%.*]] = load float, ptr [[GEP_B]], align 1
+; CHECK-MAXBW-NEXT: [[MUL:%.*]] = fmul float [[LOAD_B]], [[LOAD_A]]
; CHECK-MAXBW-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[ACCUM]]
; CHECK-MAXBW-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
; CHECK-MAXBW-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
-; CHECK-MAXBW-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK-MAXBW-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]]
; CHECK-MAXBW: [[FOR_EXIT]]:
-; CHECK-MAXBW-NEXT: [[ADD_LCSSA:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP11]], %[[MIDDLE_BLOCK]] ]
+; CHECK-MAXBW-NEXT: [[ADD_LCSSA:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP9]], %[[MIDDLE_BLOCK]] ]
; CHECK-MAXBW-NEXT: ret float [[ADD_LCSSA]]
;
+; CHECK-INTERLEAVE1-SVE2P1-LABEL: define float @fdotp_noext_f32(
+; CHECK-INTERLEAVE1-SVE2P1-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ENTRY:.*]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 2
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK-INTERLEAVE1-SVE2P1: [[VECTOR_PH]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 4
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-INTERLEAVE1-SVE2P1: [[VECTOR_BODY]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x float> [ insertelement (<vscale x 4 x float> splat (float -0.000000e+00), float 0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP4:%.*]] = getelementptr float, ptr [[A]], i64 [[INDEX]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x float>, ptr [[TMP4]], align 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP5:%.*]] = getelementptr float, ptr [[B]], i64 [[INDEX]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 4 x float>, ptr [[TMP5]], align 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP6:%.*]] = fmul <vscale x 4 x float> [[WIDE_LOAD1]], [[WIDE_LOAD]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP7]] = fadd reassoc <vscale x 4 x float> [[TMP6]], [[VEC_PHI]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
+; CHECK-INTERLEAVE1-SVE2P1: [[MIDDLE_BLOCK]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP9:%.*]] = call reassoc float @llvm.vector.reduce.fadd.nxv4f32(float -0.000000e+00, <vscale x 4 x float> [[TMP7]])
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-INTERLEAVE1-SVE2P1: [[SCALAR_PH]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP9]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-INTERLEAVE1-SVE2P1: [[FOR_BODY]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ACCUM:%.*]] = phi float [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[GEP_A:%.*]] = getelementptr float, ptr [[A]], i64 [[IV]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[LOAD_A:%.*]] = load float, ptr [[GEP_A]], align 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[GEP_B:%.*]] = getelementptr float, ptr [[B]], i64 [[IV]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[LOAD_B:%.*]] = load float, ptr [[GEP_B]], align 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[MUL:%.*]] = fmul float [[LOAD_B]], [[LOAD_A]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
+; CHECK-INTERLEAVE1-SVE2P1: [[FOR_EXIT]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ADD_LCSSA:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP9]], %[[MIDDLE_BLOCK]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: ret float [[ADD_LCSSA]]
entry:
br label %for.body
for.body: ; preds = %for.body, %entry
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
%accum = phi float [ 0.0, %entry ], [ %add, %for.body ]
- %gep.a = getelementptr half, ptr %a, i64 %iv
- %load.a = load half, ptr %gep.a, align 1
- %ext.a = fpext half %load.a to float
- %gep.b = getelementptr half, ptr %b, i64 %iv
- %load.b = load half, ptr %gep.b, align 1
- %ext.b = fpext half %load.b to float
- %mul = fmul float %ext.b, %ext.a
+ %gep.a = getelementptr float, ptr %a, i64 %iv
+ %load.a = load float, ptr %gep.a, align 1
+ %gep.b = getelementptr float, ptr %b, i64 %iv
+ %load.b = load float, ptr %gep.b, align 1
+ %mul = fmul float %load.b, %load.a
%add = fadd reassoc float %mul, %accum
%iv.next = add i64 %iv, 1
%exitcond.not = icmp eq i64 %iv.next, 1024
@@ -202,6 +987,234 @@ for.exit: ; preds = %for.body
ret float %add
}
+define double @fdotp_noext_f64(ptr %a, ptr %b) #0 {
+; CHECK-INTERLEAVE1-LABEL: define double @fdotp_noext_f64(
+; CHECK-INTERLEAVE1-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
+; CHECK-INTERLEAVE1-NEXT: [[ENTRY:.*]]:
+; CHECK-INTERLEAVE1-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVE1-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 1
+; CHECK-INTERLEAVE1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK-INTERLEAVE1: [[VECTOR_PH]]:
+; CHECK-INTERLEAVE1-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVE1-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 2
+; CHECK-INTERLEAVE1-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
+; CHECK-INTERLEAVE1-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
+; CHECK-INTERLEAVE1-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-INTERLEAVE1: [[VECTOR_BODY]]:
+; CHECK-INTERLEAVE1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 2 x double> [ insertelement (<vscale x 2 x double> splat (double -0.000000e+00), double 0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[TMP4:%.*]] = getelementptr double, ptr [[A]], i64 [[INDEX]]
+; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 2 x double>, ptr [[TMP4]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP5:%.*]] = getelementptr double, ptr [[B]], i64 [[INDEX]]
+; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 2 x double>, ptr [[TMP5]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP6:%.*]] = fmul <vscale x 2 x double> [[WIDE_LOAD1]], [[WIDE_LOAD]]
+; CHECK-INTERLEAVE1-NEXT: [[TMP7]] = fadd reassoc <vscale x 2 x double> [[TMP6]], [[VEC_PHI]]
+; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
+; CHECK-INTERLEAVE1-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]]
+; CHECK-INTERLEAVE1: [[MIDDLE_BLOCK]]:
+; CHECK-INTERLEAVE1-NEXT: [[TMP9:%.*]] = call reassoc double @llvm.vector.reduce.fadd.nxv2f64(double -0.000000e+00, <vscale x 2 x double> [[TMP7]])
+; CHECK-INTERLEAVE1-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-INTERLEAVE1: [[SCALAR_PH]]:
+; CHECK-INTERLEAVE1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[BC_MERGE_RDX:%.*]] = phi double [ [[TMP9]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
+; CHECK-INTERLEAVE1-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-INTERLEAVE1: [[FOR_BODY]]:
+; CHECK-INTERLEAVE1-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[ACCUM:%.*]] = phi double [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[GEP_A:%.*]] = getelementptr double, ptr [[A]], i64 [[IV]]
+; CHECK-INTERLEAVE1-NEXT: [[LOAD_A:%.*]] = load double, ptr [[GEP_A]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[GEP_B:%.*]] = getelementptr double, ptr [[B]], i64 [[IV]]
+; CHECK-INTERLEAVE1-NEXT: [[LOAD_B:%.*]] = load double, ptr [[GEP_B]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[MUL:%.*]] = fmul double [[LOAD_B]], [[LOAD_A]]
+; CHECK-INTERLEAVE1-NEXT: [[ADD]] = fadd reassoc double [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVE1-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-INTERLEAVE1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
+; CHECK-INTERLEAVE1-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]
+; CHECK-INTERLEAVE1: [[FOR_EXIT]]:
+; CHECK-INTERLEAVE1-NEXT: [[ADD_LCSSA:%.*]] = phi double [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP9]], %[[MIDDLE_BLOCK]] ]
+; CHECK-INTERLEAVE1-NEXT: ret double [[ADD_LCSSA]]
+;
+; CHECK-INTERLEAVED-LABEL: define double @fdotp_noext_f64(
+; CHECK-INTERLEAVED-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
+; CHECK-INTERLEAVED-NEXT: [[ENTRY:.*]]:
+; CHECK-INTERLEAVED-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVED-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 2
+; CHECK-INTERLEAVED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK-INTERLEAVED: [[VECTOR_PH]]:
+; CHECK-INTERLEAVED-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVED-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 4
+; CHECK-INTERLEAVED-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
+; CHECK-INTERLEAVED-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
+; CHECK-INTERLEAVED-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-INTERLEAVED: [[VECTOR_BODY]]:
+; CHECK-INTERLEAVED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 2 x double> [ insertelement (<vscale x 2 x double> splat (double -0.000000e+00), double 0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[TMP14:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[VEC_PHI1:%.*]] = phi <vscale x 2 x double> [ splat (double -0.000000e+00), %[[VECTOR_PH]] ], [ [[TMP15:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[TMP4:%.*]] = getelementptr double, ptr [[A]], i64 [[INDEX]]
+; CHECK-INTERLEAVED-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVED-NEXT: [[TMP6:%.*]] = shl nuw i64 [[TMP5]], 1
+; CHECK-INTERLEAVED-NEXT: [[TMP7:%.*]] = getelementptr double, ptr [[TMP4]], i64 [[TMP6]]
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 2 x double>, ptr [[TMP4]], align 1
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD2:%.*]] = load <vscale x 2 x double>, ptr [[TMP7]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP8:%.*]] = getelementptr double, ptr [[B]], i64 [[INDEX]]
+; CHECK-INTERLEAVED-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVED-NEXT: [[TMP10:%.*]] = shl nuw i64 [[TMP9]], 1
+; CHECK-INTERLEAVED-NEXT: [[TMP11:%.*]] = getelementptr double, ptr [[TMP8]], i64 [[TMP10]]
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD3:%.*]] = load <vscale x 2 x double>, ptr [[TMP8]], align 1
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD4:%.*]] = load <vscale x 2 x double>, ptr [[TMP11]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP12:%.*]] = fmul <vscale x 2 x double> [[WIDE_LOAD3]], [[WIDE_LOAD]]
+; CHECK-INTERLEAVED-NEXT: [[TMP13:%.*]] = fmul <vscale x 2 x double> [[WIDE_LOAD4]], [[WIDE_LOAD2]]
+; CHECK-INTERLEAVED-NEXT: [[TMP14]] = fadd reassoc <vscale x 2 x double> [[TMP12]], [[VEC_PHI]]
+; CHECK-INTERLEAVED-NEXT: [[TMP15]] = fadd reassoc <vscale x 2 x double> [[TMP13]], [[VEC_PHI1]]
+; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
+; CHECK-INTERLEAVED-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]]
+; CHECK-INTERLEAVED: [[MIDDLE_BLOCK]]:
+; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc <vscale x 2 x double> [[TMP15]], [[TMP14]]
+; CHECK-INTERLEAVED-NEXT: [[TMP17:%.*]] = call reassoc double @llvm.vector.reduce.fadd.nxv2f64(double -0.000000e+00, <vscale x 2 x double> [[BIN_RDX]])
+; CHECK-INTERLEAVED-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-INTERLEAVED: [[SCALAR_PH]]:
+; CHECK-INTERLEAVED-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-INTERLEAVED-NEXT: [[BC_MERGE_RDX:%.*]] = phi double [ [[TMP17]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
+; CHECK-INTERLEAVED-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-INTERLEAVED: [[FOR_BODY]]:
+; CHECK-INTERLEAVED-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[ACCUM:%.*]] = phi double [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[GEP_A:%.*]] = getelementptr double, ptr [[A]], i64 [[IV]]
+; CHECK-INTERLEAVED-NEXT: [[LOAD_A:%.*]] = load double, ptr [[GEP_A]], align 1
+; CHECK-INTERLEAVED-NEXT: [[GEP_B:%.*]] = getelementptr double, ptr [[B]], i64 [[IV]]
+; CHECK-INTERLEAVED-NEXT: [[LOAD_B:%.*]] = load double, ptr [[GEP_B]], align 1
+; CHECK-INTERLEAVED-NEXT: [[MUL:%.*]] = fmul double [[LOAD_B]], [[LOAD_A]]
+; CHECK-INTERLEAVED-NEXT: [[ADD]] = fadd reassoc double [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVED-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-INTERLEAVED-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
+; CHECK-INTERLEAVED-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]
+; CHECK-INTERLEAVED: [[FOR_EXIT]]:
+; CHECK-INTERLEAVED-NEXT: [[ADD_LCSSA:%.*]] = phi double [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP17]], %[[MIDDLE_BLOCK]] ]
+; CHECK-INTERLEAVED-NEXT: ret double [[ADD_LCSSA]]
+;
+; CHECK-MAXBW-LABEL: define double @fdotp_noext_f64(
+; CHECK-MAXBW-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
+; CHECK-MAXBW-NEXT: [[ENTRY:.*]]:
+; CHECK-MAXBW-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-MAXBW-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 1
+; CHECK-MAXBW-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
+; CHECK-MAXBW-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK-MAXBW: [[VECTOR_PH]]:
+; CHECK-MAXBW-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-MAXBW-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 2
+; CHECK-MAXBW-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
+; CHECK-MAXBW-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
+; CHECK-MAXBW-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-MAXBW: [[VECTOR_BODY]]:
+; CHECK-MAXBW-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 2 x double> [ insertelement (<vscale x 2 x double> splat (double -0.000000e+00), double 0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[TMP4:%.*]] = getelementptr double, ptr [[A]], i64 [[INDEX]]
+; CHECK-MAXBW-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 2 x double>, ptr [[TMP4]], align 1
+; CHECK-MAXBW-NEXT: [[TMP5:%.*]] = getelementptr double, ptr [[B]], i64 [[INDEX]]
+; CHECK-MAXBW-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 2 x double>, ptr [[TMP5]], align 1
+; CHECK-MAXBW-NEXT: [[TMP6:%.*]] = fmul <vscale x 2 x double> [[WIDE_LOAD1]], [[WIDE_LOAD]]
+; CHECK-MAXBW-NEXT: [[TMP7]] = fadd reassoc <vscale x 2 x double> [[TMP6]], [[VEC_PHI]]
+; CHECK-MAXBW-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
+; CHECK-MAXBW-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-MAXBW-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]
+; CHECK-MAXBW: [[MIDDLE_BLOCK]]:
+; CHECK-MAXBW-NEXT: [[TMP9:%.*]] = call reassoc double @llvm.vector.reduce.fadd.nxv2f64(double -0.000000e+00, <vscale x 2 x double> [[TMP7]])
+; CHECK-MAXBW-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
+; CHECK-MAXBW-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-MAXBW: [[SCALAR_PH]]:
+; CHECK-MAXBW-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-MAXBW-NEXT: [[BC_MERGE_RDX:%.*]] = phi double [ [[TMP9]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
+; CHECK-MAXBW-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-MAXBW: [[FOR_BODY]]:
+; CHECK-MAXBW-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[ACCUM:%.*]] = phi double [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[FOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[GEP_A:%.*]] = getelementptr double, ptr [[A]], i64 [[IV]]
+; CHECK-MAXBW-NEXT: [[LOAD_A:%.*]] = load double, ptr [[GEP_A]], align 1
+; CHECK-MAXBW-NEXT: [[GEP_B:%.*]] = getelementptr double, ptr [[B]], i64 [[IV]]
+; CHECK-MAXBW-NEXT: [[LOAD_B:%.*]] = load double, ptr [[GEP_B]], align 1
+; CHECK-MAXBW-NEXT: [[MUL:%.*]] = fmul double [[LOAD_B]], [[LOAD_A]]
+; CHECK-MAXBW-NEXT: [[ADD]] = fadd reassoc double [[MUL]], [[ACCUM]]
+; CHECK-MAXBW-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-MAXBW-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
+; CHECK-MAXBW-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]]
+; CHECK-MAXBW: [[FOR_EXIT]]:
+; CHECK-MAXBW-NEXT: [[ADD_LCSSA:%.*]] = phi double [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP9]], %[[MIDDLE_BLOCK]] ]
+; CHECK-MAXBW-NEXT: ret double [[ADD_LCSSA]]
+;
+; CHECK-INTERLEAVE1-SVE2P1-LABEL: define double @fdotp_noext_f64(
+; CHECK-INTERLEAVE1-SVE2P1-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ENTRY:.*]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK-INTERLEAVE1-SVE2P1: [[VECTOR_PH]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 2
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-INTERLEAVE1-SVE2P1: [[VECTOR_BODY]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 2 x double> [ insertelement (<vscale x 2 x double> splat (double -0.000000e+00), double 0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP4:%.*]] = getelementptr double, ptr [[A]], i64 [[INDEX]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 2 x double>, ptr [[TMP4]], align 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP5:%.*]] = getelementptr double, ptr [[B]], i64 [[INDEX]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 2 x double>, ptr [[TMP5]], align 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP6:%.*]] = fmul <vscale x 2 x double> [[WIDE_LOAD1]], [[WIDE_LOAD]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP7]] = fadd reassoc <vscale x 2 x double> [[TMP6]], [[VEC_PHI]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]]
+; CHECK-INTERLEAVE1-SVE2P1: [[MIDDLE_BLOCK]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP9:%.*]] = call reassoc double @llvm.vector.reduce.fadd.nxv2f64(double -0.000000e+00, <vscale x 2 x double> [[TMP7]])
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-INTERLEAVE1-SVE2P1: [[SCALAR_PH]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[BC_MERGE_RDX:%.*]] = phi double [ [[TMP9]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-INTERLEAVE1-SVE2P1: [[FOR_BODY]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ACCUM:%.*]] = phi double [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[GEP_A:%.*]] = getelementptr double, ptr [[A]], i64 [[IV]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[LOAD_A:%.*]] = load double, ptr [[GEP_A]], align 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[GEP_B:%.*]] = getelementptr double, ptr [[B]], i64 [[IV]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[LOAD_B:%.*]] = load double, ptr [[GEP_B]], align 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[MUL:%.*]] = fmul double [[LOAD_B]], [[LOAD_A]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ADD]] = fadd reassoc double [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]
+; CHECK-INTERLEAVE1-SVE2P1: [[FOR_EXIT]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ADD_LCSSA:%.*]] = phi double [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP9]], %[[MIDDLE_BLOCK]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: ret double [[ADD_LCSSA]]
+entry:
+ br label %for.body
+
+for.body: ; preds = %for.body, %entry
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+ %accum = phi double [ 0.0, %entry ], [ %add, %for.body ]
+ %gep.a = getelementptr double, ptr %a, i64 %iv
+ %load.a = load double, ptr %gep.a, align 1
+ %gep.b = getelementptr double, ptr %b, i64 %iv
+ %load.b = load double, ptr %gep.b, align 1
+ %mul = fmul double %load.b, %load.a
+ %add = fadd reassoc double %mul, %accum
+ %iv.next = add i64 %iv, 1
+ %exitcond.not = icmp eq i64 %iv.next, 1024
+ br i1 %exitcond.not, label %for.exit, label %for.body
+
+for.exit: ; preds = %for.body
+ ret double %add
+}
+
define double @not_fdotp_different_types(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-LABEL: define double @not_fdotp_different_types(
; CHECK-INTERLEAVE1-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
@@ -222,7 +1235,7 @@ define double @not_fdotp_different_types(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-NEXT: [[TMP5]] = fadd reassoc <8 x double> [[TMP4]], [[VEC_PHI]]
; CHECK-INTERLEAVE1-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 8
; CHECK-INTERLEAVE1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
-; CHECK-INTERLEAVE1-NEXT: br i1 [[EXITCOND_NOT]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[EXITCOND_NOT]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]]
; CHECK-INTERLEAVE1: [[MIDDLE_BLOCK]]:
; CHECK-INTERLEAVE1-NEXT: [[ADD_LCSSA:%.*]] = call reassoc double @llvm.vector.reduce.fadd.v8f64(double -0.000000e+00, <8 x double> [[TMP5]])
; CHECK-INTERLEAVE1-NEXT: br label %[[FOR_EXIT:.*]]
@@ -257,7 +1270,7 @@ define double @not_fdotp_different_types(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVED-NEXT: [[TMP11]] = fadd reassoc <8 x double> [[TMP9]], [[VEC_PHI1]]
; CHECK-INTERLEAVED-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 16
; CHECK-INTERLEAVED-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
-; CHECK-INTERLEAVED-NEXT: br i1 [[EXITCOND_NOT]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[EXITCOND_NOT]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]]
; CHECK-INTERLEAVED: [[MIDDLE_BLOCK]]:
; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc <8 x double> [[TMP11]], [[TMP10]]
; CHECK-INTERLEAVED-NEXT: [[ADD_LCSSA:%.*]] = call reassoc double @llvm.vector.reduce.fadd.v8f64(double -0.000000e+00, <8 x double> [[BIN_RDX]])
@@ -291,7 +1304,7 @@ define double @not_fdotp_different_types(ptr %a, ptr %b) #0 {
; CHECK-MAXBW-NEXT: [[TMP9]] = fadd reassoc <vscale x 8 x double> [[TMP8]], [[VEC_PHI]]
; CHECK-MAXBW-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-MAXBW-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-MAXBW-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; CHECK-MAXBW-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]]
; CHECK-MAXBW: [[MIDDLE_BLOCK]]:
; CHECK-MAXBW-NEXT: [[TMP11:%.*]] = call reassoc double @llvm.vector.reduce.fadd.nxv8f64(double -0.000000e+00, <vscale x 8 x double> [[TMP9]])
; CHECK-MAXBW-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
@@ -313,11 +1326,36 @@ define double @not_fdotp_different_types(ptr %a, ptr %b) #0 {
; CHECK-MAXBW-NEXT: [[ADD]] = fadd reassoc double [[MUL]], [[ACCUM]]
; CHECK-MAXBW-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
; CHECK-MAXBW-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
-; CHECK-MAXBW-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
+; CHECK-MAXBW-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]]
; CHECK-MAXBW: [[FOR_EXIT]]:
; CHECK-MAXBW-NEXT: [[ADD_LCSSA:%.*]] = phi double [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP11]], %[[MIDDLE_BLOCK]] ]
; CHECK-MAXBW-NEXT: ret double [[ADD_LCSSA]]
;
+; CHECK-INTERLEAVE1-SVE2P1-LABEL: define double @not_fdotp_different_types(
+; CHECK-INTERLEAVE1-SVE2P1-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ENTRY:.*:]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br label %[[VECTOR_PH:.*]]
+; CHECK-INTERLEAVE1-SVE2P1: [[VECTOR_PH]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-INTERLEAVE1-SVE2P1: [[VECTOR_BODY]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[VEC_PHI:%.*]] = phi <8 x double> [ <double 0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP0:%.*]] = getelementptr half, ptr [[A]], i64 [[INDEX]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[WIDE_LOAD:%.*]] = load <8 x half>, ptr [[TMP0]], align 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP1:%.*]] = fpext <8 x half> [[WIDE_LOAD]] to <8 x double>
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP2:%.*]] = getelementptr float, ptr [[B]], i64 [[INDEX]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[WIDE_LOAD1:%.*]] = load <8 x float>, ptr [[TMP2]], align 2
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP3:%.*]] = fpext <8 x float> [[WIDE_LOAD1]] to <8 x double>
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP4:%.*]] = fmul <8 x double> [[TMP3]], [[TMP1]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP5]] = fadd reassoc <8 x double> [[TMP4]], [[VEC_PHI]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]]
+; CHECK-INTERLEAVE1-SVE2P1: [[MIDDLE_BLOCK]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP7:%.*]] = call reassoc double @llvm.vector.reduce.fadd.v8f64(double -0.000000e+00, <8 x double> [[TMP5]])
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br label %[[FOR_EXIT:.*]]
+; CHECK-INTERLEAVE1-SVE2P1: [[FOR_EXIT]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: ret double [[TMP7]]
entry:
br label %for.body
@@ -366,7 +1404,7 @@ define float @not_fdotp_not_phi(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-NEXT: [[TMP9:%.*]] = fadd reassoc <vscale x 8 x float> [[TMP8]], [[TMP7]]
; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-INTERLEAVE1-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]
; CHECK-INTERLEAVE1: [[MIDDLE_BLOCK]]:
; CHECK-INTERLEAVE1-NEXT: [[TMP11:%.*]] = call i32 @llvm.vscale.i32()
; CHECK-INTERLEAVE1-NEXT: [[TMP12:%.*]] = mul nuw i32 [[TMP11]], 8
@@ -391,7 +1429,7 @@ define float @not_fdotp_not_phi(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[EXT_B]]
; CHECK-INTERLEAVE1-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
; CHECK-INTERLEAVE1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
-; CHECK-INTERLEAVE1-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]]
; CHECK-INTERLEAVE1: [[FOR_EXIT]]:
; CHECK-INTERLEAVE1-NEXT: [[ADD_LCSSA:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[VECTOR_RECUR_EXTRACT]], %[[MIDDLE_BLOCK]] ]
; CHECK-INTERLEAVE1-NEXT: ret float [[ADD_LCSSA]]
@@ -427,7 +1465,7 @@ define float @not_fdotp_not_phi(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVED-NEXT: [[TMP15:%.*]] = fadd reassoc <vscale x 8 x float> [[TMP14]], [[TMP13]]
; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-INTERLEAVED-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-INTERLEAVED-NEXT: br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]
; CHECK-INTERLEAVED: [[MIDDLE_BLOCK]]:
; CHECK-INTERLEAVED-NEXT: [[TMP17:%.*]] = call i32 @llvm.vscale.i32()
; CHECK-INTERLEAVED-NEXT: [[TMP18:%.*]] = mul nuw i32 [[TMP17]], 8
@@ -452,7 +1490,7 @@ define float @not_fdotp_not_phi(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVED-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[EXT_B]]
; CHECK-INTERLEAVED-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
; CHECK-INTERLEAVED-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
-; CHECK-INTERLEAVED-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]]
; CHECK-INTERLEAVED: [[FOR_EXIT]]:
; CHECK-INTERLEAVED-NEXT: [[ADD_LCSSA:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[VECTOR_RECUR_EXTRACT]], %[[MIDDLE_BLOCK]] ]
; CHECK-INTERLEAVED-NEXT: ret float [[ADD_LCSSA]]
@@ -482,7 +1520,7 @@ define float @not_fdotp_not_phi(ptr %a, ptr %b) #0 {
; CHECK-MAXBW-NEXT: [[TMP9:%.*]] = fadd reassoc <vscale x 8 x float> [[TMP8]], [[TMP7]]
; CHECK-MAXBW-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-MAXBW-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-MAXBW-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
+; CHECK-MAXBW-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]]
; CHECK-MAXBW: [[MIDDLE_BLOCK]]:
; CHECK-MAXBW-NEXT: [[TMP11:%.*]] = call i32 @llvm.vscale.i32()
; CHECK-MAXBW-NEXT: [[TMP12:%.*]] = mul nuw i32 [[TMP11]], 8
@@ -507,11 +1545,65 @@ define float @not_fdotp_not_phi(ptr %a, ptr %b) #0 {
; CHECK-MAXBW-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[EXT_B]]
; CHECK-MAXBW-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
; CHECK-MAXBW-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
-; CHECK-MAXBW-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
+; CHECK-MAXBW-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP17:![0-9]+]]
; CHECK-MAXBW: [[FOR_EXIT]]:
; CHECK-MAXBW-NEXT: [[ADD_LCSSA:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[VECTOR_RECUR_EXTRACT]], %[[MIDDLE_BLOCK]] ]
; CHECK-MAXBW-NEXT: ret float [[ADD_LCSSA]]
;
+; CHECK-INTERLEAVE1-SVE2P1-LABEL: define float @not_fdotp_not_phi(
+; CHECK-INTERLEAVE1-SVE2P1-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ENTRY:.*]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 3
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK-INTERLEAVE1-SVE2P1: [[VECTOR_PH]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 8
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-INTERLEAVE1-SVE2P1: [[VECTOR_BODY]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP4:%.*]] = getelementptr half, ptr [[A]], i64 [[INDEX]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 8 x half>, ptr [[TMP4]], align 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP5:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD]] to <vscale x 8 x float>
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP6:%.*]] = getelementptr half, ptr [[B]], i64 [[INDEX]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 8 x half>, ptr [[TMP6]], align 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP7:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD1]] to <vscale x 8 x float>
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP8:%.*]] = fmul <vscale x 8 x float> [[TMP7]], [[TMP5]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP9:%.*]] = fadd reassoc <vscale x 8 x float> [[TMP8]], [[TMP7]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]
+; CHECK-INTERLEAVE1-SVE2P1: [[MIDDLE_BLOCK]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP11:%.*]] = call i32 @llvm.vscale.i32()
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP12:%.*]] = mul nuw i32 [[TMP11]], 8
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP13:%.*]] = sub i32 [[TMP12]], 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <vscale x 8 x float> [[TMP9]], i32 [[TMP13]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-INTERLEAVE1-SVE2P1: [[SCALAR_PH]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[SCALAR_RECUR_INIT:%.*]] = phi float [ [[VECTOR_RECUR_EXTRACT]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-INTERLEAVE1-SVE2P1: [[FOR_BODY]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ACCUM:%.*]] = phi float [ [[SCALAR_RECUR_INIT]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[GEP_A:%.*]] = getelementptr half, ptr [[A]], i64 [[IV]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[LOAD_A:%.*]] = load half, ptr [[GEP_A]], align 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[EXT_A:%.*]] = fpext half [[LOAD_A]] to float
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[GEP_B:%.*]] = getelementptr half, ptr [[B]], i64 [[IV]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[EXT_B:%.*]] = fpext half [[LOAD_B]] to float
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[MUL:%.*]] = fmul float [[EXT_B]], [[EXT_A]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[EXT_B]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]]
+; CHECK-INTERLEAVE1-SVE2P1: [[FOR_EXIT]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ADD_LCSSA:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[VECTOR_RECUR_EXTRACT]], %[[MIDDLE_BLOCK]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: ret float [[ADD_LCSSA]]
entry:
br label %for.body
@@ -534,18 +1626,17 @@ for.exit: ; preds = %for.body
ret float %add
}
-define void @not_fdotp_not_phi2(ptr %matrix, i32 %n) #0 {
-; CHECK-INTERLEAVE1-LABEL: define void @not_fdotp_not_phi2(
-; CHECK-INTERLEAVE1-SAME: ptr [[MATRIX:%.*]], i32 [[N:%.*]]) #[[ATTR0]] {
-; CHECK-INTERLEAVE1-NEXT: [[ENTRY:.*]]:
-; CHECK-INTERLEAVE1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[N]], 0
-; CHECK-INTERLEAVE1-NEXT: br i1 [[CMP]], label %[[FOR_PREHEADER:.*]], label %[[EXIT:.*]]
+define float @not_fdotp_not_phi2(ptr %matrix, i32 %n, half %a, half %a1) #0 {
+; CHECK-INTERLEAVE1-LABEL: define float @not_fdotp_not_phi2(
+; CHECK-INTERLEAVE1-SAME: ptr [[MATRIX:%.*]], i32 [[N:%.*]], half [[A:%.*]], half [[A1:%.*]]) #[[ATTR0]] {
+; CHECK-INTERLEAVE1-NEXT: [[ENTRY:.*:]]
+; CHECK-INTERLEAVE1-NEXT: br label %[[FOR_PREHEADER:.*]]
; CHECK-INTERLEAVE1: [[FOR_PREHEADER]]:
-; CHECK-INTERLEAVE1-NEXT: [[LOAD_A:%.*]] = load half, ptr null, align 1
-; CHECK-INTERLEAVE1-NEXT: [[LOAD_A1:%.*]] = load half, ptr inttoptr (i64 1 to ptr), align 1
-; CHECK-INTERLEAVE1-NEXT: [[A_EXT:%.*]] = fpext half [[LOAD_A]] to float
-; CHECK-INTERLEAVE1-NEXT: [[A_EXT1:%.*]] = fpext half [[LOAD_A1]] to float
-; CHECK-INTERLEAVE1-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64
+; CHECK-INTERLEAVE1-NEXT: [[A_EXT:%.*]] = fpext half [[A]] to float
+; CHECK-INTERLEAVE1-NEXT: [[A_EXT1:%.*]] = fpext half [[A1]] to float
+; CHECK-INTERLEAVE1-NEXT: [[TMP40:%.*]] = add i32 [[N]], -1
+; CHECK-INTERLEAVE1-NEXT: [[TMP41:%.*]] = zext i32 [[TMP40]] to i64
+; CHECK-INTERLEAVE1-NEXT: [[TMP0:%.*]] = add nuw nsw i64 [[TMP41]], 1
; CHECK-INTERLEAVE1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 4
; CHECK-INTERLEAVE1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK-INTERLEAVE1: [[VECTOR_PH]]:
@@ -603,7 +1694,7 @@ define void @not_fdotp_not_phi2(ptr %matrix, i32 %n) #0 {
; CHECK-INTERLEAVE1-NEXT: [[TMP37]] = fadd reassoc <4 x float> [[TMP36]], [[TMP26]]
; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-INTERLEAVE1-NEXT: [[TMP38:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP38]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP38]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]]
; CHECK-INTERLEAVE1: [[MIDDLE_BLOCK]]:
; CHECK-INTERLEAVE1-NEXT: [[TMP39:%.*]] = call reassoc float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[TMP37]])
; CHECK-INTERLEAVE1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]
@@ -630,26 +1721,24 @@ define void @not_fdotp_not_phi2(ptr %matrix, i32 %n) #0 {
; CHECK-INTERLEAVE1-NEXT: [[SCEVGEP]] = getelementptr half, ptr [[PTR]], i64 16
; CHECK-INTERLEAVE1-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
; CHECK-INTERLEAVE1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[IV_NEXT]], [[N]]
-; CHECK-INTERLEAVE1-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]]
; CHECK-INTERLEAVE1: [[FOR_EXIT]]:
; CHECK-INTERLEAVE1-NEXT: [[ADD_FLOAT:%.*]] = phi float [ [[ADD_1]], %[[FOR_BODY]] ], [ [[TMP39]], %[[MIDDLE_BLOCK]] ]
-; CHECK-INTERLEAVE1-NEXT: br label %[[EXIT]]
+; CHECK-INTERLEAVE1-NEXT: br label %[[EXIT:.*]]
; CHECK-INTERLEAVE1: [[EXIT]]:
-; CHECK-INTERLEAVE1-NEXT: [[RESULT:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[ADD_FLOAT]], %[[FOR_EXIT]] ]
-; CHECK-INTERLEAVE1-NEXT: store float [[RESULT]], ptr [[MATRIX]], align 4
-; CHECK-INTERLEAVE1-NEXT: ret void
+; CHECK-INTERLEAVE1-NEXT: [[RESULT:%.*]] = phi float [ [[ADD_FLOAT]], %[[FOR_EXIT]] ]
+; CHECK-INTERLEAVE1-NEXT: ret float [[RESULT]]
;
-; CHECK-INTERLEAVED-LABEL: define void @not_fdotp_not_phi2(
-; CHECK-INTERLEAVED-SAME: ptr [[MATRIX:%.*]], i32 [[N:%.*]]) #[[ATTR0]] {
-; CHECK-INTERLEAVED-NEXT: [[ENTRY:.*]]:
-; CHECK-INTERLEAVED-NEXT: [[CMP:%.*]] = icmp sgt i32 [[N]], 0
-; CHECK-INTERLEAVED-NEXT: br i1 [[CMP]], label %[[FOR_PREHEADER:.*]], label %[[EXIT:.*]]
+; CHECK-INTERLEAVED-LABEL: define float @not_fdotp_not_phi2(
+; CHECK-INTERLEAVED-SAME: ptr [[MATRIX:%.*]], i32 [[N:%.*]], half [[A:%.*]], half [[A1:%.*]]) #[[ATTR0]] {
+; CHECK-INTERLEAVED-NEXT: [[ENTRY:.*:]]
+; CHECK-INTERLEAVED-NEXT: br label %[[FOR_PREHEADER:.*]]
; CHECK-INTERLEAVED: [[FOR_PREHEADER]]:
-; CHECK-INTERLEAVED-NEXT: [[LOAD_A:%.*]] = load half, ptr null, align 1
-; CHECK-INTERLEAVED-NEXT: [[LOAD_A1:%.*]] = load half, ptr inttoptr (i64 1 to ptr), align 1
-; CHECK-INTERLEAVED-NEXT: [[A_EXT:%.*]] = fpext half [[LOAD_A]] to float
-; CHECK-INTERLEAVED-NEXT: [[A_EXT1:%.*]] = fpext half [[LOAD_A1]] to float
-; CHECK-INTERLEAVED-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64
+; CHECK-INTERLEAVED-NEXT: [[A_EXT:%.*]] = fpext half [[A]] to float
+; CHECK-INTERLEAVED-NEXT: [[A_EXT1:%.*]] = fpext half [[A1]] to float
+; CHECK-INTERLEAVED-NEXT: [[TMP74:%.*]] = add i32 [[N]], -1
+; CHECK-INTERLEAVED-NEXT: [[TMP75:%.*]] = zext i32 [[TMP74]] to i64
+; CHECK-INTERLEAVED-NEXT: [[TMP0:%.*]] = add nuw nsw i64 [[TMP75]], 1
; CHECK-INTERLEAVED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 8
; CHECK-INTERLEAVED-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK-INTERLEAVED: [[VECTOR_PH]]:
@@ -746,7 +1835,7 @@ define void @not_fdotp_not_phi2(ptr %matrix, i32 %n) #0 {
; CHECK-INTERLEAVED-NEXT: [[TMP71]] = fadd reassoc <4 x float> [[TMP69]], [[TMP49]]
; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
; CHECK-INTERLEAVED-NEXT: [[TMP72:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-INTERLEAVED-NEXT: br i1 [[TMP72]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[TMP72]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]]
; CHECK-INTERLEAVED: [[MIDDLE_BLOCK]]:
; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc <4 x float> [[TMP71]], [[TMP70]]
; CHECK-INTERLEAVED-NEXT: [[TMP73:%.*]] = call reassoc float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[BIN_RDX]])
@@ -774,26 +1863,24 @@ define void @not_fdotp_not_phi2(ptr %matrix, i32 %n) #0 {
; CHECK-INTERLEAVED-NEXT: [[SCEVGEP]] = getelementptr half, ptr [[PTR]], i64 16
; CHECK-INTERLEAVED-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
; CHECK-INTERLEAVED-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[IV_NEXT]], [[N]]
-; CHECK-INTERLEAVED-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]]
; CHECK-INTERLEAVED: [[FOR_EXIT]]:
; CHECK-INTERLEAVED-NEXT: [[ADD_FLOAT:%.*]] = phi float [ [[ADD_1]], %[[FOR_BODY]] ], [ [[TMP73]], %[[MIDDLE_BLOCK]] ]
-; CHECK-INTERLEAVED-NEXT: br label %[[EXIT]]
+; CHECK-INTERLEAVED-NEXT: br label %[[EXIT:.*]]
; CHECK-INTERLEAVED: [[EXIT]]:
-; CHECK-INTERLEAVED-NEXT: [[RESULT:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[ADD_FLOAT]], %[[FOR_EXIT]] ]
-; CHECK-INTERLEAVED-NEXT: store float [[RESULT]], ptr [[MATRIX]], align 4
-; CHECK-INTERLEAVED-NEXT: ret void
+; CHECK-INTERLEAVED-NEXT: [[RESULT:%.*]] = phi float [ [[ADD_FLOAT]], %[[FOR_EXIT]] ]
+; CHECK-INTERLEAVED-NEXT: ret float [[RESULT]]
;
-; CHECK-MAXBW-LABEL: define void @not_fdotp_not_phi2(
-; CHECK-MAXBW-SAME: ptr [[MATRIX:%.*]], i32 [[N:%.*]]) #[[ATTR0]] {
-; CHECK-MAXBW-NEXT: [[ENTRY:.*]]:
-; CHECK-MAXBW-NEXT: [[CMP:%.*]] = icmp sgt i32 [[N]], 0
-; CHECK-MAXBW-NEXT: br i1 [[CMP]], label %[[FOR_PREHEADER:.*]], label %[[EXIT:.*]]
+; CHECK-MAXBW-LABEL: define float @not_fdotp_not_phi2(
+; CHECK-MAXBW-SAME: ptr [[MATRIX:%.*]], i32 [[N:%.*]], half [[A:%.*]], half [[A1:%.*]]) #[[ATTR0]] {
+; CHECK-MAXBW-NEXT: [[ENTRY:.*:]]
+; CHECK-MAXBW-NEXT: br label %[[FOR_PREHEADER:.*]]
; CHECK-MAXBW: [[FOR_PREHEADER]]:
-; CHECK-MAXBW-NEXT: [[LOAD_A:%.*]] = load half, ptr null, align 1
-; CHECK-MAXBW-NEXT: [[LOAD_A1:%.*]] = load half, ptr inttoptr (i64 1 to ptr), align 1
-; CHECK-MAXBW-NEXT: [[A_EXT:%.*]] = fpext half [[LOAD_A]] to float
-; CHECK-MAXBW-NEXT: [[A_EXT1:%.*]] = fpext half [[LOAD_A1]] to float
-; CHECK-MAXBW-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64
+; CHECK-MAXBW-NEXT: [[A_EXT:%.*]] = fpext half [[A]] to float
+; CHECK-MAXBW-NEXT: [[A_EXT1:%.*]] = fpext half [[A1]] to float
+; CHECK-MAXBW-NEXT: [[TMP40:%.*]] = add i32 [[N]], -1
+; CHECK-MAXBW-NEXT: [[TMP41:%.*]] = zext i32 [[TMP40]] to i64
+; CHECK-MAXBW-NEXT: [[TMP0:%.*]] = add nuw nsw i64 [[TMP41]], 1
; CHECK-MAXBW-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 4
; CHECK-MAXBW-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK-MAXBW: [[VECTOR_PH]]:
@@ -851,7 +1938,7 @@ define void @not_fdotp_not_phi2(ptr %matrix, i32 %n) #0 {
; CHECK-MAXBW-NEXT: [[TMP37]] = fadd reassoc <4 x float> [[TMP36]], [[TMP26]]
; CHECK-MAXBW-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-MAXBW-NEXT: [[TMP38:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-MAXBW-NEXT: br i1 [[TMP38]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
+; CHECK-MAXBW-NEXT: br i1 [[TMP38]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP18:![0-9]+]]
; CHECK-MAXBW: [[MIDDLE_BLOCK]]:
; CHECK-MAXBW-NEXT: [[TMP39:%.*]] = call reassoc float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[TMP37]])
; CHECK-MAXBW-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]
@@ -878,32 +1965,129 @@ define void @not_fdotp_not_phi2(ptr %matrix, i32 %n) #0 {
; CHECK-MAXBW-NEXT: [[SCEVGEP]] = getelementptr half, ptr [[PTR]], i64 16
; CHECK-MAXBW-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
; CHECK-MAXBW-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[IV_NEXT]], [[N]]
-; CHECK-MAXBW-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]]
+; CHECK-MAXBW-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP19:![0-9]+]]
; CHECK-MAXBW: [[FOR_EXIT]]:
; CHECK-MAXBW-NEXT: [[ADD_FLOAT:%.*]] = phi float [ [[ADD_1]], %[[FOR_BODY]] ], [ [[TMP39]], %[[MIDDLE_BLOCK]] ]
-; CHECK-MAXBW-NEXT: br label %[[EXIT]]
+; CHECK-MAXBW-NEXT: br label %[[EXIT:.*]]
; CHECK-MAXBW: [[EXIT]]:
-; CHECK-MAXBW-NEXT: [[RESULT:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[ADD_FLOAT]], %[[FOR_EXIT]] ]
-; CHECK-MAXBW-NEXT: store float [[RESULT]], ptr [[MATRIX]], align 4
-; CHECK-MAXBW-NEXT: ret void
+; CHECK-MAXBW-NEXT: [[RESULT:%.*]] = phi float [ [[ADD_FLOAT]], %[[FOR_EXIT]] ]
+; CHECK-MAXBW-NEXT: ret float [[RESULT]]
;
+; CHECK-INTERLEAVE1-SVE2P1-LABEL: define float @not_fdotp_not_phi2(
+; CHECK-INTERLEAVE1-SVE2P1-SAME: ptr [[MATRIX:%.*]], i32 [[N:%.*]], half [[A:%.*]], half [[A1:%.*]]) #[[ATTR0]] {
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ENTRY:.*:]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br label %[[FOR_PREHEADER:.*]]
+; CHECK-INTERLEAVE1-SVE2P1: [[FOR_PREHEADER]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[A_EXT:%.*]] = fpext half [[A]] to float
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[A_EXT1:%.*]] = fpext half [[A1]] to float
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP2]], 4
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK-INTERLEAVE1-SVE2P1: [[VECTOR_PH]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP2]], 4
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP2]], [[N_MOD_VF]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP3:%.*]] = trunc i64 [[N_VEC]] to i32
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP4:%.*]] = mul i64 [[N_VEC]], 32
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[MATRIX]], i64 [[TMP4]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x float> poison, float [[A_EXT]], i64 0
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x float> [[BROADCAST_SPLATINSERT]], <4 x float> poison, <4 x i32> zeroinitializer
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <4 x float> poison, float [[A_EXT1]], i64 0
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x float> [[BROADCAST_SPLATINSERT1]], <4 x float> poison, <4 x i32> zeroinitializer
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-INTERLEAVE1-SVE2P1: [[VECTOR_BODY]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[VEC_PHI:%.*]] = phi <4 x float> [ <float 0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %[[VECTOR_PH]] ], [ [[TMP39:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 32
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 0
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP7:%.*]] = add i64 [[OFFSET_IDX]], 32
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP8:%.*]] = add i64 [[OFFSET_IDX]], 64
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP9:%.*]] = add i64 [[OFFSET_IDX]], 96
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[MATRIX]], i64 [[TMP6]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[NEXT_GEP3:%.*]] = getelementptr i8, ptr [[MATRIX]], i64 [[TMP7]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[NEXT_GEP4:%.*]] = getelementptr i8, ptr [[MATRIX]], i64 [[TMP8]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[NEXT_GEP5:%.*]] = getelementptr i8, ptr [[MATRIX]], i64 [[TMP9]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP10:%.*]] = getelementptr half, ptr [[NEXT_GEP]], i64 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP11:%.*]] = getelementptr half, ptr [[NEXT_GEP3]], i64 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP12:%.*]] = getelementptr half, ptr [[NEXT_GEP4]], i64 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP13:%.*]] = getelementptr half, ptr [[NEXT_GEP5]], i64 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP14:%.*]] = getelementptr half, ptr [[NEXT_GEP]], i64 2
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP15:%.*]] = getelementptr half, ptr [[NEXT_GEP3]], i64 2
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP16:%.*]] = getelementptr half, ptr [[NEXT_GEP4]], i64 2
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP17:%.*]] = getelementptr half, ptr [[NEXT_GEP5]], i64 2
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP18:%.*]] = load half, ptr [[TMP10]], align 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP19:%.*]] = load half, ptr [[TMP11]], align 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP20:%.*]] = load half, ptr [[TMP12]], align 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP21:%.*]] = load half, ptr [[TMP13]], align 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP22:%.*]] = insertelement <4 x half> poison, half [[TMP18]], i32 0
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP23:%.*]] = insertelement <4 x half> [[TMP22]], half [[TMP19]], i32 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP24:%.*]] = insertelement <4 x half> [[TMP23]], half [[TMP20]], i32 2
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP25:%.*]] = insertelement <4 x half> [[TMP24]], half [[TMP21]], i32 3
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP26:%.*]] = fpext <4 x half> [[TMP25]] to <4 x float>
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP27:%.*]] = fmul <4 x float> [[BROADCAST_SPLAT]], [[TMP26]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP28:%.*]] = fadd reassoc <4 x float> [[TMP27]], [[VEC_PHI]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP29:%.*]] = load half, ptr [[TMP14]], align 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP30:%.*]] = load half, ptr [[TMP15]], align 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP31:%.*]] = load half, ptr [[TMP16]], align 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP32:%.*]] = load half, ptr [[TMP17]], align 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP33:%.*]] = insertelement <4 x half> poison, half [[TMP29]], i32 0
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP34:%.*]] = insertelement <4 x half> [[TMP33]], half [[TMP30]], i32 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP35:%.*]] = insertelement <4 x half> [[TMP34]], half [[TMP31]], i32 2
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP36:%.*]] = insertelement <4 x half> [[TMP35]], half [[TMP32]], i32 3
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP37:%.*]] = fpext <4 x half> [[TMP36]] to <4 x float>
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP38:%.*]] = fmul <4 x float> [[BROADCAST_SPLAT2]], [[TMP37]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP39]] = fadd reassoc <4 x float> [[TMP38]], [[TMP28]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP40:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br i1 [[TMP40]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]]
+; CHECK-INTERLEAVE1-SVE2P1: [[MIDDLE_BLOCK]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP41:%.*]] = call reassoc float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[TMP39]])
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP2]], [[N_VEC]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-INTERLEAVE1-SVE2P1: [[SCALAR_PH]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[TMP3]], %[[MIDDLE_BLOCK]] ], [ 0, %[[FOR_PREHEADER]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[BC_RESUME_VAL6:%.*]] = phi ptr [ [[TMP5]], %[[MIDDLE_BLOCK]] ], [ [[MATRIX]], %[[FOR_PREHEADER]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP41]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[FOR_PREHEADER]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-INTERLEAVE1-SVE2P1: [[FOR_BODY]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[IV:%.*]] = phi i32 [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[PTR_IV_NEXT:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL6]], %[[SCALAR_PH]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ACCUM:%.*]] = phi float [ [[ADD_1:%.*]], %[[FOR_BODY]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[GEP_B:%.*]] = getelementptr half, ptr [[PTR_IV]], i64 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[GEP_B1:%.*]] = getelementptr half, ptr [[PTR_IV]], i64 2
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[B_EXT:%.*]] = fpext half [[LOAD_B]] to float
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[MUL:%.*]] = fmul float [[A_EXT]], [[B_EXT]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ADD:%.*]] = fadd reassoc float [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[LOAD_B1:%.*]] = load half, ptr [[GEP_B1]], align 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[B_EXT1:%.*]] = fpext half [[LOAD_B1]] to float
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[MUL_1:%.*]] = fmul float [[A_EXT1]], [[B_EXT1]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ADD_1]] = fadd reassoc float [[MUL_1]], [[ADD]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[PTR_IV_NEXT]] = getelementptr half, ptr [[PTR_IV]], i64 16
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[IV_NEXT]], [[N]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]]
+; CHECK-INTERLEAVE1-SVE2P1: [[FOR_EXIT]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ADD_FLOAT:%.*]] = phi float [ [[ADD_1]], %[[FOR_BODY]] ], [ [[TMP41]], %[[MIDDLE_BLOCK]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br label %[[EXIT:.*]]
+; CHECK-INTERLEAVE1-SVE2P1: [[EXIT]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[RESULT:%.*]] = phi float [ [[ADD_FLOAT]], %[[FOR_EXIT]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: ret float [[RESULT]]
entry:
- %cmp = icmp sgt i32 %n, 0
- br i1 %cmp, label %for.preheader, label %exit
+ br label %for.preheader
for.preheader: ; preds = %entry
- %load.a = load half, ptr inttoptr (i64 0 to ptr), align 1
- %load.a1 = load half, ptr inttoptr (i64 1 to ptr), align 1
- %a.ext = fpext half %load.a to float
- %a.ext1 = fpext half %load.a1 to float
+ %a.ext = fpext half %a to float
+ %a.ext1 = fpext half %a1 to float
br label %for.body
for.body: ; preds = %for.preheader, %for.body
%iv = phi i32 [ %iv.next, %for.body ], [ 0, %for.preheader ]
- %ptr = phi ptr [ %scevgep, %for.body ], [ %matrix, %for.preheader ]
+ %ptr.iv = phi ptr [ %ptr.iv.next, %for.body ], [ %matrix, %for.preheader ]
%accum = phi float [ %add.1, %for.body ], [ 0.0, %for.preheader ]
- %gep.b = getelementptr half, ptr %ptr, i64 1
- %gep.b1 = getelementptr half, ptr %ptr, i64 2
+ %gep.b = getelementptr half, ptr %ptr.iv, i64 1
+ %gep.b1 = getelementptr half, ptr %ptr.iv, i64 2
%load.b = load half, ptr %gep.b, align 1
%b.ext = fpext half %load.b to float
%mul = fmul float %a.ext, %b.ext
@@ -912,7 +2096,7 @@ for.body: ; preds = %for.preheader, %for.body
%b.ext1 = fpext half %load.b1 to float
%mul.1 = fmul float %a.ext1, %b.ext1
%add.1 = fadd reassoc float %mul.1, %add
- %scevgep = getelementptr half, ptr %ptr, i64 16
+ %ptr.iv.next = getelementptr half, ptr %ptr.iv, i64 16
%iv.next = add nuw nsw i32 %iv, 1
%exitcond.not = icmp eq i32 %iv.next, %n
br i1 %exitcond.not, label %for.exit, label %for.body
@@ -922,17 +2106,15 @@ for.exit: ; preds = %for.body
br label %exit
exit: ; preds = %for.exit, %entry
- %result = phi float [ 0.000000e+00, %entry ], [ %add.float, %for.exit ]
- store float %result, ptr %matrix, align 4
- ret void
+ %result = phi float [ %add.float, %for.exit ]
+ ret float %result
}
define float @not_fdotp_ext_outside_plan(ptr %a, half %b, i64 %n) #0 {
; CHECK-INTERLEAVE1-LABEL: define float @not_fdotp_ext_outside_plan(
; CHECK-INTERLEAVE1-SAME: ptr [[A:%.*]], half [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {
-; CHECK-INTERLEAVE1-NEXT: [[ENTRY:.*]]:
-; CHECK-INTERLEAVE1-NEXT: [[CMP:%.*]] = icmp eq i64 [[N]], 0
-; CHECK-INTERLEAVE1-NEXT: br i1 [[CMP]], label %[[EXIT:.*]], label %[[FOR_PH:.*]]
+; CHECK-INTERLEAVE1-NEXT: [[ENTRY:.*:]]
+; CHECK-INTERLEAVE1-NEXT: br label %[[FOR_PH:.*]]
; CHECK-INTERLEAVE1: [[FOR_PH]]:
; CHECK-INTERLEAVE1-NEXT: [[EXT_B:%.*]] = fpext half [[B]] to float
; CHECK-INTERLEAVE1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 8
@@ -953,11 +2135,11 @@ define float @not_fdotp_ext_outside_plan(ptr %a, half %b, i64 %n) #0 {
; CHECK-INTERLEAVE1-NEXT: [[TMP3]] = fadd reassoc <8 x float> [[TMP2]], [[VEC_PHI]]
; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
; CHECK-INTERLEAVE1-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]]
; CHECK-INTERLEAVE1: [[MIDDLE_BLOCK]]:
; CHECK-INTERLEAVE1-NEXT: [[TMP5:%.*]] = call reassoc float @llvm.vector.reduce.fadd.v8f32(float -0.000000e+00, <8 x float> [[TMP3]])
; CHECK-INTERLEAVE1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
-; CHECK-INTERLEAVE1-NEXT: br i1 [[CMP_N]], label %[[EXIT_LOOPEXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
; CHECK-INTERLEAVE1: [[SCALAR_PH]]:
; CHECK-INTERLEAVE1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[FOR_PH]] ]
; CHECK-INTERLEAVE1-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP5]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[FOR_PH]] ]
@@ -972,19 +2154,15 @@ define float @not_fdotp_ext_outside_plan(ptr %a, half %b, i64 %n) #0 {
; CHECK-INTERLEAVE1-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[ACCUM]]
; CHECK-INTERLEAVE1-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-INTERLEAVE1-NEXT: [[CMP_1:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
-; CHECK-INTERLEAVE1-NEXT: br i1 [[CMP_1]], label %[[EXIT_LOOPEXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]]
-; CHECK-INTERLEAVE1: [[EXIT_LOOPEXIT]]:
-; CHECK-INTERLEAVE1-NEXT: [[ADD_LCSSA:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP5]], %[[MIDDLE_BLOCK]] ]
-; CHECK-INTERLEAVE1-NEXT: br label %[[EXIT]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[CMP_1]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP17:![0-9]+]]
; CHECK-INTERLEAVE1: [[EXIT]]:
-; CHECK-INTERLEAVE1-NEXT: [[RESULT:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[ADD_LCSSA]], %[[EXIT_LOOPEXIT]] ]
+; CHECK-INTERLEAVE1-NEXT: [[RESULT:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP5]], %[[MIDDLE_BLOCK]] ]
; CHECK-INTERLEAVE1-NEXT: ret float [[RESULT]]
;
; CHECK-INTERLEAVED-LABEL: define float @not_fdotp_ext_outside_plan(
; CHECK-INTERLEAVED-SAME: ptr [[A:%.*]], half [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {
-; CHECK-INTERLEAVED-NEXT: [[ENTRY:.*]]:
-; CHECK-INTERLEAVED-NEXT: [[CMP:%.*]] = icmp eq i64 [[N]], 0
-; CHECK-INTERLEAVED-NEXT: br i1 [[CMP]], label %[[EXIT:.*]], label %[[FOR_PH:.*]]
+; CHECK-INTERLEAVED-NEXT: [[ENTRY:.*:]]
+; CHECK-INTERLEAVED-NEXT: br label %[[FOR_PH:.*]]
; CHECK-INTERLEAVED: [[FOR_PH]]:
; CHECK-INTERLEAVED-NEXT: [[EXT_B:%.*]] = fpext half [[B]] to float
; CHECK-INTERLEAVED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 16
@@ -1011,12 +2189,12 @@ define float @not_fdotp_ext_outside_plan(ptr %a, half %b, i64 %n) #0 {
; CHECK-INTERLEAVED-NEXT: [[TMP7]] = fadd reassoc <8 x float> [[TMP5]], [[VEC_PHI1]]
; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16
; CHECK-INTERLEAVED-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-INTERLEAVED-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]]
; CHECK-INTERLEAVED: [[MIDDLE_BLOCK]]:
; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc <8 x float> [[TMP7]], [[TMP6]]
; CHECK-INTERLEAVED-NEXT: [[TMP9:%.*]] = call reassoc float @llvm.vector.reduce.fadd.v8f32(float -0.000000e+00, <8 x float> [[BIN_RDX]])
; CHECK-INTERLEAVED-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
-; CHECK-INTERLEAVED-NEXT: br i1 [[CMP_N]], label %[[EXIT_LOOPEXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
; CHECK-INTERLEAVED: [[SCALAR_PH]]:
; CHECK-INTERLEAVED-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[FOR_PH]] ]
; CHECK-INTERLEAVED-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP9]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[FOR_PH]] ]
@@ -1031,19 +2209,15 @@ define float @not_fdotp_ext_outside_plan(ptr %a, half %b, i64 %n) #0 {
; CHECK-INTERLEAVED-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[ACCUM]]
; CHECK-INTERLEAVED-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-INTERLEAVED-NEXT: [[CMP_1:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
-; CHECK-INTERLEAVED-NEXT: br i1 [[CMP_1]], label %[[EXIT_LOOPEXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]]
-; CHECK-INTERLEAVED: [[EXIT_LOOPEXIT]]:
-; CHECK-INTERLEAVED-NEXT: [[ADD_LCSSA:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP9]], %[[MIDDLE_BLOCK]] ]
-; CHECK-INTERLEAVED-NEXT: br label %[[EXIT]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[CMP_1]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP17:![0-9]+]]
; CHECK-INTERLEAVED: [[EXIT]]:
-; CHECK-INTERLEAVED-NEXT: [[RESULT:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[ADD_LCSSA]], %[[EXIT_LOOPEXIT]] ]
+; CHECK-INTERLEAVED-NEXT: [[RESULT:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP9]], %[[MIDDLE_BLOCK]] ]
; CHECK-INTERLEAVED-NEXT: ret float [[RESULT]]
;
; CHECK-MAXBW-LABEL: define float @not_fdotp_ext_outside_plan(
; CHECK-MAXBW-SAME: ptr [[A:%.*]], half [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {
-; CHECK-MAXBW-NEXT: [[ENTRY:.*]]:
-; CHECK-MAXBW-NEXT: [[CMP:%.*]] = icmp eq i64 [[N]], 0
-; CHECK-MAXBW-NEXT: br i1 [[CMP]], label %[[EXIT:.*]], label %[[FOR_PH:.*]]
+; CHECK-MAXBW-NEXT: [[ENTRY:.*:]]
+; CHECK-MAXBW-NEXT: br label %[[FOR_PH:.*]]
; CHECK-MAXBW: [[FOR_PH]]:
; CHECK-MAXBW-NEXT: [[EXT_B:%.*]] = fpext half [[B]] to float
; CHECK-MAXBW-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
@@ -1068,11 +2242,11 @@ define float @not_fdotp_ext_outside_plan(ptr %a, half %b, i64 %n) #0 {
; CHECK-MAXBW-NEXT: [[TMP7]] = fadd reassoc <vscale x 8 x float> [[TMP6]], [[VEC_PHI]]
; CHECK-MAXBW-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-MAXBW-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-MAXBW-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]
+; CHECK-MAXBW-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP20:![0-9]+]]
; CHECK-MAXBW: [[MIDDLE_BLOCK]]:
; CHECK-MAXBW-NEXT: [[TMP9:%.*]] = call reassoc float @llvm.vector.reduce.fadd.nxv8f32(float -0.000000e+00, <vscale x 8 x float> [[TMP7]])
; CHECK-MAXBW-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
-; CHECK-MAXBW-NEXT: br i1 [[CMP_N]], label %[[EXIT_LOOPEXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-MAXBW-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
; CHECK-MAXBW: [[SCALAR_PH]]:
; CHECK-MAXBW-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[FOR_PH]] ]
; CHECK-MAXBW-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP9]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[FOR_PH]] ]
@@ -1087,17 +2261,60 @@ define float @not_fdotp_ext_outside_plan(ptr %a, half %b, i64 %n) #0 {
; CHECK-MAXBW-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[ACCUM]]
; CHECK-MAXBW-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-MAXBW-NEXT: [[CMP_1:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
-; CHECK-MAXBW-NEXT: br i1 [[CMP_1]], label %[[EXIT_LOOPEXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]]
-; CHECK-MAXBW: [[EXIT_LOOPEXIT]]:
-; CHECK-MAXBW-NEXT: [[ADD_LCSSA:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP9]], %[[MIDDLE_BLOCK]] ]
-; CHECK-MAXBW-NEXT: br label %[[EXIT]]
+; CHECK-MAXBW-NEXT: br i1 [[CMP_1]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP21:![0-9]+]]
; CHECK-MAXBW: [[EXIT]]:
-; CHECK-MAXBW-NEXT: [[RESULT:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[ADD_LCSSA]], %[[EXIT_LOOPEXIT]] ]
+; CHECK-MAXBW-NEXT: [[RESULT:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP9]], %[[MIDDLE_BLOCK]] ]
; CHECK-MAXBW-NEXT: ret float [[RESULT]]
;
+; CHECK-INTERLEAVE1-SVE2P1-LABEL: define float @not_fdotp_ext_outside_plan(
+; CHECK-INTERLEAVE1-SVE2P1-SAME: ptr [[A:%.*]], half [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ENTRY:.*:]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br label %[[FOR_PH:.*]]
+; CHECK-INTERLEAVE1-SVE2P1: [[FOR_PH]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[EXT_B:%.*]] = fpext half [[B]] to float
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 8
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK-INTERLEAVE1-SVE2P1: [[VECTOR_PH]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 8
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <8 x float> poison, float [[EXT_B]], i64 0
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <8 x float> [[BROADCAST_SPLATINSERT]], <8 x float> poison, <8 x i32> zeroinitializer
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-INTERLEAVE1-SVE2P1: [[VECTOR_BODY]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[VEC_PHI:%.*]] = phi <8 x float> [ <float 0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %[[VECTOR_PH]] ], [ [[TMP3:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP0:%.*]] = getelementptr inbounds half, ptr [[A]], i64 [[INDEX]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[WIDE_LOAD:%.*]] = load <8 x half>, ptr [[TMP0]], align 2
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP1:%.*]] = fpext <8 x half> [[WIDE_LOAD]] to <8 x float>
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP2:%.*]] = fmul <8 x float> [[TMP1]], [[BROADCAST_SPLAT]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP3]] = fadd reassoc <8 x float> [[TMP2]], [[VEC_PHI]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]]
+; CHECK-INTERLEAVE1-SVE2P1: [[MIDDLE_BLOCK]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP5:%.*]] = call reassoc float @llvm.vector.reduce.fadd.v8f32(float -0.000000e+00, <8 x float> [[TMP3]])
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-INTERLEAVE1-SVE2P1: [[SCALAR_PH]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[FOR_PH]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP5]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[FOR_PH]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-INTERLEAVE1-SVE2P1: [[FOR_BODY]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ACCUM:%.*]] = phi float [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[GEP_A:%.*]] = getelementptr inbounds half, ptr [[A]], i64 [[IV]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[LOAD_A:%.*]] = load half, ptr [[GEP_A]], align 2
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[EXT_A:%.*]] = fpext half [[LOAD_A]] to float
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[MUL:%.*]] = fmul float [[EXT_A]], [[EXT_B]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[CMP_1:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: br i1 [[CMP_1]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP17:![0-9]+]]
+; CHECK-INTERLEAVE1-SVE2P1: [[EXIT]]:
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[RESULT:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP5]], %[[MIDDLE_BLOCK]] ]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: ret float [[RESULT]]
entry:
- %cmp = icmp eq i64 %n, 0
- br i1 %cmp, label %exit, label %for.ph
+ br label %for.ph
for.ph: ; preds = %entry
%ext.b = fpext half %b to float
@@ -1116,6 +2333,6 @@ for.body: ; preds = %for.body.lr.ph, %fo
br i1 %cmp.1, label %exit, label %for.body
exit: ; preds = %for.cond.cleanup.loopexit, %entry
- %result = phi float [ 0.0, %entry ], [ %add, %for.body ]
+ %result = phi float [ %add, %for.body ]
ret float %result
}
>From 3e3ea734f8814aab4713d25654ee0966a5d246ba Mon Sep 17 00:00:00 2001
From: Damian Heaton <Damian.Heaton at arm.com>
Date: Tue, 2 Dec 2025 15:52:33 +0000
Subject: [PATCH 6/9] Fix Invalid costs
---
.../lib/Transforms/Vectorize/VPlanRecipes.cpp | 64 +-
.../AArch64/partial-reduce-fdot-product.ll | 644 ++++++++++++------
2 files changed, 482 insertions(+), 226 deletions(-)
diff --git a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
index 0baf7172e4443..6e5280af0bfda 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
@@ -2628,10 +2628,13 @@ void VPReductionRecipe::execute(VPTransformState &State) {
PrevInChain = NewRed;
NextInChain = NewRed;
} else if (isPartialReduction()) {
- assert(Kind == RecurKind::Add && "Unexpected partial reduction kind");
+ assert((Kind == RecurKind::Add || Kind == RecurKind::FAdd) &&
+ "Unexpected partial reduction kind");
Value *PrevInChain = State.get(getChainOp(), /*IsScalar*/ false);
NewRed = State.Builder.CreateIntrinsic(
- PrevInChain->getType(), Intrinsic::vector_partial_reduce_add,
+ PrevInChain->getType(),
+ Kind == RecurKind::Add ? Intrinsic::vector_partial_reduce_add
+ : Intrinsic::vector_partial_reduce_fadd,
{PrevInChain, NewVecOp}, nullptr, "partial.reduce");
PrevInChain = NewRed;
NextInChain = NewRed;
@@ -2703,11 +2706,58 @@ InstructionCost VPReductionRecipe::computeCost(ElementCount VF,
CondCost = Ctx.TTI.getCmpSelInstrCost(Instruction::Select, VectorTy,
CondTy, Pred, Ctx.CostKind);
}
- return CondCost + Ctx.TTI.getPartialReductionCost(
- Opcode, ElementTy, ElementTy, ElementTy, VF,
- TargetTransformInfo::PR_None,
- TargetTransformInfo::PR_None, std::nullopt,
- Ctx.CostKind);
+ if (!match(getVecOp(), m_FMul(m_VPValue(), m_VPValue()))) {
+ auto *PhiType = Ctx.Types.inferScalarType(getChainOp());
+ auto *InputType = Ctx.Types.inferScalarType(getVecOp());
+ return CondCost + Ctx.TTI.getPartialReductionCost(
+ Opcode, InputType, InputType, PhiType, VF,
+ TTI::PR_None, TTI::PR_None, {}, Ctx.CostKind);
+ }
+
+ VPRecipeBase *OpR = getVecOp()->getDefiningRecipe();
+ Type *InputTypeA = nullptr, *InputTypeB = nullptr;
+ TTI::PartialReductionExtendKind ExtAType = TTI::PR_None,
+ ExtBType = TTI::PR_None;
+
+ auto GetExtendKind = [](VPRecipeBase *R) {
+ if (!R)
+ return TTI::PR_None;
+ auto *WidenCastR = dyn_cast<VPWidenCastRecipe>(R);
+ if (!WidenCastR)
+ return TTI::PR_None;
+ if (WidenCastR->getOpcode() == Instruction::CastOps::ZExt)
+ return TTI::PR_ZeroExtend;
+ if (WidenCastR->getOpcode() == Instruction::CastOps::SExt)
+ return TTI::PR_SignExtend;
+ if (WidenCastR->getOpcode() == Instruction::CastOps::FPExt)
+ return TTI::PR_FPExtend;
+ return TTI::PR_None;
+ };
+
+ if (auto Widen = dyn_cast<VPWidenRecipe>(OpR)) {
+ unsigned WidenOpcode = Widen->getOpcode();
+ VPRecipeBase *ExtAR = Widen->getOperand(0)->getDefiningRecipe();
+ VPRecipeBase *ExtBR = Widen->getOperand(1)->getDefiningRecipe();
+ InputTypeA = Ctx.Types.inferScalarType(ExtAR ? ExtAR->getOperand(0)
+ : Widen->getOperand(0));
+ InputTypeB = Ctx.Types.inferScalarType(ExtBR ? ExtBR->getOperand(0)
+ : Widen->getOperand(1));
+ ExtAType = GetExtendKind(ExtAR);
+ ExtBType = GetExtendKind(ExtBR);
+
+ using namespace VPlanPatternMatch;
+ const APInt *C;
+ if (!ExtBR && match(Widen->getOperand(1), m_APInt(C)) &&
+ canConstantBeExtended(C, InputTypeA, ExtAType)) {
+ InputTypeB = InputTypeA;
+ ExtBType = ExtAType;
+ }
+
+ auto *PhiType = Ctx.Types.inferScalarType(getOperand(1));
+ return CondCost + Ctx.TTI.getPartialReductionCost(
+ Opcode, InputTypeA, InputTypeB, PhiType, VF,
+ ExtAType, ExtBType, WidenOpcode, Ctx.CostKind);
+ }
}
// TODO: Support any-of reductions.
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fdot-product.ll b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fdot-product.ll
index 8536cca61d164..46208a72df219 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fdot-product.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fdot-product.ll
@@ -11,81 +11,103 @@ define float @fdotp_f16_f32(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-INTERLEAVE1-NEXT: [[ENTRY:.*]]:
; CHECK-INTERLEAVE1-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64()
-; CHECK-INTERLEAVE1-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP4]], 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP4]], 3
; CHECK-INTERLEAVE1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
; CHECK-INTERLEAVE1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK-INTERLEAVE1: [[VECTOR_PH]]:
; CHECK-INTERLEAVE1-NEXT: [[TMP12:%.*]] = call i64 @llvm.vscale.i64()
-; CHECK-INTERLEAVE1-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP12]], 2
+; CHECK-INTERLEAVE1-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP12]], 8
; CHECK-INTERLEAVE1-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
; CHECK-INTERLEAVE1-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
; CHECK-INTERLEAVE1-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK-INTERLEAVE1: [[VECTOR_BODY]]:
; CHECK-INTERLEAVE1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT1:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-INTERLEAVE1-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 2 x float> [ insertelement (<vscale x 2 x float> splat (float -0.000000e+00), float 0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[TMP9:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x float> [ insertelement (<vscale x 4 x float> splat (float -0.000000e+00), float 0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], %[[VECTOR_BODY]] ]
; CHECK-INTERLEAVE1-NEXT: [[TMP0:%.*]] = getelementptr half, ptr [[A]], i64 [[INDEX]]
-; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 2 x half>, ptr [[TMP0]], align 1
-; CHECK-INTERLEAVE1-NEXT: [[TMP5:%.*]] = fpext <vscale x 2 x half> [[WIDE_LOAD]] to <vscale x 2 x float>
+; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 8 x half>, ptr [[TMP0]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP11:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD]] to <vscale x 8 x float>
; CHECK-INTERLEAVE1-NEXT: [[TMP2:%.*]] = getelementptr half, ptr [[B]], i64 [[INDEX]]
-; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD1:%.*]] = load <8 x half>, ptr [[TMP2]], align 1
-; CHECK-INTERLEAVE1-NEXT: [[TMP3:%.*]] = fpext <8 x half> [[WIDE_LOAD1]] to <8 x float>
-; CHECK-INTERLEAVE1-NEXT: [[TMP4:%.*]] = fmul <8 x float> [[TMP3]], [[TMP1]]
-; CHECK-INTERLEAVE1-NEXT: [[PARTIAL_REDUCE]] = call <4 x float> @llvm.vector.partial.reduce.fadd.v4f32.v8f32(<4 x float> [[VEC_PHI]], <8 x float> [[TMP4]])
-; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
-; CHECK-INTERLEAVE1-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
-; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 8 x half>, ptr [[TMP2]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP7:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD1]] to <vscale x 8 x float>
+; CHECK-INTERLEAVE1-NEXT: [[TMP8:%.*]] = fmul <vscale x 8 x float> [[TMP7]], [[TMP11]]
+; CHECK-INTERLEAVE1-NEXT: [[PARTIAL_REDUCE]] = call <vscale x 4 x float> @llvm.vector.partial.reduce.fadd.nxv4f32.nxv8f32(<vscale x 4 x float> [[VEC_PHI]], <vscale x 8 x float> [[TMP8]])
+; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT1]] = add nuw i64 [[INDEX]], [[TMP3]]
+; CHECK-INTERLEAVE1-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT1]], [[N_VEC]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK-INTERLEAVE1: [[MIDDLE_BLOCK]]:
-; CHECK-INTERLEAVE1-NEXT: [[TMP6:%.*]] = call reassoc float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[PARTIAL_REDUCE]])
-; CHECK-INTERLEAVE1-NEXT: br label %[[FOR_EXIT:.*]]
+; CHECK-INTERLEAVE1-NEXT: [[TMP10:%.*]] = call reassoc float @llvm.vector.reduce.fadd.nxv4f32(float -0.000000e+00, <vscale x 4 x float> [[PARTIAL_REDUCE]])
+; CHECK-INTERLEAVE1-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-INTERLEAVE1: [[SCALAR_PH]]:
+; CHECK-INTERLEAVE1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP10]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
+; CHECK-INTERLEAVE1-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-INTERLEAVE1: [[FOR_BODY]]:
+; CHECK-INTERLEAVE1-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[ACCUM:%.*]] = phi float [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[GEP_A:%.*]] = getelementptr half, ptr [[A]], i64 [[IV]]
+; CHECK-INTERLEAVE1-NEXT: [[LOAD_A:%.*]] = load half, ptr [[GEP_A]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[EXT_A:%.*]] = fpext half [[LOAD_A]] to float
+; CHECK-INTERLEAVE1-NEXT: [[GEP_B:%.*]] = getelementptr half, ptr [[B]], i64 [[IV]]
+; CHECK-INTERLEAVE1-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[EXT_B:%.*]] = fpext half [[LOAD_B]] to float
+; CHECK-INTERLEAVE1-NEXT: [[MUL:%.*]] = fmul float [[EXT_B]], [[EXT_A]]
+; CHECK-INTERLEAVE1-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add i64 [[IV]], 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
+; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP5]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK-INTERLEAVE1: [[FOR_EXIT]]:
+; CHECK-INTERLEAVE1-NEXT: [[TMP6:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP10]], %[[MIDDLE_BLOCK]] ]
; CHECK-INTERLEAVE1-NEXT: ret float [[TMP6]]
;
; CHECK-INTERLEAVED-LABEL: define float @fdotp_f16_f32(
; CHECK-INTERLEAVED-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-INTERLEAVED-NEXT: [[ENTRY:.*]]:
; CHECK-INTERLEAVED-NEXT: [[TMP10:%.*]] = call i64 @llvm.vscale.i64()
-; CHECK-INTERLEAVED-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP10]], 2
+; CHECK-INTERLEAVED-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP10]], 4
; CHECK-INTERLEAVED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
; CHECK-INTERLEAVED-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK-INTERLEAVED: [[VECTOR_PH]]:
; CHECK-INTERLEAVED-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
-; CHECK-INTERLEAVED-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 4
+; CHECK-INTERLEAVED-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 16
; CHECK-INTERLEAVED-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
; CHECK-INTERLEAVED-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
; CHECK-INTERLEAVED-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK-INTERLEAVED: [[VECTOR_BODY]]:
; CHECK-INTERLEAVED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT1:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-INTERLEAVED-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 2 x float> [ insertelement (<vscale x 2 x float> splat (float -0.000000e+00), float 0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[TMP18:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-INTERLEAVED-NEXT: [[VEC_PHI1:%.*]] = phi <vscale x 2 x float> [ splat (float -0.000000e+00), %[[VECTOR_PH]] ], [ [[TMP19:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x float> [ insertelement (<vscale x 4 x float> splat (float -0.000000e+00), float 0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[VEC_PHI1:%.*]] = phi <vscale x 4 x float> [ insertelement (<vscale x 4 x float> splat (float -0.000000e+00), float -0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE5:%.*]], %[[VECTOR_BODY]] ]
; CHECK-INTERLEAVED-NEXT: [[TMP0:%.*]] = getelementptr half, ptr [[A]], i64 [[INDEX]]
; CHECK-INTERLEAVED-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
-; CHECK-INTERLEAVED-NEXT: [[TMP6:%.*]] = shl nuw i64 [[TMP5]], 1
+; CHECK-INTERLEAVED-NEXT: [[TMP6:%.*]] = shl nuw i64 [[TMP5]], 3
; CHECK-INTERLEAVED-NEXT: [[TMP7:%.*]] = getelementptr half, ptr [[TMP0]], i64 [[TMP6]]
-; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 2 x half>, ptr [[TMP0]], align 1
-; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD2:%.*]] = load <vscale x 2 x half>, ptr [[TMP7]], align 1
-; CHECK-INTERLEAVED-NEXT: [[TMP8:%.*]] = fpext <vscale x 2 x half> [[WIDE_LOAD]] to <vscale x 2 x float>
-; CHECK-INTERLEAVED-NEXT: [[TMP9:%.*]] = fpext <vscale x 2 x half> [[WIDE_LOAD2]] to <vscale x 2 x float>
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 8 x half>, ptr [[TMP0]], align 1
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD2:%.*]] = load <vscale x 8 x half>, ptr [[TMP7]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP8:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD]] to <vscale x 8 x float>
+; CHECK-INTERLEAVED-NEXT: [[TMP9:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD2]] to <vscale x 8 x float>
; CHECK-INTERLEAVED-NEXT: [[TMP4:%.*]] = getelementptr half, ptr [[B]], i64 [[INDEX]]
-; CHECK-INTERLEAVED-NEXT: [[TMP5:%.*]] = getelementptr half, ptr [[TMP4]], i32 8
-; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD3:%.*]] = load <8 x half>, ptr [[TMP4]], align 1
-; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD4:%.*]] = load <8 x half>, ptr [[TMP5]], align 1
-; CHECK-INTERLEAVED-NEXT: [[TMP6:%.*]] = fpext <8 x half> [[WIDE_LOAD3]] to <8 x float>
-; CHECK-INTERLEAVED-NEXT: [[TMP7:%.*]] = fpext <8 x half> [[WIDE_LOAD4]] to <8 x float>
-; CHECK-INTERLEAVED-NEXT: [[TMP8:%.*]] = fmul <8 x float> [[TMP6]], [[TMP2]]
-; CHECK-INTERLEAVED-NEXT: [[TMP9:%.*]] = fmul <8 x float> [[TMP7]], [[TMP3]]
-; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE]] = call <4 x float> @llvm.vector.partial.reduce.fadd.v4f32.v8f32(<4 x float> [[VEC_PHI]], <8 x float> [[TMP8]])
-; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE5]] = call <4 x float> @llvm.vector.partial.reduce.fadd.v4f32.v8f32(<4 x float> [[VEC_PHI1]], <8 x float> [[TMP9]])
-; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16
-; CHECK-INTERLEAVED-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
-; CHECK-INTERLEAVED-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK-INTERLEAVED-NEXT: [[TMP20:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVED-NEXT: [[TMP21:%.*]] = shl nuw i64 [[TMP20]], 3
+; CHECK-INTERLEAVED-NEXT: [[TMP13:%.*]] = getelementptr half, ptr [[TMP4]], i64 [[TMP21]]
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD3:%.*]] = load <vscale x 8 x half>, ptr [[TMP4]], align 1
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD4:%.*]] = load <vscale x 8 x half>, ptr [[TMP13]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP14:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD3]] to <vscale x 8 x float>
+; CHECK-INTERLEAVED-NEXT: [[TMP15:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD4]] to <vscale x 8 x float>
+; CHECK-INTERLEAVED-NEXT: [[TMP16:%.*]] = fmul <vscale x 8 x float> [[TMP14]], [[TMP8]]
+; CHECK-INTERLEAVED-NEXT: [[TMP17:%.*]] = fmul <vscale x 8 x float> [[TMP15]], [[TMP9]]
+; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE]] = call <vscale x 4 x float> @llvm.vector.partial.reduce.fadd.nxv4f32.nxv8f32(<vscale x 4 x float> [[VEC_PHI]], <vscale x 8 x float> [[TMP16]])
+; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE5]] = call <vscale x 4 x float> @llvm.vector.partial.reduce.fadd.nxv4f32.nxv8f32(<vscale x 4 x float> [[VEC_PHI1]], <vscale x 8 x float> [[TMP17]])
+; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT1]] = add nuw i64 [[INDEX]], [[TMP3]]
+; CHECK-INTERLEAVED-NEXT: [[TMP18:%.*]] = icmp eq i64 [[INDEX_NEXT1]], [[N_VEC]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[TMP18]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK-INTERLEAVED: [[MIDDLE_BLOCK]]:
-; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc <vscale x 2 x float> [[TMP19]], [[TMP18]]
-; CHECK-INTERLEAVED-NEXT: [[TMP21:%.*]] = call reassoc float @llvm.vector.reduce.fadd.nxv2f32(float -0.000000e+00, <vscale x 2 x float> [[BIN_RDX]])
+; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc <vscale x 4 x float> [[PARTIAL_REDUCE5]], [[PARTIAL_REDUCE]]
+; CHECK-INTERLEAVED-NEXT: [[TMP19:%.*]] = call reassoc float @llvm.vector.reduce.fadd.nxv4f32(float -0.000000e+00, <vscale x 4 x float> [[BIN_RDX]])
; CHECK-INTERLEAVED-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
; CHECK-INTERLEAVED-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
; CHECK-INTERLEAVED: [[SCALAR_PH]]:
; CHECK-INTERLEAVED-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
-; CHECK-INTERLEAVED-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP21]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
+; CHECK-INTERLEAVED-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP19]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
; CHECK-INTERLEAVED-NEXT: br label %[[FOR_BODY:.*]]
; CHECK-INTERLEAVED: [[FOR_BODY]]:
; CHECK-INTERLEAVED-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[FOR_BODY]] ]
@@ -102,7 +124,7 @@ define float @fdotp_f16_f32(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVED-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
; CHECK-INTERLEAVED-NEXT: br i1 [[TMP12]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK-INTERLEAVED: [[FOR_EXIT]]:
-; CHECK-INTERLEAVED-NEXT: [[TMP11:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP21]], %[[MIDDLE_BLOCK]] ]
+; CHECK-INTERLEAVED-NEXT: [[TMP11:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP19]], %[[MIDDLE_BLOCK]] ]
; CHECK-INTERLEAVED-NEXT: ret float [[TMP11]]
;
; CHECK-MAXBW-LABEL: define float @fdotp_f16_f32(
@@ -133,12 +155,12 @@ define float @fdotp_f16_f32(ptr %a, ptr %b) #0 {
; CHECK-MAXBW-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-MAXBW-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK-MAXBW: [[MIDDLE_BLOCK]]:
-; CHECK-MAXBW-NEXT: [[TMP11:%.*]] = call reassoc float @llvm.vector.reduce.fadd.nxv2f32(float -0.000000e+00, <vscale x 2 x float> [[TMP10]])
+; CHECK-MAXBW-NEXT: [[TMP10:%.*]] = call reassoc float @llvm.vector.reduce.fadd.nxv4f32(float -0.000000e+00, <vscale x 4 x float> [[PARTIAL_REDUCE]])
; CHECK-MAXBW-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
; CHECK-MAXBW-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
; CHECK-MAXBW: [[SCALAR_PH]]:
; CHECK-MAXBW-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
-; CHECK-MAXBW-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP11]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
+; CHECK-MAXBW-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP10]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
; CHECK-MAXBW-NEXT: br label %[[FOR_BODY:.*]]
; CHECK-MAXBW: [[FOR_BODY]]:
; CHECK-MAXBW-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
@@ -155,7 +177,7 @@ define float @fdotp_f16_f32(ptr %a, ptr %b) #0 {
; CHECK-MAXBW-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
; CHECK-MAXBW-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK-MAXBW: [[FOR_EXIT]]:
-; CHECK-MAXBW-NEXT: [[ADD_LCSSA:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP11]], %[[MIDDLE_BLOCK]] ]
+; CHECK-MAXBW-NEXT: [[ADD_LCSSA:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP10]], %[[MIDDLE_BLOCK]] ]
; CHECK-MAXBW-NEXT: ret float [[ADD_LCSSA]]
;
; CHECK-INTERLEAVE1-SVE2P1-LABEL: define float @fdotp_f16_f32(
@@ -208,64 +230,122 @@ for.exit: ; preds = %for.body
define double @fdotp_f16_f64(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-LABEL: define double @fdotp_f16_f64(
; CHECK-INTERLEAVE1-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
-; CHECK-INTERLEAVE1-NEXT: [[ENTRY:.*:]]
-; CHECK-INTERLEAVE1-NEXT: br label %[[VECTOR_PH:.*]]
+; CHECK-INTERLEAVE1-NEXT: [[ENTRY:.*]]:
+; CHECK-INTERLEAVE1-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVE1-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP4]], 3
+; CHECK-INTERLEAVE1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK-INTERLEAVE1: [[VECTOR_PH]]:
+; CHECK-INTERLEAVE1-NEXT: [[TMP11:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVE1-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP11]], 8
+; CHECK-INTERLEAVE1-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
+; CHECK-INTERLEAVE1-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
; CHECK-INTERLEAVE1-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK-INTERLEAVE1: [[VECTOR_BODY]]:
-; CHECK-INTERLEAVE1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-INTERLEAVE1-NEXT: [[VEC_PHI:%.*]] = phi <2 x double> [ <double 0.000000e+00, double -0.000000e+00>, %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT1:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 2 x double> [ insertelement (<vscale x 2 x double> splat (double -0.000000e+00), double 0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], %[[VECTOR_BODY]] ]
; CHECK-INTERLEAVE1-NEXT: [[TMP0:%.*]] = getelementptr half, ptr [[A]], i64 [[INDEX]]
-; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD:%.*]] = load <8 x half>, ptr [[TMP0]], align 1
-; CHECK-INTERLEAVE1-NEXT: [[TMP1:%.*]] = fpext <8 x half> [[WIDE_LOAD]] to <8 x double>
+; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 8 x half>, ptr [[TMP0]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP12:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD]] to <vscale x 8 x double>
; CHECK-INTERLEAVE1-NEXT: [[TMP2:%.*]] = getelementptr half, ptr [[B]], i64 [[INDEX]]
-; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD1:%.*]] = load <8 x half>, ptr [[TMP2]], align 1
-; CHECK-INTERLEAVE1-NEXT: [[TMP3:%.*]] = fpext <8 x half> [[WIDE_LOAD1]] to <8 x double>
-; CHECK-INTERLEAVE1-NEXT: [[TMP4:%.*]] = fmul <8 x double> [[TMP3]], [[TMP1]]
-; CHECK-INTERLEAVE1-NEXT: [[PARTIAL_REDUCE]] = call <2 x double> @llvm.vector.partial.reduce.fadd.v2f64.v8f64(<2 x double> [[VEC_PHI]], <8 x double> [[TMP4]])
-; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
-; CHECK-INTERLEAVE1-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
-; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 8 x half>, ptr [[TMP2]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP7:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD1]] to <vscale x 8 x double>
+; CHECK-INTERLEAVE1-NEXT: [[TMP8:%.*]] = fmul <vscale x 8 x double> [[TMP7]], [[TMP12]]
+; CHECK-INTERLEAVE1-NEXT: [[PARTIAL_REDUCE]] = call <vscale x 2 x double> @llvm.vector.partial.reduce.fadd.nxv2f64.nxv8f64(<vscale x 2 x double> [[VEC_PHI]], <vscale x 8 x double> [[TMP8]])
+; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT1]] = add nuw i64 [[INDEX]], [[TMP3]]
+; CHECK-INTERLEAVE1-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT1]], [[N_VEC]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
; CHECK-INTERLEAVE1: [[MIDDLE_BLOCK]]:
-; CHECK-INTERLEAVE1-NEXT: [[TMP6:%.*]] = call reassoc double @llvm.vector.reduce.fadd.v2f64(double -0.000000e+00, <2 x double> [[PARTIAL_REDUCE]])
-; CHECK-INTERLEAVE1-NEXT: br label %[[FOR_EXIT:.*]]
+; CHECK-INTERLEAVE1-NEXT: [[TMP10:%.*]] = call reassoc double @llvm.vector.reduce.fadd.nxv2f64(double -0.000000e+00, <vscale x 2 x double> [[PARTIAL_REDUCE]])
+; CHECK-INTERLEAVE1-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-INTERLEAVE1: [[SCALAR_PH]]:
+; CHECK-INTERLEAVE1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[BC_MERGE_RDX:%.*]] = phi double [ [[TMP10]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
+; CHECK-INTERLEAVE1-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-INTERLEAVE1: [[FOR_BODY]]:
+; CHECK-INTERLEAVE1-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[ACCUM:%.*]] = phi double [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[GEP_A:%.*]] = getelementptr half, ptr [[A]], i64 [[IV]]
+; CHECK-INTERLEAVE1-NEXT: [[LOAD_A:%.*]] = load half, ptr [[GEP_A]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[EXT_A:%.*]] = fpext half [[LOAD_A]] to double
+; CHECK-INTERLEAVE1-NEXT: [[GEP_B:%.*]] = getelementptr half, ptr [[B]], i64 [[IV]]
+; CHECK-INTERLEAVE1-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[EXT_B:%.*]] = fpext half [[LOAD_B]] to double
+; CHECK-INTERLEAVE1-NEXT: [[MUL:%.*]] = fmul double [[EXT_B]], [[EXT_A]]
+; CHECK-INTERLEAVE1-NEXT: [[ADD]] = fadd reassoc double [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add i64 [[IV]], 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
+; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP5]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
; CHECK-INTERLEAVE1: [[FOR_EXIT]]:
+; CHECK-INTERLEAVE1-NEXT: [[TMP6:%.*]] = phi double [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP10]], %[[MIDDLE_BLOCK]] ]
; CHECK-INTERLEAVE1-NEXT: ret double [[TMP6]]
;
; CHECK-INTERLEAVED-LABEL: define double @fdotp_f16_f64(
; CHECK-INTERLEAVED-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
-; CHECK-INTERLEAVED-NEXT: [[ENTRY:.*:]]
-; CHECK-INTERLEAVED-NEXT: br label %[[VECTOR_PH:.*]]
+; CHECK-INTERLEAVED-NEXT: [[ENTRY:.*]]:
+; CHECK-INTERLEAVED-NEXT: [[TMP20:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVED-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP20]], 4
+; CHECK-INTERLEAVED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK-INTERLEAVED: [[VECTOR_PH]]:
+; CHECK-INTERLEAVED-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVED-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 16
+; CHECK-INTERLEAVED-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
+; CHECK-INTERLEAVED-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
; CHECK-INTERLEAVED-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK-INTERLEAVED: [[VECTOR_BODY]]:
-; CHECK-INTERLEAVED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-INTERLEAVED-NEXT: [[VEC_PHI:%.*]] = phi <2 x double> [ <double 0.000000e+00, double -0.000000e+00>, %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-INTERLEAVED-NEXT: [[VEC_PHI1:%.*]] = phi <2 x double> [ splat (double -0.000000e+00), %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE5:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT1:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 2 x double> [ insertelement (<vscale x 2 x double> splat (double -0.000000e+00), double 0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[VEC_PHI1:%.*]] = phi <vscale x 2 x double> [ insertelement (<vscale x 2 x double> splat (double -0.000000e+00), double -0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE5:%.*]], %[[VECTOR_BODY]] ]
; CHECK-INTERLEAVED-NEXT: [[TMP0:%.*]] = getelementptr half, ptr [[A]], i64 [[INDEX]]
-; CHECK-INTERLEAVED-NEXT: [[TMP1:%.*]] = getelementptr half, ptr [[TMP0]], i32 8
-; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD:%.*]] = load <8 x half>, ptr [[TMP0]], align 1
-; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD2:%.*]] = load <8 x half>, ptr [[TMP1]], align 1
-; CHECK-INTERLEAVED-NEXT: [[TMP2:%.*]] = fpext <8 x half> [[WIDE_LOAD]] to <8 x double>
-; CHECK-INTERLEAVED-NEXT: [[TMP3:%.*]] = fpext <8 x half> [[WIDE_LOAD2]] to <8 x double>
+; CHECK-INTERLEAVED-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVED-NEXT: [[TMP6:%.*]] = shl nuw i64 [[TMP5]], 3
+; CHECK-INTERLEAVED-NEXT: [[TMP7:%.*]] = getelementptr half, ptr [[TMP0]], i64 [[TMP6]]
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 8 x half>, ptr [[TMP0]], align 1
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD2:%.*]] = load <vscale x 8 x half>, ptr [[TMP7]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP8:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD]] to <vscale x 8 x double>
+; CHECK-INTERLEAVED-NEXT: [[TMP9:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD2]] to <vscale x 8 x double>
; CHECK-INTERLEAVED-NEXT: [[TMP4:%.*]] = getelementptr half, ptr [[B]], i64 [[INDEX]]
-; CHECK-INTERLEAVED-NEXT: [[TMP5:%.*]] = getelementptr half, ptr [[TMP4]], i32 8
-; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD3:%.*]] = load <8 x half>, ptr [[TMP4]], align 1
-; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD4:%.*]] = load <8 x half>, ptr [[TMP5]], align 1
-; CHECK-INTERLEAVED-NEXT: [[TMP6:%.*]] = fpext <8 x half> [[WIDE_LOAD3]] to <8 x double>
-; CHECK-INTERLEAVED-NEXT: [[TMP7:%.*]] = fpext <8 x half> [[WIDE_LOAD4]] to <8 x double>
-; CHECK-INTERLEAVED-NEXT: [[TMP8:%.*]] = fmul <8 x double> [[TMP6]], [[TMP2]]
-; CHECK-INTERLEAVED-NEXT: [[TMP9:%.*]] = fmul <8 x double> [[TMP7]], [[TMP3]]
-; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE]] = call <2 x double> @llvm.vector.partial.reduce.fadd.v2f64.v8f64(<2 x double> [[VEC_PHI]], <8 x double> [[TMP8]])
-; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE5]] = call <2 x double> @llvm.vector.partial.reduce.fadd.v2f64.v8f64(<2 x double> [[VEC_PHI1]], <8 x double> [[TMP9]])
-; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16
-; CHECK-INTERLEAVED-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
-; CHECK-INTERLEAVED-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK-INTERLEAVED-NEXT: [[TMP21:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVED-NEXT: [[TMP12:%.*]] = shl nuw i64 [[TMP21]], 3
+; CHECK-INTERLEAVED-NEXT: [[TMP13:%.*]] = getelementptr half, ptr [[TMP4]], i64 [[TMP12]]
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD3:%.*]] = load <vscale x 8 x half>, ptr [[TMP4]], align 1
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD4:%.*]] = load <vscale x 8 x half>, ptr [[TMP13]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP14:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD3]] to <vscale x 8 x double>
+; CHECK-INTERLEAVED-NEXT: [[TMP15:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD4]] to <vscale x 8 x double>
+; CHECK-INTERLEAVED-NEXT: [[TMP16:%.*]] = fmul <vscale x 8 x double> [[TMP14]], [[TMP8]]
+; CHECK-INTERLEAVED-NEXT: [[TMP17:%.*]] = fmul <vscale x 8 x double> [[TMP15]], [[TMP9]]
+; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE]] = call <vscale x 2 x double> @llvm.vector.partial.reduce.fadd.nxv2f64.nxv8f64(<vscale x 2 x double> [[VEC_PHI]], <vscale x 8 x double> [[TMP16]])
+; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE5]] = call <vscale x 2 x double> @llvm.vector.partial.reduce.fadd.nxv2f64.nxv8f64(<vscale x 2 x double> [[VEC_PHI1]], <vscale x 8 x double> [[TMP17]])
+; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT1]] = add nuw i64 [[INDEX]], [[TMP3]]
+; CHECK-INTERLEAVED-NEXT: [[TMP18:%.*]] = icmp eq i64 [[INDEX_NEXT1]], [[N_VEC]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[TMP18]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
; CHECK-INTERLEAVED: [[MIDDLE_BLOCK]]:
-; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc <2 x double> [[PARTIAL_REDUCE5]], [[PARTIAL_REDUCE]]
-; CHECK-INTERLEAVED-NEXT: [[TMP11:%.*]] = call reassoc double @llvm.vector.reduce.fadd.v2f64(double -0.000000e+00, <2 x double> [[BIN_RDX]])
-; CHECK-INTERLEAVED-NEXT: br label %[[FOR_EXIT:.*]]
+; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc <vscale x 2 x double> [[PARTIAL_REDUCE5]], [[PARTIAL_REDUCE]]
+; CHECK-INTERLEAVED-NEXT: [[TMP19:%.*]] = call reassoc double @llvm.vector.reduce.fadd.nxv2f64(double -0.000000e+00, <vscale x 2 x double> [[BIN_RDX]])
+; CHECK-INTERLEAVED-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-INTERLEAVED: [[SCALAR_PH]]:
+; CHECK-INTERLEAVED-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-INTERLEAVED-NEXT: [[BC_MERGE_RDX:%.*]] = phi double [ [[TMP19]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
+; CHECK-INTERLEAVED-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-INTERLEAVED: [[FOR_BODY]]:
+; CHECK-INTERLEAVED-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[ACCUM:%.*]] = phi double [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[GEP_A:%.*]] = getelementptr half, ptr [[A]], i64 [[IV]]
+; CHECK-INTERLEAVED-NEXT: [[LOAD_A:%.*]] = load half, ptr [[GEP_A]], align 1
+; CHECK-INTERLEAVED-NEXT: [[EXT_A:%.*]] = fpext half [[LOAD_A]] to double
+; CHECK-INTERLEAVED-NEXT: [[GEP_B:%.*]] = getelementptr half, ptr [[B]], i64 [[IV]]
+; CHECK-INTERLEAVED-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
+; CHECK-INTERLEAVED-NEXT: [[EXT_B:%.*]] = fpext half [[LOAD_B]] to double
+; CHECK-INTERLEAVED-NEXT: [[MUL:%.*]] = fmul double [[EXT_B]], [[EXT_A]]
+; CHECK-INTERLEAVED-NEXT: [[ADD]] = fadd reassoc double [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add i64 [[IV]], 1
+; CHECK-INTERLEAVED-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
+; CHECK-INTERLEAVED-NEXT: br i1 [[TMP10]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
; CHECK-INTERLEAVED: [[FOR_EXIT]]:
+; CHECK-INTERLEAVED-NEXT: [[TMP11:%.*]] = phi double [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP19]], %[[MIDDLE_BLOCK]] ]
; CHECK-INTERLEAVED-NEXT: ret double [[TMP11]]
;
; CHECK-MAXBW-LABEL: define double @fdotp_f16_f64(
@@ -371,64 +451,122 @@ for.exit: ; preds = %for.body
define double @fdotp_f32_f64(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-LABEL: define double @fdotp_f32_f64(
; CHECK-INTERLEAVE1-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
-; CHECK-INTERLEAVE1-NEXT: [[ENTRY:.*:]]
-; CHECK-INTERLEAVE1-NEXT: br label %[[VECTOR_PH:.*]]
+; CHECK-INTERLEAVE1-NEXT: [[ENTRY:.*]]:
+; CHECK-INTERLEAVE1-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVE1-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP4]], 2
+; CHECK-INTERLEAVE1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK-INTERLEAVE1: [[VECTOR_PH]]:
+; CHECK-INTERLEAVE1-NEXT: [[TMP11:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVE1-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP11]], 4
+; CHECK-INTERLEAVE1-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
+; CHECK-INTERLEAVE1-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
; CHECK-INTERLEAVE1-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK-INTERLEAVE1: [[VECTOR_BODY]]:
-; CHECK-INTERLEAVE1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-INTERLEAVE1-NEXT: [[VEC_PHI:%.*]] = phi <2 x double> [ <double 0.000000e+00, double -0.000000e+00>, %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT1:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 2 x double> [ insertelement (<vscale x 2 x double> splat (double -0.000000e+00), double 0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], %[[VECTOR_BODY]] ]
; CHECK-INTERLEAVE1-NEXT: [[TMP0:%.*]] = getelementptr float, ptr [[A]], i64 [[INDEX]]
-; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP0]], align 1
-; CHECK-INTERLEAVE1-NEXT: [[TMP1:%.*]] = fpext <4 x float> [[WIDE_LOAD]] to <4 x double>
+; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x float>, ptr [[TMP0]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP12:%.*]] = fpext <vscale x 4 x float> [[WIDE_LOAD]] to <vscale x 4 x double>
; CHECK-INTERLEAVE1-NEXT: [[TMP2:%.*]] = getelementptr float, ptr [[B]], i64 [[INDEX]]
-; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x float>, ptr [[TMP2]], align 1
-; CHECK-INTERLEAVE1-NEXT: [[TMP3:%.*]] = fpext <4 x float> [[WIDE_LOAD1]] to <4 x double>
-; CHECK-INTERLEAVE1-NEXT: [[TMP4:%.*]] = fmul <4 x double> [[TMP3]], [[TMP1]]
-; CHECK-INTERLEAVE1-NEXT: [[PARTIAL_REDUCE]] = call <2 x double> @llvm.vector.partial.reduce.fadd.v2f64.v4f64(<2 x double> [[VEC_PHI]], <4 x double> [[TMP4]])
-; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
-; CHECK-INTERLEAVE1-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
-; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 4 x float>, ptr [[TMP2]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP7:%.*]] = fpext <vscale x 4 x float> [[WIDE_LOAD1]] to <vscale x 4 x double>
+; CHECK-INTERLEAVE1-NEXT: [[TMP8:%.*]] = fmul <vscale x 4 x double> [[TMP7]], [[TMP12]]
+; CHECK-INTERLEAVE1-NEXT: [[PARTIAL_REDUCE]] = call <vscale x 2 x double> @llvm.vector.partial.reduce.fadd.nxv2f64.nxv4f64(<vscale x 2 x double> [[VEC_PHI]], <vscale x 4 x double> [[TMP8]])
+; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT1]] = add nuw i64 [[INDEX]], [[TMP3]]
+; CHECK-INTERLEAVE1-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT1]], [[N_VEC]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
; CHECK-INTERLEAVE1: [[MIDDLE_BLOCK]]:
-; CHECK-INTERLEAVE1-NEXT: [[TMP6:%.*]] = call reassoc double @llvm.vector.reduce.fadd.v2f64(double -0.000000e+00, <2 x double> [[PARTIAL_REDUCE]])
-; CHECK-INTERLEAVE1-NEXT: br label %[[FOR_EXIT:.*]]
+; CHECK-INTERLEAVE1-NEXT: [[TMP10:%.*]] = call reassoc double @llvm.vector.reduce.fadd.nxv2f64(double -0.000000e+00, <vscale x 2 x double> [[PARTIAL_REDUCE]])
+; CHECK-INTERLEAVE1-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-INTERLEAVE1: [[SCALAR_PH]]:
+; CHECK-INTERLEAVE1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[BC_MERGE_RDX:%.*]] = phi double [ [[TMP10]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
+; CHECK-INTERLEAVE1-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-INTERLEAVE1: [[FOR_BODY]]:
+; CHECK-INTERLEAVE1-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[ACCUM:%.*]] = phi double [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[GEP_A:%.*]] = getelementptr float, ptr [[A]], i64 [[IV]]
+; CHECK-INTERLEAVE1-NEXT: [[LOAD_A:%.*]] = load float, ptr [[GEP_A]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[EXT_A:%.*]] = fpext float [[LOAD_A]] to double
+; CHECK-INTERLEAVE1-NEXT: [[GEP_B:%.*]] = getelementptr float, ptr [[B]], i64 [[IV]]
+; CHECK-INTERLEAVE1-NEXT: [[LOAD_B:%.*]] = load float, ptr [[GEP_B]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[EXT_B:%.*]] = fpext float [[LOAD_B]] to double
+; CHECK-INTERLEAVE1-NEXT: [[MUL:%.*]] = fmul double [[EXT_B]], [[EXT_A]]
+; CHECK-INTERLEAVE1-NEXT: [[ADD]] = fadd reassoc double [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add i64 [[IV]], 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
+; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP5]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
; CHECK-INTERLEAVE1: [[FOR_EXIT]]:
+; CHECK-INTERLEAVE1-NEXT: [[TMP6:%.*]] = phi double [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP10]], %[[MIDDLE_BLOCK]] ]
; CHECK-INTERLEAVE1-NEXT: ret double [[TMP6]]
;
; CHECK-INTERLEAVED-LABEL: define double @fdotp_f32_f64(
; CHECK-INTERLEAVED-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
-; CHECK-INTERLEAVED-NEXT: [[ENTRY:.*:]]
-; CHECK-INTERLEAVED-NEXT: br label %[[VECTOR_PH:.*]]
+; CHECK-INTERLEAVED-NEXT: [[ENTRY:.*]]:
+; CHECK-INTERLEAVED-NEXT: [[TMP20:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVED-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP20]], 3
+; CHECK-INTERLEAVED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK-INTERLEAVED: [[VECTOR_PH]]:
+; CHECK-INTERLEAVED-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVED-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 8
+; CHECK-INTERLEAVED-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
+; CHECK-INTERLEAVED-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
; CHECK-INTERLEAVED-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK-INTERLEAVED: [[VECTOR_BODY]]:
-; CHECK-INTERLEAVED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-INTERLEAVED-NEXT: [[VEC_PHI:%.*]] = phi <2 x double> [ <double 0.000000e+00, double -0.000000e+00>, %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-INTERLEAVED-NEXT: [[VEC_PHI1:%.*]] = phi <2 x double> [ splat (double -0.000000e+00), %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE5:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT1:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 2 x double> [ insertelement (<vscale x 2 x double> splat (double -0.000000e+00), double 0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[VEC_PHI1:%.*]] = phi <vscale x 2 x double> [ insertelement (<vscale x 2 x double> splat (double -0.000000e+00), double -0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE5:%.*]], %[[VECTOR_BODY]] ]
; CHECK-INTERLEAVED-NEXT: [[TMP0:%.*]] = getelementptr float, ptr [[A]], i64 [[INDEX]]
-; CHECK-INTERLEAVED-NEXT: [[TMP1:%.*]] = getelementptr float, ptr [[TMP0]], i32 4
-; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP0]], align 1
-; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD2:%.*]] = load <4 x float>, ptr [[TMP1]], align 1
-; CHECK-INTERLEAVED-NEXT: [[TMP2:%.*]] = fpext <4 x float> [[WIDE_LOAD]] to <4 x double>
-; CHECK-INTERLEAVED-NEXT: [[TMP3:%.*]] = fpext <4 x float> [[WIDE_LOAD2]] to <4 x double>
+; CHECK-INTERLEAVED-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVED-NEXT: [[TMP6:%.*]] = shl nuw i64 [[TMP5]], 2
+; CHECK-INTERLEAVED-NEXT: [[TMP7:%.*]] = getelementptr float, ptr [[TMP0]], i64 [[TMP6]]
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x float>, ptr [[TMP0]], align 1
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD2:%.*]] = load <vscale x 4 x float>, ptr [[TMP7]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP8:%.*]] = fpext <vscale x 4 x float> [[WIDE_LOAD]] to <vscale x 4 x double>
+; CHECK-INTERLEAVED-NEXT: [[TMP9:%.*]] = fpext <vscale x 4 x float> [[WIDE_LOAD2]] to <vscale x 4 x double>
; CHECK-INTERLEAVED-NEXT: [[TMP4:%.*]] = getelementptr float, ptr [[B]], i64 [[INDEX]]
-; CHECK-INTERLEAVED-NEXT: [[TMP5:%.*]] = getelementptr float, ptr [[TMP4]], i32 4
-; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD3:%.*]] = load <4 x float>, ptr [[TMP4]], align 1
-; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x float>, ptr [[TMP5]], align 1
-; CHECK-INTERLEAVED-NEXT: [[TMP6:%.*]] = fpext <4 x float> [[WIDE_LOAD3]] to <4 x double>
-; CHECK-INTERLEAVED-NEXT: [[TMP7:%.*]] = fpext <4 x float> [[WIDE_LOAD4]] to <4 x double>
-; CHECK-INTERLEAVED-NEXT: [[TMP8:%.*]] = fmul <4 x double> [[TMP6]], [[TMP2]]
-; CHECK-INTERLEAVED-NEXT: [[TMP9:%.*]] = fmul <4 x double> [[TMP7]], [[TMP3]]
-; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE]] = call <2 x double> @llvm.vector.partial.reduce.fadd.v2f64.v4f64(<2 x double> [[VEC_PHI]], <4 x double> [[TMP8]])
-; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE5]] = call <2 x double> @llvm.vector.partial.reduce.fadd.v2f64.v4f64(<2 x double> [[VEC_PHI1]], <4 x double> [[TMP9]])
-; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
-; CHECK-INTERLEAVED-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
-; CHECK-INTERLEAVED-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; CHECK-INTERLEAVED-NEXT: [[TMP21:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVED-NEXT: [[TMP12:%.*]] = shl nuw i64 [[TMP21]], 2
+; CHECK-INTERLEAVED-NEXT: [[TMP13:%.*]] = getelementptr float, ptr [[TMP4]], i64 [[TMP12]]
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD3:%.*]] = load <vscale x 4 x float>, ptr [[TMP4]], align 1
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD4:%.*]] = load <vscale x 4 x float>, ptr [[TMP13]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP14:%.*]] = fpext <vscale x 4 x float> [[WIDE_LOAD3]] to <vscale x 4 x double>
+; CHECK-INTERLEAVED-NEXT: [[TMP15:%.*]] = fpext <vscale x 4 x float> [[WIDE_LOAD4]] to <vscale x 4 x double>
+; CHECK-INTERLEAVED-NEXT: [[TMP16:%.*]] = fmul <vscale x 4 x double> [[TMP14]], [[TMP8]]
+; CHECK-INTERLEAVED-NEXT: [[TMP17:%.*]] = fmul <vscale x 4 x double> [[TMP15]], [[TMP9]]
+; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE]] = call <vscale x 2 x double> @llvm.vector.partial.reduce.fadd.nxv2f64.nxv4f64(<vscale x 2 x double> [[VEC_PHI]], <vscale x 4 x double> [[TMP16]])
+; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE5]] = call <vscale x 2 x double> @llvm.vector.partial.reduce.fadd.nxv2f64.nxv4f64(<vscale x 2 x double> [[VEC_PHI1]], <vscale x 4 x double> [[TMP17]])
+; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT1]] = add nuw i64 [[INDEX]], [[TMP3]]
+; CHECK-INTERLEAVED-NEXT: [[TMP18:%.*]] = icmp eq i64 [[INDEX_NEXT1]], [[N_VEC]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[TMP18]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
; CHECK-INTERLEAVED: [[MIDDLE_BLOCK]]:
-; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc <2 x double> [[PARTIAL_REDUCE5]], [[PARTIAL_REDUCE]]
-; CHECK-INTERLEAVED-NEXT: [[TMP11:%.*]] = call reassoc double @llvm.vector.reduce.fadd.v2f64(double -0.000000e+00, <2 x double> [[BIN_RDX]])
-; CHECK-INTERLEAVED-NEXT: br label %[[FOR_EXIT:.*]]
+; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc <vscale x 2 x double> [[PARTIAL_REDUCE5]], [[PARTIAL_REDUCE]]
+; CHECK-INTERLEAVED-NEXT: [[TMP19:%.*]] = call reassoc double @llvm.vector.reduce.fadd.nxv2f64(double -0.000000e+00, <vscale x 2 x double> [[BIN_RDX]])
+; CHECK-INTERLEAVED-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-INTERLEAVED: [[SCALAR_PH]]:
+; CHECK-INTERLEAVED-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-INTERLEAVED-NEXT: [[BC_MERGE_RDX:%.*]] = phi double [ [[TMP19]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
+; CHECK-INTERLEAVED-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-INTERLEAVED: [[FOR_BODY]]:
+; CHECK-INTERLEAVED-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[ACCUM:%.*]] = phi double [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[GEP_A:%.*]] = getelementptr float, ptr [[A]], i64 [[IV]]
+; CHECK-INTERLEAVED-NEXT: [[LOAD_A:%.*]] = load float, ptr [[GEP_A]], align 1
+; CHECK-INTERLEAVED-NEXT: [[EXT_A:%.*]] = fpext float [[LOAD_A]] to double
+; CHECK-INTERLEAVED-NEXT: [[GEP_B:%.*]] = getelementptr float, ptr [[B]], i64 [[IV]]
+; CHECK-INTERLEAVED-NEXT: [[LOAD_B:%.*]] = load float, ptr [[GEP_B]], align 1
+; CHECK-INTERLEAVED-NEXT: [[EXT_B:%.*]] = fpext float [[LOAD_B]] to double
+; CHECK-INTERLEAVED-NEXT: [[MUL:%.*]] = fmul double [[EXT_B]], [[EXT_A]]
+; CHECK-INTERLEAVED-NEXT: [[ADD]] = fadd reassoc double [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add i64 [[IV]], 1
+; CHECK-INTERLEAVED-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
+; CHECK-INTERLEAVED-NEXT: br i1 [[TMP10]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
; CHECK-INTERLEAVED: [[FOR_EXIT]]:
+; CHECK-INTERLEAVED-NEXT: [[TMP11:%.*]] = phi double [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP19]], %[[MIDDLE_BLOCK]] ]
; CHECK-INTERLEAVED-NEXT: ret double [[TMP11]]
;
; CHECK-MAXBW-LABEL: define double @fdotp_f32_f64(
@@ -556,7 +694,7 @@ define half @fdotp_noext_f16(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-NEXT: [[TMP7]] = fadd reassoc <vscale x 8 x half> [[TMP6]], [[VEC_PHI]]
; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-INTERLEAVE1-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
; CHECK-INTERLEAVE1: [[MIDDLE_BLOCK]]:
; CHECK-INTERLEAVE1-NEXT: [[TMP9:%.*]] = call reassoc half @llvm.vector.reduce.fadd.nxv8f16(half 0xH8000, <vscale x 8 x half> [[TMP7]])
; CHECK-INTERLEAVE1-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
@@ -576,7 +714,7 @@ define half @fdotp_noext_f16(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-NEXT: [[ADD]] = fadd reassoc half [[MUL]], [[ACCUM]]
; CHECK-INTERLEAVE1-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
; CHECK-INTERLEAVE1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
-; CHECK-INTERLEAVE1-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]]
; CHECK-INTERLEAVE1: [[FOR_EXIT]]:
; CHECK-INTERLEAVE1-NEXT: [[ADD_LCSSA:%.*]] = phi half [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP9]], %[[MIDDLE_BLOCK]] ]
; CHECK-INTERLEAVE1-NEXT: ret half [[ADD_LCSSA]]
@@ -616,7 +754,7 @@ define half @fdotp_noext_f16(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVED-NEXT: [[TMP15]] = fadd reassoc <vscale x 8 x half> [[TMP13]], [[VEC_PHI1]]
; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-INTERLEAVED-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-INTERLEAVED-NEXT: br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
; CHECK-INTERLEAVED: [[MIDDLE_BLOCK]]:
; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc <vscale x 8 x half> [[TMP15]], [[TMP14]]
; CHECK-INTERLEAVED-NEXT: [[TMP17:%.*]] = call reassoc half @llvm.vector.reduce.fadd.nxv8f16(half 0xH8000, <vscale x 8 x half> [[BIN_RDX]])
@@ -637,7 +775,7 @@ define half @fdotp_noext_f16(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVED-NEXT: [[ADD]] = fadd reassoc half [[MUL]], [[ACCUM]]
; CHECK-INTERLEAVED-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
; CHECK-INTERLEAVED-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
-; CHECK-INTERLEAVED-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]]
; CHECK-INTERLEAVED: [[FOR_EXIT]]:
; CHECK-INTERLEAVED-NEXT: [[ADD_LCSSA:%.*]] = phi half [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP17]], %[[MIDDLE_BLOCK]] ]
; CHECK-INTERLEAVED-NEXT: ret half [[ADD_LCSSA]]
@@ -784,7 +922,7 @@ define float @fdotp_noext_f32(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-NEXT: [[TMP7]] = fadd reassoc <vscale x 4 x float> [[TMP6]], [[VEC_PHI]]
; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-INTERLEAVE1-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]
; CHECK-INTERLEAVE1: [[MIDDLE_BLOCK]]:
; CHECK-INTERLEAVE1-NEXT: [[TMP9:%.*]] = call reassoc float @llvm.vector.reduce.fadd.nxv4f32(float -0.000000e+00, <vscale x 4 x float> [[TMP7]])
; CHECK-INTERLEAVE1-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
@@ -804,7 +942,7 @@ define float @fdotp_noext_f32(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[ACCUM]]
; CHECK-INTERLEAVE1-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
; CHECK-INTERLEAVE1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
-; CHECK-INTERLEAVE1-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]]
; CHECK-INTERLEAVE1: [[FOR_EXIT]]:
; CHECK-INTERLEAVE1-NEXT: [[ADD_LCSSA:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP9]], %[[MIDDLE_BLOCK]] ]
; CHECK-INTERLEAVE1-NEXT: ret float [[ADD_LCSSA]]
@@ -844,7 +982,7 @@ define float @fdotp_noext_f32(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVED-NEXT: [[TMP15]] = fadd reassoc <vscale x 4 x float> [[TMP13]], [[VEC_PHI1]]
; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-INTERLEAVED-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-INTERLEAVED-NEXT: br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]
; CHECK-INTERLEAVED: [[MIDDLE_BLOCK]]:
; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc <vscale x 4 x float> [[TMP15]], [[TMP14]]
; CHECK-INTERLEAVED-NEXT: [[TMP17:%.*]] = call reassoc float @llvm.vector.reduce.fadd.nxv4f32(float -0.000000e+00, <vscale x 4 x float> [[BIN_RDX]])
@@ -865,7 +1003,7 @@ define float @fdotp_noext_f32(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVED-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[ACCUM]]
; CHECK-INTERLEAVED-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
; CHECK-INTERLEAVED-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
-; CHECK-INTERLEAVED-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]]
; CHECK-INTERLEAVED: [[FOR_EXIT]]:
; CHECK-INTERLEAVED-NEXT: [[ADD_LCSSA:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP17]], %[[MIDDLE_BLOCK]] ]
; CHECK-INTERLEAVED-NEXT: ret float [[ADD_LCSSA]]
@@ -1012,7 +1150,7 @@ define double @fdotp_noext_f64(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-NEXT: [[TMP7]] = fadd reassoc <vscale x 2 x double> [[TMP6]], [[VEC_PHI]]
; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-INTERLEAVE1-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]
; CHECK-INTERLEAVE1: [[MIDDLE_BLOCK]]:
; CHECK-INTERLEAVE1-NEXT: [[TMP9:%.*]] = call reassoc double @llvm.vector.reduce.fadd.nxv2f64(double -0.000000e+00, <vscale x 2 x double> [[TMP7]])
; CHECK-INTERLEAVE1-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
@@ -1032,7 +1170,7 @@ define double @fdotp_noext_f64(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-NEXT: [[ADD]] = fadd reassoc double [[MUL]], [[ACCUM]]
; CHECK-INTERLEAVE1-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
; CHECK-INTERLEAVE1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
-; CHECK-INTERLEAVE1-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]]
; CHECK-INTERLEAVE1: [[FOR_EXIT]]:
; CHECK-INTERLEAVE1-NEXT: [[ADD_LCSSA:%.*]] = phi double [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP9]], %[[MIDDLE_BLOCK]] ]
; CHECK-INTERLEAVE1-NEXT: ret double [[ADD_LCSSA]]
@@ -1072,7 +1210,7 @@ define double @fdotp_noext_f64(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVED-NEXT: [[TMP15]] = fadd reassoc <vscale x 2 x double> [[TMP13]], [[VEC_PHI1]]
; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-INTERLEAVED-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-INTERLEAVED-NEXT: br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]
; CHECK-INTERLEAVED: [[MIDDLE_BLOCK]]:
; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc <vscale x 2 x double> [[TMP15]], [[TMP14]]
; CHECK-INTERLEAVED-NEXT: [[TMP17:%.*]] = call reassoc double @llvm.vector.reduce.fadd.nxv2f64(double -0.000000e+00, <vscale x 2 x double> [[BIN_RDX]])
@@ -1093,7 +1231,7 @@ define double @fdotp_noext_f64(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVED-NEXT: [[ADD]] = fadd reassoc double [[MUL]], [[ACCUM]]
; CHECK-INTERLEAVED-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
; CHECK-INTERLEAVED-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
-; CHECK-INTERLEAVED-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]]
; CHECK-INTERLEAVED: [[FOR_EXIT]]:
; CHECK-INTERLEAVED-NEXT: [[ADD_LCSSA:%.*]] = phi double [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP17]], %[[MIDDLE_BLOCK]] ]
; CHECK-INTERLEAVED-NEXT: ret double [[ADD_LCSSA]]
@@ -1218,64 +1356,122 @@ for.exit: ; preds = %for.body
define double @not_fdotp_different_types(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-LABEL: define double @not_fdotp_different_types(
; CHECK-INTERLEAVE1-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
-; CHECK-INTERLEAVE1-NEXT: [[ENTRY:.*:]]
-; CHECK-INTERLEAVE1-NEXT: br label %[[VECTOR_PH:.*]]
+; CHECK-INTERLEAVE1-NEXT: [[ENTRY:.*]]:
+; CHECK-INTERLEAVE1-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVE1-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 3
+; CHECK-INTERLEAVE1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK-INTERLEAVE1: [[VECTOR_PH]]:
+; CHECK-INTERLEAVE1-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVE1-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 8
+; CHECK-INTERLEAVE1-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
+; CHECK-INTERLEAVE1-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
; CHECK-INTERLEAVE1-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK-INTERLEAVE1: [[VECTOR_BODY]]:
-; CHECK-INTERLEAVE1-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[IV_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-INTERLEAVE1-NEXT: [[VEC_PHI:%.*]] = phi <8 x double> [ <double 0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 8 x double> [ insertelement (<vscale x 8 x double> splat (double -0.000000e+00), double 0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[TMP9:%.*]], %[[VECTOR_BODY]] ]
; CHECK-INTERLEAVE1-NEXT: [[GEP_A:%.*]] = getelementptr half, ptr [[A]], i64 [[IV]]
-; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD:%.*]] = load <8 x half>, ptr [[GEP_A]], align 1
-; CHECK-INTERLEAVE1-NEXT: [[TMP1:%.*]] = fpext <8 x half> [[WIDE_LOAD]] to <8 x double>
+; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 8 x half>, ptr [[GEP_A]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP5:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD]] to <vscale x 8 x double>
; CHECK-INTERLEAVE1-NEXT: [[GEP_B:%.*]] = getelementptr float, ptr [[B]], i64 [[IV]]
-; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD1:%.*]] = load <8 x float>, ptr [[GEP_B]], align 2
-; CHECK-INTERLEAVE1-NEXT: [[TMP3:%.*]] = fpext <8 x float> [[WIDE_LOAD1]] to <8 x double>
-; CHECK-INTERLEAVE1-NEXT: [[TMP4:%.*]] = fmul <8 x double> [[TMP3]], [[TMP1]]
-; CHECK-INTERLEAVE1-NEXT: [[TMP5]] = fadd reassoc <8 x double> [[TMP4]], [[VEC_PHI]]
-; CHECK-INTERLEAVE1-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 8
-; CHECK-INTERLEAVE1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
-; CHECK-INTERLEAVE1-NEXT: br i1 [[EXITCOND_NOT]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]]
+; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 8 x float>, ptr [[GEP_B]], align 2
+; CHECK-INTERLEAVE1-NEXT: [[TMP7:%.*]] = fpext <vscale x 8 x float> [[WIDE_LOAD1]] to <vscale x 8 x double>
+; CHECK-INTERLEAVE1-NEXT: [[TMP8:%.*]] = fmul <vscale x 8 x double> [[TMP7]], [[TMP5]]
+; CHECK-INTERLEAVE1-NEXT: [[TMP9]] = fadd reassoc <vscale x 8 x double> [[TMP8]], [[VEC_PHI]]
+; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], [[TMP3]]
+; CHECK-INTERLEAVE1-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]]
; CHECK-INTERLEAVE1: [[MIDDLE_BLOCK]]:
-; CHECK-INTERLEAVE1-NEXT: [[ADD_LCSSA:%.*]] = call reassoc double @llvm.vector.reduce.fadd.v8f64(double -0.000000e+00, <8 x double> [[TMP5]])
-; CHECK-INTERLEAVE1-NEXT: br label %[[FOR_EXIT:.*]]
+; CHECK-INTERLEAVE1-NEXT: [[TMP11:%.*]] = call reassoc double @llvm.vector.reduce.fadd.nxv8f64(double -0.000000e+00, <vscale x 8 x double> [[TMP9]])
+; CHECK-INTERLEAVE1-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-INTERLEAVE1: [[SCALAR_PH]]:
+; CHECK-INTERLEAVE1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[BC_MERGE_RDX:%.*]] = phi double [ [[TMP11]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
+; CHECK-INTERLEAVE1-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-INTERLEAVE1: [[FOR_BODY]]:
+; CHECK-INTERLEAVE1-NEXT: [[IV1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[ACCUM:%.*]] = phi double [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[GEP_A1:%.*]] = getelementptr half, ptr [[A]], i64 [[IV1]]
+; CHECK-INTERLEAVE1-NEXT: [[LOAD_A:%.*]] = load half, ptr [[GEP_A1]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[EXT_A:%.*]] = fpext half [[LOAD_A]] to double
+; CHECK-INTERLEAVE1-NEXT: [[GEP_B1:%.*]] = getelementptr float, ptr [[B]], i64 [[IV1]]
+; CHECK-INTERLEAVE1-NEXT: [[LOAD_B:%.*]] = load float, ptr [[GEP_B1]], align 2
+; CHECK-INTERLEAVE1-NEXT: [[EXT_B:%.*]] = fpext float [[LOAD_B]] to double
+; CHECK-INTERLEAVE1-NEXT: [[MUL:%.*]] = fmul double [[EXT_B]], [[EXT_A]]
+; CHECK-INTERLEAVE1-NEXT: [[ADD]] = fadd reassoc double [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVE1-NEXT: [[IV_NEXT]] = add i64 [[IV1]], 1
+; CHECK-INTERLEAVE1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
+; CHECK-INTERLEAVE1-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]]
; CHECK-INTERLEAVE1: [[FOR_EXIT]]:
+; CHECK-INTERLEAVE1-NEXT: [[ADD_LCSSA:%.*]] = phi double [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP11]], %[[MIDDLE_BLOCK]] ]
; CHECK-INTERLEAVE1-NEXT: ret double [[ADD_LCSSA]]
;
; CHECK-INTERLEAVED-LABEL: define double @not_fdotp_different_types(
; CHECK-INTERLEAVED-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
-; CHECK-INTERLEAVED-NEXT: [[ENTRY:.*:]]
-; CHECK-INTERLEAVED-NEXT: br label %[[VECTOR_PH:.*]]
+; CHECK-INTERLEAVED-NEXT: [[ENTRY:.*]]:
+; CHECK-INTERLEAVED-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVED-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 4
+; CHECK-INTERLEAVED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK-INTERLEAVED: [[VECTOR_PH]]:
+; CHECK-INTERLEAVED-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVED-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 16
+; CHECK-INTERLEAVED-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
+; CHECK-INTERLEAVED-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
; CHECK-INTERLEAVED-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK-INTERLEAVED: [[VECTOR_BODY]]:
-; CHECK-INTERLEAVED-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[IV_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-INTERLEAVED-NEXT: [[VEC_PHI:%.*]] = phi <8 x double> [ <double 0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %[[VECTOR_PH]] ], [ [[TMP10:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-INTERLEAVED-NEXT: [[VEC_PHI1:%.*]] = phi <8 x double> [ splat (double -0.000000e+00), %[[VECTOR_PH]] ], [ [[TMP11:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 8 x double> [ insertelement (<vscale x 8 x double> splat (double -0.000000e+00), double 0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[TMP18:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[VEC_PHI1:%.*]] = phi <vscale x 8 x double> [ splat (double -0.000000e+00), %[[VECTOR_PH]] ], [ [[TMP19:%.*]], %[[VECTOR_BODY]] ]
; CHECK-INTERLEAVED-NEXT: [[GEP_A:%.*]] = getelementptr half, ptr [[A]], i64 [[IV]]
-; CHECK-INTERLEAVED-NEXT: [[TMP1:%.*]] = getelementptr half, ptr [[GEP_A]], i32 8
-; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD:%.*]] = load <8 x half>, ptr [[GEP_A]], align 1
-; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD2:%.*]] = load <8 x half>, ptr [[TMP1]], align 1
-; CHECK-INTERLEAVED-NEXT: [[TMP2:%.*]] = fpext <8 x half> [[WIDE_LOAD]] to <8 x double>
-; CHECK-INTERLEAVED-NEXT: [[TMP3:%.*]] = fpext <8 x half> [[WIDE_LOAD2]] to <8 x double>
+; CHECK-INTERLEAVED-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVED-NEXT: [[TMP6:%.*]] = shl nuw i64 [[TMP5]], 3
+; CHECK-INTERLEAVED-NEXT: [[TMP7:%.*]] = getelementptr half, ptr [[GEP_A]], i64 [[TMP6]]
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 8 x half>, ptr [[GEP_A]], align 1
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD2:%.*]] = load <vscale x 8 x half>, ptr [[TMP7]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP8:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD]] to <vscale x 8 x double>
+; CHECK-INTERLEAVED-NEXT: [[TMP9:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD2]] to <vscale x 8 x double>
; CHECK-INTERLEAVED-NEXT: [[GEP_B:%.*]] = getelementptr float, ptr [[B]], i64 [[IV]]
-; CHECK-INTERLEAVED-NEXT: [[TMP5:%.*]] = getelementptr float, ptr [[GEP_B]], i32 8
-; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD3:%.*]] = load <8 x float>, ptr [[GEP_B]], align 2
-; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD4:%.*]] = load <8 x float>, ptr [[TMP5]], align 2
-; CHECK-INTERLEAVED-NEXT: [[TMP6:%.*]] = fpext <8 x float> [[WIDE_LOAD3]] to <8 x double>
-; CHECK-INTERLEAVED-NEXT: [[TMP7:%.*]] = fpext <8 x float> [[WIDE_LOAD4]] to <8 x double>
-; CHECK-INTERLEAVED-NEXT: [[TMP8:%.*]] = fmul <8 x double> [[TMP6]], [[TMP2]]
-; CHECK-INTERLEAVED-NEXT: [[TMP9:%.*]] = fmul <8 x double> [[TMP7]], [[TMP3]]
-; CHECK-INTERLEAVED-NEXT: [[TMP10]] = fadd reassoc <8 x double> [[TMP8]], [[VEC_PHI]]
-; CHECK-INTERLEAVED-NEXT: [[TMP11]] = fadd reassoc <8 x double> [[TMP9]], [[VEC_PHI1]]
-; CHECK-INTERLEAVED-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 16
-; CHECK-INTERLEAVED-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
-; CHECK-INTERLEAVED-NEXT: br i1 [[EXITCOND_NOT]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]]
+; CHECK-INTERLEAVED-NEXT: [[TMP11:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVED-NEXT: [[TMP12:%.*]] = shl nuw i64 [[TMP11]], 3
+; CHECK-INTERLEAVED-NEXT: [[TMP13:%.*]] = getelementptr float, ptr [[GEP_B]], i64 [[TMP12]]
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD3:%.*]] = load <vscale x 8 x float>, ptr [[GEP_B]], align 2
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD4:%.*]] = load <vscale x 8 x float>, ptr [[TMP13]], align 2
+; CHECK-INTERLEAVED-NEXT: [[TMP14:%.*]] = fpext <vscale x 8 x float> [[WIDE_LOAD3]] to <vscale x 8 x double>
+; CHECK-INTERLEAVED-NEXT: [[TMP15:%.*]] = fpext <vscale x 8 x float> [[WIDE_LOAD4]] to <vscale x 8 x double>
+; CHECK-INTERLEAVED-NEXT: [[TMP16:%.*]] = fmul <vscale x 8 x double> [[TMP14]], [[TMP8]]
+; CHECK-INTERLEAVED-NEXT: [[TMP17:%.*]] = fmul <vscale x 8 x double> [[TMP15]], [[TMP9]]
+; CHECK-INTERLEAVED-NEXT: [[TMP18]] = fadd reassoc <vscale x 8 x double> [[TMP16]], [[VEC_PHI]]
+; CHECK-INTERLEAVED-NEXT: [[TMP19]] = fadd reassoc <vscale x 8 x double> [[TMP17]], [[VEC_PHI1]]
+; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], [[TMP3]]
+; CHECK-INTERLEAVED-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[TMP20]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]]
; CHECK-INTERLEAVED: [[MIDDLE_BLOCK]]:
-; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc <8 x double> [[TMP11]], [[TMP10]]
-; CHECK-INTERLEAVED-NEXT: [[ADD_LCSSA:%.*]] = call reassoc double @llvm.vector.reduce.fadd.v8f64(double -0.000000e+00, <8 x double> [[BIN_RDX]])
-; CHECK-INTERLEAVED-NEXT: br label %[[FOR_EXIT:.*]]
+; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc <vscale x 8 x double> [[TMP19]], [[TMP18]]
+; CHECK-INTERLEAVED-NEXT: [[TMP21:%.*]] = call reassoc double @llvm.vector.reduce.fadd.nxv8f64(double -0.000000e+00, <vscale x 8 x double> [[BIN_RDX]])
+; CHECK-INTERLEAVED-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-INTERLEAVED: [[SCALAR_PH]]:
+; CHECK-INTERLEAVED-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-INTERLEAVED-NEXT: [[BC_MERGE_RDX:%.*]] = phi double [ [[TMP21]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
+; CHECK-INTERLEAVED-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-INTERLEAVED: [[FOR_BODY]]:
+; CHECK-INTERLEAVED-NEXT: [[IV1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[ACCUM:%.*]] = phi double [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[GEP_A1:%.*]] = getelementptr half, ptr [[A]], i64 [[IV1]]
+; CHECK-INTERLEAVED-NEXT: [[LOAD_A:%.*]] = load half, ptr [[GEP_A1]], align 1
+; CHECK-INTERLEAVED-NEXT: [[EXT_A:%.*]] = fpext half [[LOAD_A]] to double
+; CHECK-INTERLEAVED-NEXT: [[GEP_B1:%.*]] = getelementptr float, ptr [[B]], i64 [[IV1]]
+; CHECK-INTERLEAVED-NEXT: [[LOAD_B:%.*]] = load float, ptr [[GEP_B1]], align 2
+; CHECK-INTERLEAVED-NEXT: [[EXT_B:%.*]] = fpext float [[LOAD_B]] to double
+; CHECK-INTERLEAVED-NEXT: [[MUL:%.*]] = fmul double [[EXT_B]], [[EXT_A]]
+; CHECK-INTERLEAVED-NEXT: [[ADD]] = fadd reassoc double [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVED-NEXT: [[IV_NEXT]] = add i64 [[IV1]], 1
+; CHECK-INTERLEAVED-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
+; CHECK-INTERLEAVED-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]]
; CHECK-INTERLEAVED: [[FOR_EXIT]]:
+; CHECK-INTERLEAVED-NEXT: [[ADD_LCSSA:%.*]] = phi double [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP21]], %[[MIDDLE_BLOCK]] ]
; CHECK-INTERLEAVED-NEXT: ret double [[ADD_LCSSA]]
;
; CHECK-MAXBW-LABEL: define double @not_fdotp_different_types(
@@ -1404,7 +1600,7 @@ define float @not_fdotp_not_phi(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-NEXT: [[TMP9:%.*]] = fadd reassoc <vscale x 8 x float> [[TMP8]], [[TMP7]]
; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-INTERLEAVE1-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]]
; CHECK-INTERLEAVE1: [[MIDDLE_BLOCK]]:
; CHECK-INTERLEAVE1-NEXT: [[TMP11:%.*]] = call i32 @llvm.vscale.i32()
; CHECK-INTERLEAVE1-NEXT: [[TMP12:%.*]] = mul nuw i32 [[TMP11]], 8
@@ -1429,7 +1625,7 @@ define float @not_fdotp_not_phi(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[EXT_B]]
; CHECK-INTERLEAVE1-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
; CHECK-INTERLEAVE1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
-; CHECK-INTERLEAVE1-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP17:![0-9]+]]
; CHECK-INTERLEAVE1: [[FOR_EXIT]]:
; CHECK-INTERLEAVE1-NEXT: [[ADD_LCSSA:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[VECTOR_RECUR_EXTRACT]], %[[MIDDLE_BLOCK]] ]
; CHECK-INTERLEAVE1-NEXT: ret float [[ADD_LCSSA]]
@@ -1465,7 +1661,7 @@ define float @not_fdotp_not_phi(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVED-NEXT: [[TMP15:%.*]] = fadd reassoc <vscale x 8 x float> [[TMP14]], [[TMP13]]
; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-INTERLEAVED-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-INTERLEAVED-NEXT: br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]]
; CHECK-INTERLEAVED: [[MIDDLE_BLOCK]]:
; CHECK-INTERLEAVED-NEXT: [[TMP17:%.*]] = call i32 @llvm.vscale.i32()
; CHECK-INTERLEAVED-NEXT: [[TMP18:%.*]] = mul nuw i32 [[TMP17]], 8
@@ -1490,7 +1686,7 @@ define float @not_fdotp_not_phi(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVED-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[EXT_B]]
; CHECK-INTERLEAVED-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
; CHECK-INTERLEAVED-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
-; CHECK-INTERLEAVED-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP17:![0-9]+]]
; CHECK-INTERLEAVED: [[FOR_EXIT]]:
; CHECK-INTERLEAVED-NEXT: [[ADD_LCSSA:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[VECTOR_RECUR_EXTRACT]], %[[MIDDLE_BLOCK]] ]
; CHECK-INTERLEAVED-NEXT: ret float [[ADD_LCSSA]]
@@ -1694,7 +1890,7 @@ define float @not_fdotp_not_phi2(ptr %matrix, i32 %n, half %a, half %a1) #0 {
; CHECK-INTERLEAVE1-NEXT: [[TMP37]] = fadd reassoc <4 x float> [[TMP36]], [[TMP26]]
; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-INTERLEAVE1-NEXT: [[TMP38:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP38]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP38]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP18:![0-9]+]]
; CHECK-INTERLEAVE1: [[MIDDLE_BLOCK]]:
; CHECK-INTERLEAVE1-NEXT: [[TMP39:%.*]] = call reassoc float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[TMP37]])
; CHECK-INTERLEAVE1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]
@@ -1721,7 +1917,7 @@ define float @not_fdotp_not_phi2(ptr %matrix, i32 %n, half %a, half %a1) #0 {
; CHECK-INTERLEAVE1-NEXT: [[SCEVGEP]] = getelementptr half, ptr [[PTR]], i64 16
; CHECK-INTERLEAVE1-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
; CHECK-INTERLEAVE1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[IV_NEXT]], [[N]]
-; CHECK-INTERLEAVE1-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP19:![0-9]+]]
; CHECK-INTERLEAVE1: [[FOR_EXIT]]:
; CHECK-INTERLEAVE1-NEXT: [[ADD_FLOAT:%.*]] = phi float [ [[ADD_1]], %[[FOR_BODY]] ], [ [[TMP39]], %[[MIDDLE_BLOCK]] ]
; CHECK-INTERLEAVE1-NEXT: br label %[[EXIT:.*]]
@@ -1835,7 +2031,7 @@ define float @not_fdotp_not_phi2(ptr %matrix, i32 %n, half %a, half %a1) #0 {
; CHECK-INTERLEAVED-NEXT: [[TMP71]] = fadd reassoc <4 x float> [[TMP69]], [[TMP49]]
; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
; CHECK-INTERLEAVED-NEXT: [[TMP72:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-INTERLEAVED-NEXT: br i1 [[TMP72]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[TMP72]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP18:![0-9]+]]
; CHECK-INTERLEAVED: [[MIDDLE_BLOCK]]:
; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc <4 x float> [[TMP71]], [[TMP70]]
; CHECK-INTERLEAVED-NEXT: [[TMP73:%.*]] = call reassoc float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[BIN_RDX]])
@@ -1863,7 +2059,7 @@ define float @not_fdotp_not_phi2(ptr %matrix, i32 %n, half %a, half %a1) #0 {
; CHECK-INTERLEAVED-NEXT: [[SCEVGEP]] = getelementptr half, ptr [[PTR]], i64 16
; CHECK-INTERLEAVED-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
; CHECK-INTERLEAVED-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[IV_NEXT]], [[N]]
-; CHECK-INTERLEAVED-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP19:![0-9]+]]
; CHECK-INTERLEAVED: [[FOR_EXIT]]:
; CHECK-INTERLEAVED-NEXT: [[ADD_FLOAT:%.*]] = phi float [ [[ADD_1]], %[[FOR_BODY]] ], [ [[TMP73]], %[[MIDDLE_BLOCK]] ]
; CHECK-INTERLEAVED-NEXT: br label %[[EXIT:.*]]
@@ -2117,32 +2313,36 @@ define float @not_fdotp_ext_outside_plan(ptr %a, half %b, i64 %n) #0 {
; CHECK-INTERLEAVE1-NEXT: br label %[[FOR_PH:.*]]
; CHECK-INTERLEAVE1: [[FOR_PH]]:
; CHECK-INTERLEAVE1-NEXT: [[EXT_B:%.*]] = fpext half [[B]] to float
-; CHECK-INTERLEAVE1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 8
+; CHECK-INTERLEAVE1-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVE1-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP8]], 3
+; CHECK-INTERLEAVE1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], [[TMP1]]
; CHECK-INTERLEAVE1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK-INTERLEAVE1: [[VECTOR_PH]]:
-; CHECK-INTERLEAVE1-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 8
+; CHECK-INTERLEAVE1-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVE1-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 8
+; CHECK-INTERLEAVE1-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], [[TMP3]]
; CHECK-INTERLEAVE1-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
-; CHECK-INTERLEAVE1-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <8 x float> poison, float [[EXT_B]], i64 0
-; CHECK-INTERLEAVE1-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <8 x float> [[BROADCAST_SPLATINSERT]], <8 x float> poison, <8 x i32> zeroinitializer
+; CHECK-INTERLEAVE1-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 8 x float> poison, float [[EXT_B]], i64 0
+; CHECK-INTERLEAVE1-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 8 x float> [[BROADCAST_SPLATINSERT]], <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
; CHECK-INTERLEAVE1-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK-INTERLEAVE1: [[VECTOR_BODY]]:
; CHECK-INTERLEAVE1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-INTERLEAVE1-NEXT: [[VEC_PHI:%.*]] = phi <8 x float> [ <float 0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %[[VECTOR_PH]] ], [ [[TMP3:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 8 x float> [ insertelement (<vscale x 8 x float> splat (float -0.000000e+00), float 0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ]
; CHECK-INTERLEAVE1-NEXT: [[TMP0:%.*]] = getelementptr inbounds half, ptr [[A]], i64 [[INDEX]]
-; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD:%.*]] = load <8 x half>, ptr [[TMP0]], align 2
-; CHECK-INTERLEAVE1-NEXT: [[TMP1:%.*]] = fpext <8 x half> [[WIDE_LOAD]] to <8 x float>
-; CHECK-INTERLEAVE1-NEXT: [[TMP2:%.*]] = fmul <8 x float> [[TMP1]], [[BROADCAST_SPLAT]]
-; CHECK-INTERLEAVE1-NEXT: [[TMP3]] = fadd reassoc <8 x float> [[TMP2]], [[VEC_PHI]]
-; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
+; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 8 x half>, ptr [[TMP0]], align 2
+; CHECK-INTERLEAVE1-NEXT: [[TMP5:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD]] to <vscale x 8 x float>
+; CHECK-INTERLEAVE1-NEXT: [[TMP6:%.*]] = fmul <vscale x 8 x float> [[TMP5]], [[BROADCAST_SPLAT]]
+; CHECK-INTERLEAVE1-NEXT: [[TMP7]] = fadd reassoc <vscale x 8 x float> [[TMP6]], [[VEC_PHI]]
+; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-INTERLEAVE1-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP20:![0-9]+]]
; CHECK-INTERLEAVE1: [[MIDDLE_BLOCK]]:
-; CHECK-INTERLEAVE1-NEXT: [[TMP5:%.*]] = call reassoc float @llvm.vector.reduce.fadd.v8f32(float -0.000000e+00, <8 x float> [[TMP3]])
+; CHECK-INTERLEAVE1-NEXT: [[TMP9:%.*]] = call reassoc float @llvm.vector.reduce.fadd.nxv8f32(float -0.000000e+00, <vscale x 8 x float> [[TMP7]])
; CHECK-INTERLEAVE1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
; CHECK-INTERLEAVE1-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
; CHECK-INTERLEAVE1: [[SCALAR_PH]]:
; CHECK-INTERLEAVE1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[FOR_PH]] ]
-; CHECK-INTERLEAVE1-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP5]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[FOR_PH]] ]
+; CHECK-INTERLEAVE1-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP9]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[FOR_PH]] ]
; CHECK-INTERLEAVE1-NEXT: br label %[[FOR_BODY:.*]]
; CHECK-INTERLEAVE1: [[FOR_BODY]]:
; CHECK-INTERLEAVE1-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
@@ -2154,9 +2354,9 @@ define float @not_fdotp_ext_outside_plan(ptr %a, half %b, i64 %n) #0 {
; CHECK-INTERLEAVE1-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[ACCUM]]
; CHECK-INTERLEAVE1-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-INTERLEAVE1-NEXT: [[CMP_1:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
-; CHECK-INTERLEAVE1-NEXT: br i1 [[CMP_1]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP17:![0-9]+]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[CMP_1]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP21:![0-9]+]]
; CHECK-INTERLEAVE1: [[EXIT]]:
-; CHECK-INTERLEAVE1-NEXT: [[RESULT:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP5]], %[[MIDDLE_BLOCK]] ]
+; CHECK-INTERLEAVE1-NEXT: [[RESULT:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP9]], %[[MIDDLE_BLOCK]] ]
; CHECK-INTERLEAVE1-NEXT: ret float [[RESULT]]
;
; CHECK-INTERLEAVED-LABEL: define float @not_fdotp_ext_outside_plan(
@@ -2165,39 +2365,45 @@ define float @not_fdotp_ext_outside_plan(ptr %a, half %b, i64 %n) #0 {
; CHECK-INTERLEAVED-NEXT: br label %[[FOR_PH:.*]]
; CHECK-INTERLEAVED: [[FOR_PH]]:
; CHECK-INTERLEAVED-NEXT: [[EXT_B:%.*]] = fpext half [[B]] to float
-; CHECK-INTERLEAVED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 16
+; CHECK-INTERLEAVED-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVED-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP4]], 4
+; CHECK-INTERLEAVED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], [[TMP1]]
; CHECK-INTERLEAVED-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK-INTERLEAVED: [[VECTOR_PH]]:
-; CHECK-INTERLEAVED-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 16
+; CHECK-INTERLEAVED-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVED-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 16
+; CHECK-INTERLEAVED-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], [[TMP3]]
; CHECK-INTERLEAVED-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
-; CHECK-INTERLEAVED-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <8 x float> poison, float [[EXT_B]], i64 0
-; CHECK-INTERLEAVED-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <8 x float> [[BROADCAST_SPLATINSERT]], <8 x float> poison, <8 x i32> zeroinitializer
+; CHECK-INTERLEAVED-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 8 x float> poison, float [[EXT_B]], i64 0
+; CHECK-INTERLEAVED-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 8 x float> [[BROADCAST_SPLATINSERT]], <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
; CHECK-INTERLEAVED-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK-INTERLEAVED: [[VECTOR_BODY]]:
; CHECK-INTERLEAVED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-INTERLEAVED-NEXT: [[VEC_PHI:%.*]] = phi <8 x float> [ <float 0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %[[VECTOR_PH]] ], [ [[TMP6:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-INTERLEAVED-NEXT: [[VEC_PHI1:%.*]] = phi <8 x float> [ splat (float -0.000000e+00), %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 8 x float> [ insertelement (<vscale x 8 x float> splat (float -0.000000e+00), float 0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[TMP12:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[VEC_PHI1:%.*]] = phi <vscale x 8 x float> [ splat (float -0.000000e+00), %[[VECTOR_PH]] ], [ [[TMP13:%.*]], %[[VECTOR_BODY]] ]
; CHECK-INTERLEAVED-NEXT: [[TMP0:%.*]] = getelementptr inbounds half, ptr [[A]], i64 [[INDEX]]
-; CHECK-INTERLEAVED-NEXT: [[TMP1:%.*]] = getelementptr inbounds half, ptr [[TMP0]], i32 8
-; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD:%.*]] = load <8 x half>, ptr [[TMP0]], align 2
-; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD2:%.*]] = load <8 x half>, ptr [[TMP1]], align 2
-; CHECK-INTERLEAVED-NEXT: [[TMP2:%.*]] = fpext <8 x half> [[WIDE_LOAD]] to <8 x float>
-; CHECK-INTERLEAVED-NEXT: [[TMP3:%.*]] = fpext <8 x half> [[WIDE_LOAD2]] to <8 x float>
-; CHECK-INTERLEAVED-NEXT: [[TMP4:%.*]] = fmul <8 x float> [[TMP2]], [[BROADCAST_SPLAT]]
-; CHECK-INTERLEAVED-NEXT: [[TMP5:%.*]] = fmul <8 x float> [[TMP3]], [[BROADCAST_SPLAT]]
-; CHECK-INTERLEAVED-NEXT: [[TMP6]] = fadd reassoc <8 x float> [[TMP4]], [[VEC_PHI]]
-; CHECK-INTERLEAVED-NEXT: [[TMP7]] = fadd reassoc <8 x float> [[TMP5]], [[VEC_PHI1]]
-; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16
+; CHECK-INTERLEAVED-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVED-NEXT: [[TMP6:%.*]] = shl nuw i64 [[TMP5]], 3
+; CHECK-INTERLEAVED-NEXT: [[TMP7:%.*]] = getelementptr inbounds half, ptr [[TMP0]], i64 [[TMP6]]
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 8 x half>, ptr [[TMP0]], align 2
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD2:%.*]] = load <vscale x 8 x half>, ptr [[TMP7]], align 2
+; CHECK-INTERLEAVED-NEXT: [[TMP14:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD]] to <vscale x 8 x float>
+; CHECK-INTERLEAVED-NEXT: [[TMP9:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD2]] to <vscale x 8 x float>
+; CHECK-INTERLEAVED-NEXT: [[TMP10:%.*]] = fmul <vscale x 8 x float> [[TMP14]], [[BROADCAST_SPLAT]]
+; CHECK-INTERLEAVED-NEXT: [[TMP11:%.*]] = fmul <vscale x 8 x float> [[TMP9]], [[BROADCAST_SPLAT]]
+; CHECK-INTERLEAVED-NEXT: [[TMP12]] = fadd reassoc <vscale x 8 x float> [[TMP10]], [[VEC_PHI]]
+; CHECK-INTERLEAVED-NEXT: [[TMP13]] = fadd reassoc <vscale x 8 x float> [[TMP11]], [[VEC_PHI1]]
+; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-INTERLEAVED-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-INTERLEAVED-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP20:![0-9]+]]
; CHECK-INTERLEAVED: [[MIDDLE_BLOCK]]:
-; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc <8 x float> [[TMP7]], [[TMP6]]
-; CHECK-INTERLEAVED-NEXT: [[TMP9:%.*]] = call reassoc float @llvm.vector.reduce.fadd.v8f32(float -0.000000e+00, <8 x float> [[BIN_RDX]])
+; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc <vscale x 8 x float> [[TMP13]], [[TMP12]]
+; CHECK-INTERLEAVED-NEXT: [[TMP15:%.*]] = call reassoc float @llvm.vector.reduce.fadd.nxv8f32(float -0.000000e+00, <vscale x 8 x float> [[BIN_RDX]])
; CHECK-INTERLEAVED-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
; CHECK-INTERLEAVED-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
; CHECK-INTERLEAVED: [[SCALAR_PH]]:
; CHECK-INTERLEAVED-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[FOR_PH]] ]
-; CHECK-INTERLEAVED-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP9]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[FOR_PH]] ]
+; CHECK-INTERLEAVED-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP15]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[FOR_PH]] ]
; CHECK-INTERLEAVED-NEXT: br label %[[FOR_BODY:.*]]
; CHECK-INTERLEAVED: [[FOR_BODY]]:
; CHECK-INTERLEAVED-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
@@ -2209,9 +2415,9 @@ define float @not_fdotp_ext_outside_plan(ptr %a, half %b, i64 %n) #0 {
; CHECK-INTERLEAVED-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[ACCUM]]
; CHECK-INTERLEAVED-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-INTERLEAVED-NEXT: [[CMP_1:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
-; CHECK-INTERLEAVED-NEXT: br i1 [[CMP_1]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP17:![0-9]+]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[CMP_1]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP21:![0-9]+]]
; CHECK-INTERLEAVED: [[EXIT]]:
-; CHECK-INTERLEAVED-NEXT: [[RESULT:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP9]], %[[MIDDLE_BLOCK]] ]
+; CHECK-INTERLEAVED-NEXT: [[RESULT:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP15]], %[[MIDDLE_BLOCK]] ]
; CHECK-INTERLEAVED-NEXT: ret float [[RESULT]]
;
; CHECK-MAXBW-LABEL: define float @not_fdotp_ext_outside_plan(
>From cb01d738b3c3660b07ce52f2e1e124a86c8c2e1e Mon Sep 17 00:00:00 2001
From: Damian Heaton <Damian.Heaton at arm.com>
Date: Tue, 2 Dec 2025 16:22:38 +0000
Subject: [PATCH 7/9] Remove stray variable
---
llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index 351a4a2fea5b4..b166b4a4aacff 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -8301,7 +8301,6 @@ VPRecipeBuilder::tryToCreatePartialReduction(VPInstruction *Reduction,
vputils::getVFScaleFactor(Accumulator->getDefiningRecipe()) &&
"all accumulators in chain must have same scale factor");
- unsigned ReductionOpcode = Reduction->getOpcode();
auto *ReductionI = Reduction->getUnderlyingInstr();
if (Reduction->getOpcode() == Instruction::FAdd &&
!ReductionI->hasAllowReassoc())
>From 24d5ffd7e2e8fe9869a0bfa9d96bc8d3e134ec27 Mon Sep 17 00:00:00 2001
From: Damian Heaton <Damian.Heaton at arm.com>
Date: Tue, 9 Dec 2025 12:09:57 +0000
Subject: [PATCH 8/9] Also require allow-contract
---
.../llvm/Analysis/TargetTransformInfo.h | 2 +-
.../llvm/Analysis/TargetTransformInfoImpl.h | 2 +-
llvm/lib/Analysis/TargetTransformInfo.cpp | 4 +-
.../AArch64/AArch64TargetTransformInfo.cpp | 11 +-
.../AArch64/AArch64TargetTransformInfo.h | 4 +-
.../Transforms/Vectorize/LoopVectorize.cpp | 40 +-
.../lib/Transforms/Vectorize/VPlanRecipes.cpp | 14 +-
.../Transforms/Vectorize/VPlanTransforms.cpp | 5 +-
.../AArch64/partial-reduce-fdot-product.ll | 484 ++++++++++++------
9 files changed, 405 insertions(+), 161 deletions(-)
diff --git a/llvm/include/llvm/Analysis/TargetTransformInfo.h b/llvm/include/llvm/Analysis/TargetTransformInfo.h
index 7f4ee11150eb2..1833b02d04c7a 100644
--- a/llvm/include/llvm/Analysis/TargetTransformInfo.h
+++ b/llvm/include/llvm/Analysis/TargetTransformInfo.h
@@ -1425,7 +1425,7 @@ class TargetTransformInfo {
unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType,
ElementCount VF, PartialReductionExtendKind OpAExtend,
PartialReductionExtendKind OpBExtend, std::optional<unsigned> BinOp,
- TTI::TargetCostKind CostKind) const;
+ TTI::TargetCostKind CostKind, std::optional<FastMathFlags> FMF) const;
/// \return The maximum interleave factor that any transform should try to
/// perform for this target. This number depends on the level of parallelism
diff --git a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
index 624302bc6d0a3..5da001eab4420 100644
--- a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
+++ b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
@@ -659,7 +659,7 @@ class TargetTransformInfoImplBase {
unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType,
ElementCount VF, TTI::PartialReductionExtendKind OpAExtend,
TTI::PartialReductionExtendKind OpBExtend, std::optional<unsigned> BinOp,
- TTI::TargetCostKind CostKind) const {
+ TTI::TargetCostKind CostKind, std::optional<FastMathFlags> FMF) const {
return InstructionCost::getInvalid();
}
diff --git a/llvm/lib/Analysis/TargetTransformInfo.cpp b/llvm/lib/Analysis/TargetTransformInfo.cpp
index 497f937b35cbb..5f39f54635b1b 100644
--- a/llvm/lib/Analysis/TargetTransformInfo.cpp
+++ b/llvm/lib/Analysis/TargetTransformInfo.cpp
@@ -880,10 +880,10 @@ InstructionCost TargetTransformInfo::getPartialReductionCost(
unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType,
ElementCount VF, PartialReductionExtendKind OpAExtend,
PartialReductionExtendKind OpBExtend, std::optional<unsigned> BinOp,
- TTI::TargetCostKind CostKind) const {
+ TTI::TargetCostKind CostKind, std::optional<FastMathFlags> FMF) const {
return TTIImpl->getPartialReductionCost(Opcode, InputTypeA, InputTypeB,
AccumType, VF, OpAExtend, OpBExtend,
- BinOp, CostKind);
+ BinOp, CostKind, FMF);
}
unsigned TargetTransformInfo::getMaxInterleaveFactor(ElementCount VF) const {
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
index fd2b608df51a0..079471e96cbb8 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -5788,7 +5788,7 @@ InstructionCost AArch64TTIImpl::getPartialReductionCost(
unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType,
ElementCount VF, TTI::PartialReductionExtendKind OpAExtend,
TTI::PartialReductionExtendKind OpBExtend, std::optional<unsigned> BinOp,
- TTI::TargetCostKind CostKind) const {
+ TTI::TargetCostKind CostKind, std::optional<FastMathFlags> FMF) const {
InstructionCost Invalid = InstructionCost::getInvalid();
if (CostKind != TTI::TCK_RecipThroughput)
@@ -5803,6 +5803,12 @@ InstructionCost AArch64TTIImpl::getPartialReductionCost(
OpAExtend == TTI::PR_None)
return Invalid;
+ // Floating-point partial reductions are invalid if `reassoc` and `contract`
+ // are not allowed.
+ if (Opcode == Instruction::FAdd &&
+ (!FMF->allowReassoc() || !FMF->allowContract()))
+ return Invalid;
+
assert((BinOp || (OpBExtend == TTI::PR_None && !InputTypeB)) &&
(!BinOp || (OpBExtend != TTI::PR_None && InputTypeB)) &&
"Unexpected values for OpBExtend or InputTypeB");
@@ -5822,6 +5828,9 @@ InstructionCost AArch64TTIImpl::getPartialReductionCost(
if (VF.getKnownMinValue() <= Ratio)
return Invalid;
+ if (Opcode == Instruction::FAdd && Ratio <= 1)
+ return Invalid;
+
VectorType *InputVectorType = VectorType::get(InputTypeA, VF);
VectorType *AccumVectorType =
VectorType::get(AccumType, VF.divideCoefficientBy(Ratio));
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
index fe3bb5e7981d2..f984610c618c0 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
@@ -21,6 +21,7 @@
#include "AArch64TargetMachine.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/BasicTTIImpl.h"
+#include "llvm/IR/FMF.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/Support/InstructionCost.h"
@@ -422,7 +423,8 @@ class AArch64TTIImpl final : public BasicTTIImplBase<AArch64TTIImpl> {
unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType,
ElementCount VF, TTI::PartialReductionExtendKind OpAExtend,
TTI::PartialReductionExtendKind OpBExtend, std::optional<unsigned> BinOp,
- TTI::TargetCostKind CostKind) const override;
+ TTI::TargetCostKind CostKind,
+ std::optional<FastMathFlags> FMF) const override;
bool enableOrderedReductions() const override { return true; }
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index b166b4a4aacff..672d1ef58e683 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -6220,7 +6220,33 @@ LoopVectorizationCostModel::getInstructionCost(Instruction *I,
}
[[fallthrough]];
}
- case Instruction::FAdd:
+ case Instruction::FAdd: {
+ // Skip this when falling through from Add/Sub.
+ if (I->getOpcode() == Instruction::FAdd) {
+ Value *Op0 = I->getOperand(0);
+ Value *Op1 = I->getOperand(1);
+ if (Op0 && Op1) {
+ Instruction *Mul = dyn_cast<Instruction>(Op0);
+ if (Mul && Mul->getOpcode() == Instruction::FMul) {
+ Value *MulOp0 = Mul->getOperand(0);
+ Value *MulOp1 = Mul->getOperand(1);
+ if (isa<Instruction>(MulOp0) && isa<Instruction>(MulOp1)) {
+ auto Cost = TTI.getPartialReductionCost(
+ I->getOpcode(), MulOp0->getType(), MulOp1->getType(),
+ VectorTy->getScalarType(), VF,
+ TTI.getPartialReductionExtendKind(
+ dyn_cast<Instruction>(MulOp0)),
+ TTI.getPartialReductionExtendKind(
+ dyn_cast<Instruction>(MulOp1)),
+ Mul->getOpcode(), CostKind, I->getFastMathFlags());
+ if (Cost.isValid())
+ return Cost;
+ }
+ }
+ }
+ }
+ [[fallthrough]];
+ }
case Instruction::FSub:
case Instruction::Mul:
case Instruction::FMul:
@@ -8173,10 +8199,13 @@ bool VPRecipeBuilder::getScaledReductions(
if (LoopVectorizationPlanner::getDecisionAndClampRange(
[&](ElementCount VF) {
+ std::optional<FastMathFlags> FMF = std::nullopt;
+ if (Update->getOpcode() == Instruction::FAdd)
+ FMF = Update->getFastMathFlags();
InstructionCost Cost = TTI->getPartialReductionCost(
Update->getOpcode(), ExtOpTypes[0], ExtOpTypes[1],
PHI->getType(), VF, ExtKinds[0], ExtKinds[1], BinOpc,
- CM.CostKind);
+ CM.CostKind, FMF);
return Cost.isValid();
},
Range)) {
@@ -8303,7 +8332,7 @@ VPRecipeBuilder::tryToCreatePartialReduction(VPInstruction *Reduction,
auto *ReductionI = Reduction->getUnderlyingInstr();
if (Reduction->getOpcode() == Instruction::FAdd &&
- !ReductionI->hasAllowReassoc())
+ (!ReductionI->hasAllowReassoc() || !ReductionI->hasAllowContract()))
return nullptr;
if (Reduction->getOpcode() == Instruction::Sub) {
auto *const Zero = ConstantInt::get(ReductionI->getType(), 0);
@@ -8322,7 +8351,10 @@ VPRecipeBuilder::tryToCreatePartialReduction(VPInstruction *Reduction,
return new VPReductionRecipe(
Reduction->getOpcode() == Instruction::FAdd ? RecurKind::FAdd
: RecurKind::Add,
- FastMathFlags(), ReductionI, Accumulator, BinOp, Cond,
+ Reduction->getOpcode() == Instruction::FAdd
+ ? Reduction->getFastMathFlags()
+ : FastMathFlags(),
+ ReductionI, Accumulator, BinOp, Cond,
RdxUnordered{/*VFScaleFactor=*/ScaleFactor}, ReductionI->getDebugLoc());
}
diff --git a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
index 6e5280af0bfda..fc3a52dc4ac81 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
@@ -2635,7 +2635,8 @@ void VPReductionRecipe::execute(VPTransformState &State) {
PrevInChain->getType(),
Kind == RecurKind::Add ? Intrinsic::vector_partial_reduce_add
: Intrinsic::vector_partial_reduce_fadd,
- {PrevInChain, NewVecOp}, nullptr, "partial.reduce");
+ {PrevInChain, NewVecOp}, State.Builder.getFastMathFlags(),
+ "partial.reduce");
PrevInChain = NewRed;
NextInChain = NewRed;
} else {
@@ -2711,7 +2712,8 @@ InstructionCost VPReductionRecipe::computeCost(ElementCount VF,
auto *InputType = Ctx.Types.inferScalarType(getVecOp());
return CondCost + Ctx.TTI.getPartialReductionCost(
Opcode, InputType, InputType, PhiType, VF,
- TTI::PR_None, TTI::PR_None, {}, Ctx.CostKind);
+ TTI::PR_None, TTI::PR_None, {}, Ctx.CostKind,
+ OptionalFMF);
}
VPRecipeBase *OpR = getVecOp()->getDefiningRecipe();
@@ -2756,7 +2758,8 @@ InstructionCost VPReductionRecipe::computeCost(ElementCount VF,
auto *PhiType = Ctx.Types.inferScalarType(getOperand(1));
return CondCost + Ctx.TTI.getPartialReductionCost(
Opcode, InputTypeA, InputTypeB, PhiType, VF,
- ExtAType, ExtBType, WidenOpcode, Ctx.CostKind);
+ ExtAType, ExtBType, WidenOpcode, Ctx.CostKind,
+ OptionalFMF);
}
}
@@ -2873,7 +2876,8 @@ InstructionCost VPExpressionRecipe::computeCost(ElementCount VF,
RedTy, VF,
TargetTransformInfo::getPartialReductionExtendKind(
ExtR->getOpcode()),
- TargetTransformInfo::PR_None, std::nullopt, Ctx.CostKind)
+ TargetTransformInfo::PR_None, std::nullopt, Ctx.CostKind,
+ std::nullopt)
: Ctx.TTI.getExtendedReductionCost(
Opcode, ExtR->getOpcode() == Instruction::ZExt, RedTy,
SrcVecTy, std::nullopt, Ctx.CostKind);
@@ -2899,7 +2903,7 @@ InstructionCost VPExpressionRecipe::computeCost(ElementCount VF,
Ext0R->getOpcode()),
TargetTransformInfo::getPartialReductionExtendKind(
Ext1R->getOpcode()),
- Mul->getOpcode(), Ctx.CostKind);
+ Mul->getOpcode(), Ctx.CostKind, std::nullopt);
}
return Ctx.TTI.getMulAccReductionCost(
cast<VPWidenCastRecipe>(ExpressionRecipes.front())->getOpcode() ==
diff --git a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
index b12f8ccc73c7e..64891e2cb4ca5 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
@@ -3801,7 +3801,8 @@ tryToMatchAndCreateExtendedReduction(VPReductionRecipe *Red, VPCostContext &Ctx,
// here from LoopVectorize.cpp.
ExtRedCost = Ctx.TTI.getPartialReductionCost(
Opcode, SrcTy, nullptr, RedTy, VF, ExtKind,
- llvm::TargetTransformInfo::PR_None, std::nullopt, Ctx.CostKind);
+ llvm::TargetTransformInfo::PR_None, std::nullopt, Ctx.CostKind,
+ std::nullopt);
} else {
ExtRedCost = Ctx.TTI.getExtendedReductionCost(
Opcode, ExtOpc == Instruction::CastOps::ZExt, RedTy, SrcVecTy,
@@ -3865,7 +3866,7 @@ tryToMatchAndCreateMulAccumulateReduction(VPReductionRecipe *Red,
Ext1 ? TargetTransformInfo::getPartialReductionExtendKind(
Ext1->getOpcode())
: TargetTransformInfo::PR_None,
- Mul->getOpcode(), CostKind);
+ Mul->getOpcode(), CostKind, std::nullopt);
} else {
// Only partial reductions support mixed extends at the moment.
if (Ext0 && Ext1 && Ext0->getOpcode() != Ext1->getOpcode())
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fdot-product.ll b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fdot-product.ll
index 46208a72df219..91a22a2229318 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fdot-product.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fdot-product.ll
@@ -30,12 +30,12 @@ define float @fdotp_f16_f32(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 8 x half>, ptr [[TMP2]], align 1
; CHECK-INTERLEAVE1-NEXT: [[TMP7:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD1]] to <vscale x 8 x float>
; CHECK-INTERLEAVE1-NEXT: [[TMP8:%.*]] = fmul <vscale x 8 x float> [[TMP7]], [[TMP11]]
-; CHECK-INTERLEAVE1-NEXT: [[PARTIAL_REDUCE]] = call <vscale x 4 x float> @llvm.vector.partial.reduce.fadd.nxv4f32.nxv8f32(<vscale x 4 x float> [[VEC_PHI]], <vscale x 8 x float> [[TMP8]])
+; CHECK-INTERLEAVE1-NEXT: [[PARTIAL_REDUCE]] = call reassoc contract <vscale x 4 x float> @llvm.vector.partial.reduce.fadd.nxv4f32.nxv8f32(<vscale x 4 x float> [[VEC_PHI]], <vscale x 8 x float> [[TMP8]])
; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT1]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-INTERLEAVE1-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT1]], [[N_VEC]]
; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK-INTERLEAVE1: [[MIDDLE_BLOCK]]:
-; CHECK-INTERLEAVE1-NEXT: [[TMP10:%.*]] = call reassoc float @llvm.vector.reduce.fadd.nxv4f32(float -0.000000e+00, <vscale x 4 x float> [[PARTIAL_REDUCE]])
+; CHECK-INTERLEAVE1-NEXT: [[TMP10:%.*]] = call reassoc contract float @llvm.vector.reduce.fadd.nxv4f32(float -0.000000e+00, <vscale x 4 x float> [[PARTIAL_REDUCE]])
; CHECK-INTERLEAVE1-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
; CHECK-INTERLEAVE1-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
; CHECK-INTERLEAVE1: [[SCALAR_PH]]:
@@ -52,7 +52,7 @@ define float @fdotp_f16_f32(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
; CHECK-INTERLEAVE1-NEXT: [[EXT_B:%.*]] = fpext half [[LOAD_B]] to float
; CHECK-INTERLEAVE1-NEXT: [[MUL:%.*]] = fmul float [[EXT_B]], [[EXT_A]]
-; CHECK-INTERLEAVE1-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVE1-NEXT: [[ADD]] = fadd reassoc contract float [[MUL]], [[ACCUM]]
; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add i64 [[IV]], 1
; CHECK-INTERLEAVE1-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP5]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
@@ -95,14 +95,14 @@ define float @fdotp_f16_f32(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVED-NEXT: [[TMP15:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD4]] to <vscale x 8 x float>
; CHECK-INTERLEAVED-NEXT: [[TMP16:%.*]] = fmul <vscale x 8 x float> [[TMP14]], [[TMP8]]
; CHECK-INTERLEAVED-NEXT: [[TMP17:%.*]] = fmul <vscale x 8 x float> [[TMP15]], [[TMP9]]
-; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE]] = call <vscale x 4 x float> @llvm.vector.partial.reduce.fadd.nxv4f32.nxv8f32(<vscale x 4 x float> [[VEC_PHI]], <vscale x 8 x float> [[TMP16]])
-; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE5]] = call <vscale x 4 x float> @llvm.vector.partial.reduce.fadd.nxv4f32.nxv8f32(<vscale x 4 x float> [[VEC_PHI1]], <vscale x 8 x float> [[TMP17]])
+; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE]] = call reassoc contract <vscale x 4 x float> @llvm.vector.partial.reduce.fadd.nxv4f32.nxv8f32(<vscale x 4 x float> [[VEC_PHI]], <vscale x 8 x float> [[TMP16]])
+; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE5]] = call reassoc contract <vscale x 4 x float> @llvm.vector.partial.reduce.fadd.nxv4f32.nxv8f32(<vscale x 4 x float> [[VEC_PHI1]], <vscale x 8 x float> [[TMP17]])
; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT1]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-INTERLEAVED-NEXT: [[TMP18:%.*]] = icmp eq i64 [[INDEX_NEXT1]], [[N_VEC]]
; CHECK-INTERLEAVED-NEXT: br i1 [[TMP18]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK-INTERLEAVED: [[MIDDLE_BLOCK]]:
-; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc <vscale x 4 x float> [[PARTIAL_REDUCE5]], [[PARTIAL_REDUCE]]
-; CHECK-INTERLEAVED-NEXT: [[TMP19:%.*]] = call reassoc float @llvm.vector.reduce.fadd.nxv4f32(float -0.000000e+00, <vscale x 4 x float> [[BIN_RDX]])
+; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc contract <vscale x 4 x float> [[PARTIAL_REDUCE5]], [[PARTIAL_REDUCE]]
+; CHECK-INTERLEAVED-NEXT: [[TMP19:%.*]] = call reassoc contract float @llvm.vector.reduce.fadd.nxv4f32(float -0.000000e+00, <vscale x 4 x float> [[BIN_RDX]])
; CHECK-INTERLEAVED-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
; CHECK-INTERLEAVED-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
; CHECK-INTERLEAVED: [[SCALAR_PH]]:
@@ -119,7 +119,7 @@ define float @fdotp_f16_f32(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVED-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
; CHECK-INTERLEAVED-NEXT: [[EXT_B:%.*]] = fpext half [[LOAD_B]] to float
; CHECK-INTERLEAVED-NEXT: [[MUL:%.*]] = fmul float [[EXT_B]], [[EXT_A]]
-; CHECK-INTERLEAVED-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVED-NEXT: [[ADD]] = fadd reassoc contract float [[MUL]], [[ACCUM]]
; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add i64 [[IV]], 1
; CHECK-INTERLEAVED-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
; CHECK-INTERLEAVED-NEXT: br i1 [[TMP12]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
@@ -150,12 +150,12 @@ define float @fdotp_f16_f32(ptr %a, ptr %b) #0 {
; CHECK-MAXBW-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 8 x half>, ptr [[TMP6]], align 1
; CHECK-MAXBW-NEXT: [[TMP7:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD1]] to <vscale x 8 x float>
; CHECK-MAXBW-NEXT: [[TMP8:%.*]] = fmul <vscale x 8 x float> [[TMP7]], [[TMP5]]
-; CHECK-MAXBW-NEXT: [[PARTIAL_REDUCE]] = call <vscale x 4 x float> @llvm.vector.partial.reduce.fadd.nxv4f32.nxv8f32(<vscale x 4 x float> [[VEC_PHI]], <vscale x 8 x float> [[TMP8]])
+; CHECK-MAXBW-NEXT: [[PARTIAL_REDUCE]] = call reassoc contract <vscale x 4 x float> @llvm.vector.partial.reduce.fadd.nxv4f32.nxv8f32(<vscale x 4 x float> [[VEC_PHI]], <vscale x 8 x float> [[TMP8]])
; CHECK-MAXBW-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-MAXBW-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-MAXBW-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK-MAXBW: [[MIDDLE_BLOCK]]:
-; CHECK-MAXBW-NEXT: [[TMP10:%.*]] = call reassoc float @llvm.vector.reduce.fadd.nxv4f32(float -0.000000e+00, <vscale x 4 x float> [[PARTIAL_REDUCE]])
+; CHECK-MAXBW-NEXT: [[TMP10:%.*]] = call reassoc contract float @llvm.vector.reduce.fadd.nxv4f32(float -0.000000e+00, <vscale x 4 x float> [[PARTIAL_REDUCE]])
; CHECK-MAXBW-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
; CHECK-MAXBW-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
; CHECK-MAXBW: [[SCALAR_PH]]:
@@ -172,7 +172,7 @@ define float @fdotp_f16_f32(ptr %a, ptr %b) #0 {
; CHECK-MAXBW-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
; CHECK-MAXBW-NEXT: [[EXT_B:%.*]] = fpext half [[LOAD_B]] to float
; CHECK-MAXBW-NEXT: [[MUL:%.*]] = fmul float [[EXT_B]], [[EXT_A]]
-; CHECK-MAXBW-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[ACCUM]]
+; CHECK-MAXBW-NEXT: [[ADD]] = fadd reassoc contract float [[MUL]], [[ACCUM]]
; CHECK-MAXBW-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
; CHECK-MAXBW-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
; CHECK-MAXBW-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
@@ -218,7 +218,7 @@ for.body: ; preds = %for.body, %entry
%load.b = load half, ptr %gep.b, align 1
%ext.b = fpext half %load.b to float
%mul = fmul float %ext.b, %ext.a
- %add = fadd reassoc float %mul, %accum
+ %add = fadd reassoc contract float %mul, %accum
%iv.next = add i64 %iv, 1
%exitcond.not = icmp eq i64 %iv.next, 1024
br i1 %exitcond.not, label %for.exit, label %for.body
@@ -251,12 +251,12 @@ define double @fdotp_f16_f64(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 8 x half>, ptr [[TMP2]], align 1
; CHECK-INTERLEAVE1-NEXT: [[TMP7:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD1]] to <vscale x 8 x double>
; CHECK-INTERLEAVE1-NEXT: [[TMP8:%.*]] = fmul <vscale x 8 x double> [[TMP7]], [[TMP12]]
-; CHECK-INTERLEAVE1-NEXT: [[PARTIAL_REDUCE]] = call <vscale x 2 x double> @llvm.vector.partial.reduce.fadd.nxv2f64.nxv8f64(<vscale x 2 x double> [[VEC_PHI]], <vscale x 8 x double> [[TMP8]])
+; CHECK-INTERLEAVE1-NEXT: [[PARTIAL_REDUCE]] = call reassoc contract <vscale x 2 x double> @llvm.vector.partial.reduce.fadd.nxv2f64.nxv8f64(<vscale x 2 x double> [[VEC_PHI]], <vscale x 8 x double> [[TMP8]])
; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT1]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-INTERLEAVE1-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT1]], [[N_VEC]]
; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
; CHECK-INTERLEAVE1: [[MIDDLE_BLOCK]]:
-; CHECK-INTERLEAVE1-NEXT: [[TMP10:%.*]] = call reassoc double @llvm.vector.reduce.fadd.nxv2f64(double -0.000000e+00, <vscale x 2 x double> [[PARTIAL_REDUCE]])
+; CHECK-INTERLEAVE1-NEXT: [[TMP10:%.*]] = call reassoc contract double @llvm.vector.reduce.fadd.nxv2f64(double -0.000000e+00, <vscale x 2 x double> [[PARTIAL_REDUCE]])
; CHECK-INTERLEAVE1-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
; CHECK-INTERLEAVE1-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
; CHECK-INTERLEAVE1: [[SCALAR_PH]]:
@@ -273,7 +273,7 @@ define double @fdotp_f16_f64(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
; CHECK-INTERLEAVE1-NEXT: [[EXT_B:%.*]] = fpext half [[LOAD_B]] to double
; CHECK-INTERLEAVE1-NEXT: [[MUL:%.*]] = fmul double [[EXT_B]], [[EXT_A]]
-; CHECK-INTERLEAVE1-NEXT: [[ADD]] = fadd reassoc double [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVE1-NEXT: [[ADD]] = fadd reassoc contract double [[MUL]], [[ACCUM]]
; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add i64 [[IV]], 1
; CHECK-INTERLEAVE1-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP5]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
@@ -316,14 +316,14 @@ define double @fdotp_f16_f64(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVED-NEXT: [[TMP15:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD4]] to <vscale x 8 x double>
; CHECK-INTERLEAVED-NEXT: [[TMP16:%.*]] = fmul <vscale x 8 x double> [[TMP14]], [[TMP8]]
; CHECK-INTERLEAVED-NEXT: [[TMP17:%.*]] = fmul <vscale x 8 x double> [[TMP15]], [[TMP9]]
-; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE]] = call <vscale x 2 x double> @llvm.vector.partial.reduce.fadd.nxv2f64.nxv8f64(<vscale x 2 x double> [[VEC_PHI]], <vscale x 8 x double> [[TMP16]])
-; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE5]] = call <vscale x 2 x double> @llvm.vector.partial.reduce.fadd.nxv2f64.nxv8f64(<vscale x 2 x double> [[VEC_PHI1]], <vscale x 8 x double> [[TMP17]])
+; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE]] = call reassoc contract <vscale x 2 x double> @llvm.vector.partial.reduce.fadd.nxv2f64.nxv8f64(<vscale x 2 x double> [[VEC_PHI]], <vscale x 8 x double> [[TMP16]])
+; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE5]] = call reassoc contract <vscale x 2 x double> @llvm.vector.partial.reduce.fadd.nxv2f64.nxv8f64(<vscale x 2 x double> [[VEC_PHI1]], <vscale x 8 x double> [[TMP17]])
; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT1]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-INTERLEAVED-NEXT: [[TMP18:%.*]] = icmp eq i64 [[INDEX_NEXT1]], [[N_VEC]]
; CHECK-INTERLEAVED-NEXT: br i1 [[TMP18]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
; CHECK-INTERLEAVED: [[MIDDLE_BLOCK]]:
-; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc <vscale x 2 x double> [[PARTIAL_REDUCE5]], [[PARTIAL_REDUCE]]
-; CHECK-INTERLEAVED-NEXT: [[TMP19:%.*]] = call reassoc double @llvm.vector.reduce.fadd.nxv2f64(double -0.000000e+00, <vscale x 2 x double> [[BIN_RDX]])
+; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc contract <vscale x 2 x double> [[PARTIAL_REDUCE5]], [[PARTIAL_REDUCE]]
+; CHECK-INTERLEAVED-NEXT: [[TMP19:%.*]] = call reassoc contract double @llvm.vector.reduce.fadd.nxv2f64(double -0.000000e+00, <vscale x 2 x double> [[BIN_RDX]])
; CHECK-INTERLEAVED-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
; CHECK-INTERLEAVED-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
; CHECK-INTERLEAVED: [[SCALAR_PH]]:
@@ -340,7 +340,7 @@ define double @fdotp_f16_f64(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVED-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
; CHECK-INTERLEAVED-NEXT: [[EXT_B:%.*]] = fpext half [[LOAD_B]] to double
; CHECK-INTERLEAVED-NEXT: [[MUL:%.*]] = fmul double [[EXT_B]], [[EXT_A]]
-; CHECK-INTERLEAVED-NEXT: [[ADD]] = fadd reassoc double [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVED-NEXT: [[ADD]] = fadd reassoc contract double [[MUL]], [[ACCUM]]
; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add i64 [[IV]], 1
; CHECK-INTERLEAVED-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
; CHECK-INTERLEAVED-NEXT: br i1 [[TMP10]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
@@ -371,12 +371,12 @@ define double @fdotp_f16_f64(ptr %a, ptr %b) #0 {
; CHECK-MAXBW-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 8 x half>, ptr [[TMP6]], align 1
; CHECK-MAXBW-NEXT: [[TMP7:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD1]] to <vscale x 8 x double>
; CHECK-MAXBW-NEXT: [[TMP8:%.*]] = fmul <vscale x 8 x double> [[TMP7]], [[TMP5]]
-; CHECK-MAXBW-NEXT: [[PARTIAL_REDUCE]] = call <vscale x 2 x double> @llvm.vector.partial.reduce.fadd.nxv2f64.nxv8f64(<vscale x 2 x double> [[VEC_PHI]], <vscale x 8 x double> [[TMP8]])
+; CHECK-MAXBW-NEXT: [[PARTIAL_REDUCE]] = call reassoc contract <vscale x 2 x double> @llvm.vector.partial.reduce.fadd.nxv2f64.nxv8f64(<vscale x 2 x double> [[VEC_PHI]], <vscale x 8 x double> [[TMP8]])
; CHECK-MAXBW-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-MAXBW-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-MAXBW-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
; CHECK-MAXBW: [[MIDDLE_BLOCK]]:
-; CHECK-MAXBW-NEXT: [[TMP10:%.*]] = call reassoc double @llvm.vector.reduce.fadd.nxv2f64(double -0.000000e+00, <vscale x 2 x double> [[PARTIAL_REDUCE]])
+; CHECK-MAXBW-NEXT: [[TMP10:%.*]] = call reassoc contract double @llvm.vector.reduce.fadd.nxv2f64(double -0.000000e+00, <vscale x 2 x double> [[PARTIAL_REDUCE]])
; CHECK-MAXBW-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
; CHECK-MAXBW-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
; CHECK-MAXBW: [[SCALAR_PH]]:
@@ -393,7 +393,7 @@ define double @fdotp_f16_f64(ptr %a, ptr %b) #0 {
; CHECK-MAXBW-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
; CHECK-MAXBW-NEXT: [[EXT_B:%.*]] = fpext half [[LOAD_B]] to double
; CHECK-MAXBW-NEXT: [[MUL:%.*]] = fmul double [[EXT_B]], [[EXT_A]]
-; CHECK-MAXBW-NEXT: [[ADD]] = fadd reassoc double [[MUL]], [[ACCUM]]
+; CHECK-MAXBW-NEXT: [[ADD]] = fadd reassoc contract double [[MUL]], [[ACCUM]]
; CHECK-MAXBW-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
; CHECK-MAXBW-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
; CHECK-MAXBW-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
@@ -439,7 +439,7 @@ for.body: ; preds = %for.body, %entry
%load.b = load half, ptr %gep.b, align 1
%ext.b = fpext half %load.b to double
%mul = fmul double %ext.b, %ext.a
- %add = fadd reassoc double %mul, %accum
+ %add = fadd reassoc contract double %mul, %accum
%iv.next = add i64 %iv, 1
%exitcond.not = icmp eq i64 %iv.next, 1024
br i1 %exitcond.not, label %for.exit, label %for.body
@@ -472,12 +472,12 @@ define double @fdotp_f32_f64(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 4 x float>, ptr [[TMP2]], align 1
; CHECK-INTERLEAVE1-NEXT: [[TMP7:%.*]] = fpext <vscale x 4 x float> [[WIDE_LOAD1]] to <vscale x 4 x double>
; CHECK-INTERLEAVE1-NEXT: [[TMP8:%.*]] = fmul <vscale x 4 x double> [[TMP7]], [[TMP12]]
-; CHECK-INTERLEAVE1-NEXT: [[PARTIAL_REDUCE]] = call <vscale x 2 x double> @llvm.vector.partial.reduce.fadd.nxv2f64.nxv4f64(<vscale x 2 x double> [[VEC_PHI]], <vscale x 4 x double> [[TMP8]])
+; CHECK-INTERLEAVE1-NEXT: [[PARTIAL_REDUCE]] = call reassoc contract <vscale x 2 x double> @llvm.vector.partial.reduce.fadd.nxv2f64.nxv4f64(<vscale x 2 x double> [[VEC_PHI]], <vscale x 4 x double> [[TMP8]])
; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT1]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-INTERLEAVE1-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT1]], [[N_VEC]]
; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
; CHECK-INTERLEAVE1: [[MIDDLE_BLOCK]]:
-; CHECK-INTERLEAVE1-NEXT: [[TMP10:%.*]] = call reassoc double @llvm.vector.reduce.fadd.nxv2f64(double -0.000000e+00, <vscale x 2 x double> [[PARTIAL_REDUCE]])
+; CHECK-INTERLEAVE1-NEXT: [[TMP10:%.*]] = call reassoc contract double @llvm.vector.reduce.fadd.nxv2f64(double -0.000000e+00, <vscale x 2 x double> [[PARTIAL_REDUCE]])
; CHECK-INTERLEAVE1-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
; CHECK-INTERLEAVE1-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
; CHECK-INTERLEAVE1: [[SCALAR_PH]]:
@@ -494,7 +494,7 @@ define double @fdotp_f32_f64(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-NEXT: [[LOAD_B:%.*]] = load float, ptr [[GEP_B]], align 1
; CHECK-INTERLEAVE1-NEXT: [[EXT_B:%.*]] = fpext float [[LOAD_B]] to double
; CHECK-INTERLEAVE1-NEXT: [[MUL:%.*]] = fmul double [[EXT_B]], [[EXT_A]]
-; CHECK-INTERLEAVE1-NEXT: [[ADD]] = fadd reassoc double [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVE1-NEXT: [[ADD]] = fadd reassoc contract double [[MUL]], [[ACCUM]]
; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add i64 [[IV]], 1
; CHECK-INTERLEAVE1-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP5]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
@@ -537,14 +537,14 @@ define double @fdotp_f32_f64(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVED-NEXT: [[TMP15:%.*]] = fpext <vscale x 4 x float> [[WIDE_LOAD4]] to <vscale x 4 x double>
; CHECK-INTERLEAVED-NEXT: [[TMP16:%.*]] = fmul <vscale x 4 x double> [[TMP14]], [[TMP8]]
; CHECK-INTERLEAVED-NEXT: [[TMP17:%.*]] = fmul <vscale x 4 x double> [[TMP15]], [[TMP9]]
-; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE]] = call <vscale x 2 x double> @llvm.vector.partial.reduce.fadd.nxv2f64.nxv4f64(<vscale x 2 x double> [[VEC_PHI]], <vscale x 4 x double> [[TMP16]])
-; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE5]] = call <vscale x 2 x double> @llvm.vector.partial.reduce.fadd.nxv2f64.nxv4f64(<vscale x 2 x double> [[VEC_PHI1]], <vscale x 4 x double> [[TMP17]])
+; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE]] = call reassoc contract <vscale x 2 x double> @llvm.vector.partial.reduce.fadd.nxv2f64.nxv4f64(<vscale x 2 x double> [[VEC_PHI]], <vscale x 4 x double> [[TMP16]])
+; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE5]] = call reassoc contract <vscale x 2 x double> @llvm.vector.partial.reduce.fadd.nxv2f64.nxv4f64(<vscale x 2 x double> [[VEC_PHI1]], <vscale x 4 x double> [[TMP17]])
; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT1]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-INTERLEAVED-NEXT: [[TMP18:%.*]] = icmp eq i64 [[INDEX_NEXT1]], [[N_VEC]]
; CHECK-INTERLEAVED-NEXT: br i1 [[TMP18]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
; CHECK-INTERLEAVED: [[MIDDLE_BLOCK]]:
-; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc <vscale x 2 x double> [[PARTIAL_REDUCE5]], [[PARTIAL_REDUCE]]
-; CHECK-INTERLEAVED-NEXT: [[TMP19:%.*]] = call reassoc double @llvm.vector.reduce.fadd.nxv2f64(double -0.000000e+00, <vscale x 2 x double> [[BIN_RDX]])
+; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc contract <vscale x 2 x double> [[PARTIAL_REDUCE5]], [[PARTIAL_REDUCE]]
+; CHECK-INTERLEAVED-NEXT: [[TMP19:%.*]] = call reassoc contract double @llvm.vector.reduce.fadd.nxv2f64(double -0.000000e+00, <vscale x 2 x double> [[BIN_RDX]])
; CHECK-INTERLEAVED-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
; CHECK-INTERLEAVED-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
; CHECK-INTERLEAVED: [[SCALAR_PH]]:
@@ -561,7 +561,7 @@ define double @fdotp_f32_f64(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVED-NEXT: [[LOAD_B:%.*]] = load float, ptr [[GEP_B]], align 1
; CHECK-INTERLEAVED-NEXT: [[EXT_B:%.*]] = fpext float [[LOAD_B]] to double
; CHECK-INTERLEAVED-NEXT: [[MUL:%.*]] = fmul double [[EXT_B]], [[EXT_A]]
-; CHECK-INTERLEAVED-NEXT: [[ADD]] = fadd reassoc double [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVED-NEXT: [[ADD]] = fadd reassoc contract double [[MUL]], [[ACCUM]]
; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add i64 [[IV]], 1
; CHECK-INTERLEAVED-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
; CHECK-INTERLEAVED-NEXT: br i1 [[TMP10]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
@@ -592,12 +592,12 @@ define double @fdotp_f32_f64(ptr %a, ptr %b) #0 {
; CHECK-MAXBW-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 4 x float>, ptr [[TMP6]], align 1
; CHECK-MAXBW-NEXT: [[TMP7:%.*]] = fpext <vscale x 4 x float> [[WIDE_LOAD1]] to <vscale x 4 x double>
; CHECK-MAXBW-NEXT: [[TMP8:%.*]] = fmul <vscale x 4 x double> [[TMP7]], [[TMP5]]
-; CHECK-MAXBW-NEXT: [[PARTIAL_REDUCE]] = call <vscale x 2 x double> @llvm.vector.partial.reduce.fadd.nxv2f64.nxv4f64(<vscale x 2 x double> [[VEC_PHI]], <vscale x 4 x double> [[TMP8]])
+; CHECK-MAXBW-NEXT: [[PARTIAL_REDUCE]] = call reassoc contract <vscale x 2 x double> @llvm.vector.partial.reduce.fadd.nxv2f64.nxv4f64(<vscale x 2 x double> [[VEC_PHI]], <vscale x 4 x double> [[TMP8]])
; CHECK-MAXBW-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-MAXBW-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-MAXBW-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
; CHECK-MAXBW: [[MIDDLE_BLOCK]]:
-; CHECK-MAXBW-NEXT: [[TMP10:%.*]] = call reassoc double @llvm.vector.reduce.fadd.nxv2f64(double -0.000000e+00, <vscale x 2 x double> [[PARTIAL_REDUCE]])
+; CHECK-MAXBW-NEXT: [[TMP10:%.*]] = call reassoc contract double @llvm.vector.reduce.fadd.nxv2f64(double -0.000000e+00, <vscale x 2 x double> [[PARTIAL_REDUCE]])
; CHECK-MAXBW-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
; CHECK-MAXBW-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
; CHECK-MAXBW: [[SCALAR_PH]]:
@@ -614,7 +614,7 @@ define double @fdotp_f32_f64(ptr %a, ptr %b) #0 {
; CHECK-MAXBW-NEXT: [[LOAD_B:%.*]] = load float, ptr [[GEP_B]], align 1
; CHECK-MAXBW-NEXT: [[EXT_B:%.*]] = fpext float [[LOAD_B]] to double
; CHECK-MAXBW-NEXT: [[MUL:%.*]] = fmul double [[EXT_B]], [[EXT_A]]
-; CHECK-MAXBW-NEXT: [[ADD]] = fadd reassoc double [[MUL]], [[ACCUM]]
+; CHECK-MAXBW-NEXT: [[ADD]] = fadd reassoc contract double [[MUL]], [[ACCUM]]
; CHECK-MAXBW-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
; CHECK-MAXBW-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
; CHECK-MAXBW-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
@@ -660,7 +660,7 @@ for.body: ; preds = %for.body, %entry
%load.b = load float, ptr %gep.b, align 1
%ext.b = fpext float %load.b to double
%mul = fmul double %ext.b, %ext.a
- %add = fadd reassoc double %mul, %accum
+ %add = fadd reassoc contract double %mul, %accum
%iv.next = add i64 %iv, 1
%exitcond.not = icmp eq i64 %iv.next, 1024
br i1 %exitcond.not, label %for.exit, label %for.body
@@ -691,12 +691,12 @@ define half @fdotp_noext_f16(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-NEXT: [[TMP5:%.*]] = getelementptr half, ptr [[B]], i64 [[INDEX]]
; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 8 x half>, ptr [[TMP5]], align 1
; CHECK-INTERLEAVE1-NEXT: [[TMP6:%.*]] = fmul <vscale x 8 x half> [[WIDE_LOAD1]], [[WIDE_LOAD]]
-; CHECK-INTERLEAVE1-NEXT: [[TMP7]] = fadd reassoc <vscale x 8 x half> [[TMP6]], [[VEC_PHI]]
+; CHECK-INTERLEAVE1-NEXT: [[TMP7]] = fadd reassoc contract <vscale x 8 x half> [[TMP6]], [[VEC_PHI]]
; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-INTERLEAVE1-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
; CHECK-INTERLEAVE1: [[MIDDLE_BLOCK]]:
-; CHECK-INTERLEAVE1-NEXT: [[TMP9:%.*]] = call reassoc half @llvm.vector.reduce.fadd.nxv8f16(half 0xH8000, <vscale x 8 x half> [[TMP7]])
+; CHECK-INTERLEAVE1-NEXT: [[TMP9:%.*]] = call reassoc contract half @llvm.vector.reduce.fadd.nxv8f16(half 0xH8000, <vscale x 8 x half> [[TMP7]])
; CHECK-INTERLEAVE1-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
; CHECK-INTERLEAVE1-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
; CHECK-INTERLEAVE1: [[SCALAR_PH]]:
@@ -711,7 +711,7 @@ define half @fdotp_noext_f16(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-NEXT: [[GEP_B:%.*]] = getelementptr half, ptr [[B]], i64 [[IV]]
; CHECK-INTERLEAVE1-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
; CHECK-INTERLEAVE1-NEXT: [[MUL:%.*]] = fmul half [[LOAD_B]], [[LOAD_A]]
-; CHECK-INTERLEAVE1-NEXT: [[ADD]] = fadd reassoc half [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVE1-NEXT: [[ADD]] = fadd reassoc contract half [[MUL]], [[ACCUM]]
; CHECK-INTERLEAVE1-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
; CHECK-INTERLEAVE1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
; CHECK-INTERLEAVE1-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]]
@@ -750,14 +750,14 @@ define half @fdotp_noext_f16(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD4:%.*]] = load <vscale x 8 x half>, ptr [[TMP11]], align 1
; CHECK-INTERLEAVED-NEXT: [[TMP12:%.*]] = fmul <vscale x 8 x half> [[WIDE_LOAD3]], [[WIDE_LOAD]]
; CHECK-INTERLEAVED-NEXT: [[TMP13:%.*]] = fmul <vscale x 8 x half> [[WIDE_LOAD4]], [[WIDE_LOAD2]]
-; CHECK-INTERLEAVED-NEXT: [[TMP14]] = fadd reassoc <vscale x 8 x half> [[TMP12]], [[VEC_PHI]]
-; CHECK-INTERLEAVED-NEXT: [[TMP15]] = fadd reassoc <vscale x 8 x half> [[TMP13]], [[VEC_PHI1]]
+; CHECK-INTERLEAVED-NEXT: [[TMP14]] = fadd reassoc contract <vscale x 8 x half> [[TMP12]], [[VEC_PHI]]
+; CHECK-INTERLEAVED-NEXT: [[TMP15]] = fadd reassoc contract <vscale x 8 x half> [[TMP13]], [[VEC_PHI1]]
; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-INTERLEAVED-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-INTERLEAVED-NEXT: br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
; CHECK-INTERLEAVED: [[MIDDLE_BLOCK]]:
-; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc <vscale x 8 x half> [[TMP15]], [[TMP14]]
-; CHECK-INTERLEAVED-NEXT: [[TMP17:%.*]] = call reassoc half @llvm.vector.reduce.fadd.nxv8f16(half 0xH8000, <vscale x 8 x half> [[BIN_RDX]])
+; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc contract <vscale x 8 x half> [[TMP15]], [[TMP14]]
+; CHECK-INTERLEAVED-NEXT: [[TMP17:%.*]] = call reassoc contract half @llvm.vector.reduce.fadd.nxv8f16(half 0xH8000, <vscale x 8 x half> [[BIN_RDX]])
; CHECK-INTERLEAVED-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
; CHECK-INTERLEAVED-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
; CHECK-INTERLEAVED: [[SCALAR_PH]]:
@@ -772,7 +772,7 @@ define half @fdotp_noext_f16(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVED-NEXT: [[GEP_B:%.*]] = getelementptr half, ptr [[B]], i64 [[IV]]
; CHECK-INTERLEAVED-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
; CHECK-INTERLEAVED-NEXT: [[MUL:%.*]] = fmul half [[LOAD_B]], [[LOAD_A]]
-; CHECK-INTERLEAVED-NEXT: [[ADD]] = fadd reassoc half [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVED-NEXT: [[ADD]] = fadd reassoc contract half [[MUL]], [[ACCUM]]
; CHECK-INTERLEAVED-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
; CHECK-INTERLEAVED-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
; CHECK-INTERLEAVED-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]]
@@ -801,12 +801,12 @@ define half @fdotp_noext_f16(ptr %a, ptr %b) #0 {
; CHECK-MAXBW-NEXT: [[TMP5:%.*]] = getelementptr half, ptr [[B]], i64 [[INDEX]]
; CHECK-MAXBW-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 8 x half>, ptr [[TMP5]], align 1
; CHECK-MAXBW-NEXT: [[TMP6:%.*]] = fmul <vscale x 8 x half> [[WIDE_LOAD1]], [[WIDE_LOAD]]
-; CHECK-MAXBW-NEXT: [[TMP7]] = fadd reassoc <vscale x 8 x half> [[TMP6]], [[VEC_PHI]]
+; CHECK-MAXBW-NEXT: [[TMP7]] = fadd reassoc contract <vscale x 8 x half> [[TMP6]], [[VEC_PHI]]
; CHECK-MAXBW-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-MAXBW-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-MAXBW-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
; CHECK-MAXBW: [[MIDDLE_BLOCK]]:
-; CHECK-MAXBW-NEXT: [[TMP9:%.*]] = call reassoc half @llvm.vector.reduce.fadd.nxv8f16(half 0xH8000, <vscale x 8 x half> [[TMP7]])
+; CHECK-MAXBW-NEXT: [[TMP9:%.*]] = call reassoc contract half @llvm.vector.reduce.fadd.nxv8f16(half 0xH8000, <vscale x 8 x half> [[TMP7]])
; CHECK-MAXBW-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
; CHECK-MAXBW-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
; CHECK-MAXBW: [[SCALAR_PH]]:
@@ -821,7 +821,7 @@ define half @fdotp_noext_f16(ptr %a, ptr %b) #0 {
; CHECK-MAXBW-NEXT: [[GEP_B:%.*]] = getelementptr half, ptr [[B]], i64 [[IV]]
; CHECK-MAXBW-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
; CHECK-MAXBW-NEXT: [[MUL:%.*]] = fmul half [[LOAD_B]], [[LOAD_A]]
-; CHECK-MAXBW-NEXT: [[ADD]] = fadd reassoc half [[MUL]], [[ACCUM]]
+; CHECK-MAXBW-NEXT: [[ADD]] = fadd reassoc contract half [[MUL]], [[ACCUM]]
; CHECK-MAXBW-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
; CHECK-MAXBW-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
; CHECK-MAXBW-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]]
@@ -850,7 +850,7 @@ define half @fdotp_noext_f16(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP5:%.*]] = getelementptr half, ptr [[B]], i64 [[INDEX]]
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 8 x half>, ptr [[TMP5]], align 1
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP6:%.*]] = fmul <vscale x 8 x half> [[WIDE_LOAD1]], [[WIDE_LOAD]]
-; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP7]] = fadd reassoc <vscale x 8 x half> [[TMP6]], [[VEC_PHI]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP7]] = fadd reassoc contract <vscale x 8 x half> [[TMP6]], [[VEC_PHI]]
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-INTERLEAVE1-SVE2P1-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
@@ -870,7 +870,7 @@ define half @fdotp_noext_f16(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[GEP_B:%.*]] = getelementptr half, ptr [[B]], i64 [[IV]]
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[MUL:%.*]] = fmul half [[LOAD_B]], [[LOAD_A]]
-; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ADD]] = fadd reassoc half [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ADD]] = fadd reassoc contract half [[MUL]], [[ACCUM]]
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
; CHECK-INTERLEAVE1-SVE2P1-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
@@ -888,7 +888,7 @@ for.body: ; preds = %for.body, %entry
%gep.b = getelementptr half, ptr %b, i64 %iv
%load.b = load half, ptr %gep.b, align 1
%mul = fmul half %load.b, %load.a
- %add = fadd reassoc half %mul, %accum
+ %add = fadd reassoc contract half %mul, %accum
%iv.next = add i64 %iv, 1
%exitcond.not = icmp eq i64 %iv.next, 1024
br i1 %exitcond.not, label %for.exit, label %for.body
@@ -919,12 +919,12 @@ define float @fdotp_noext_f32(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-NEXT: [[TMP5:%.*]] = getelementptr float, ptr [[B]], i64 [[INDEX]]
; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 4 x float>, ptr [[TMP5]], align 1
; CHECK-INTERLEAVE1-NEXT: [[TMP6:%.*]] = fmul <vscale x 4 x float> [[WIDE_LOAD1]], [[WIDE_LOAD]]
-; CHECK-INTERLEAVE1-NEXT: [[TMP7]] = fadd reassoc <vscale x 4 x float> [[TMP6]], [[VEC_PHI]]
+; CHECK-INTERLEAVE1-NEXT: [[TMP7]] = fadd reassoc contract <vscale x 4 x float> [[TMP6]], [[VEC_PHI]]
; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-INTERLEAVE1-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]
; CHECK-INTERLEAVE1: [[MIDDLE_BLOCK]]:
-; CHECK-INTERLEAVE1-NEXT: [[TMP9:%.*]] = call reassoc float @llvm.vector.reduce.fadd.nxv4f32(float -0.000000e+00, <vscale x 4 x float> [[TMP7]])
+; CHECK-INTERLEAVE1-NEXT: [[TMP9:%.*]] = call reassoc contract float @llvm.vector.reduce.fadd.nxv4f32(float -0.000000e+00, <vscale x 4 x float> [[TMP7]])
; CHECK-INTERLEAVE1-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
; CHECK-INTERLEAVE1-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
; CHECK-INTERLEAVE1: [[SCALAR_PH]]:
@@ -939,7 +939,7 @@ define float @fdotp_noext_f32(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-NEXT: [[GEP_B:%.*]] = getelementptr float, ptr [[B]], i64 [[IV]]
; CHECK-INTERLEAVE1-NEXT: [[LOAD_B:%.*]] = load float, ptr [[GEP_B]], align 1
; CHECK-INTERLEAVE1-NEXT: [[MUL:%.*]] = fmul float [[LOAD_B]], [[LOAD_A]]
-; CHECK-INTERLEAVE1-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVE1-NEXT: [[ADD]] = fadd reassoc contract float [[MUL]], [[ACCUM]]
; CHECK-INTERLEAVE1-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
; CHECK-INTERLEAVE1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
; CHECK-INTERLEAVE1-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]]
@@ -978,14 +978,14 @@ define float @fdotp_noext_f32(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD4:%.*]] = load <vscale x 4 x float>, ptr [[TMP11]], align 1
; CHECK-INTERLEAVED-NEXT: [[TMP12:%.*]] = fmul <vscale x 4 x float> [[WIDE_LOAD3]], [[WIDE_LOAD]]
; CHECK-INTERLEAVED-NEXT: [[TMP13:%.*]] = fmul <vscale x 4 x float> [[WIDE_LOAD4]], [[WIDE_LOAD2]]
-; CHECK-INTERLEAVED-NEXT: [[TMP14]] = fadd reassoc <vscale x 4 x float> [[TMP12]], [[VEC_PHI]]
-; CHECK-INTERLEAVED-NEXT: [[TMP15]] = fadd reassoc <vscale x 4 x float> [[TMP13]], [[VEC_PHI1]]
+; CHECK-INTERLEAVED-NEXT: [[TMP14]] = fadd reassoc contract <vscale x 4 x float> [[TMP12]], [[VEC_PHI]]
+; CHECK-INTERLEAVED-NEXT: [[TMP15]] = fadd reassoc contract <vscale x 4 x float> [[TMP13]], [[VEC_PHI1]]
; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-INTERLEAVED-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-INTERLEAVED-NEXT: br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]
; CHECK-INTERLEAVED: [[MIDDLE_BLOCK]]:
-; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc <vscale x 4 x float> [[TMP15]], [[TMP14]]
-; CHECK-INTERLEAVED-NEXT: [[TMP17:%.*]] = call reassoc float @llvm.vector.reduce.fadd.nxv4f32(float -0.000000e+00, <vscale x 4 x float> [[BIN_RDX]])
+; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc contract <vscale x 4 x float> [[TMP15]], [[TMP14]]
+; CHECK-INTERLEAVED-NEXT: [[TMP17:%.*]] = call reassoc contract float @llvm.vector.reduce.fadd.nxv4f32(float -0.000000e+00, <vscale x 4 x float> [[BIN_RDX]])
; CHECK-INTERLEAVED-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
; CHECK-INTERLEAVED-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
; CHECK-INTERLEAVED: [[SCALAR_PH]]:
@@ -1000,7 +1000,7 @@ define float @fdotp_noext_f32(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVED-NEXT: [[GEP_B:%.*]] = getelementptr float, ptr [[B]], i64 [[IV]]
; CHECK-INTERLEAVED-NEXT: [[LOAD_B:%.*]] = load float, ptr [[GEP_B]], align 1
; CHECK-INTERLEAVED-NEXT: [[MUL:%.*]] = fmul float [[LOAD_B]], [[LOAD_A]]
-; CHECK-INTERLEAVED-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVED-NEXT: [[ADD]] = fadd reassoc contract float [[MUL]], [[ACCUM]]
; CHECK-INTERLEAVED-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
; CHECK-INTERLEAVED-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
; CHECK-INTERLEAVED-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]]
@@ -1029,12 +1029,12 @@ define float @fdotp_noext_f32(ptr %a, ptr %b) #0 {
; CHECK-MAXBW-NEXT: [[TMP5:%.*]] = getelementptr float, ptr [[B]], i64 [[INDEX]]
; CHECK-MAXBW-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 4 x float>, ptr [[TMP5]], align 1
; CHECK-MAXBW-NEXT: [[TMP6:%.*]] = fmul <vscale x 4 x float> [[WIDE_LOAD1]], [[WIDE_LOAD]]
-; CHECK-MAXBW-NEXT: [[TMP7]] = fadd reassoc <vscale x 4 x float> [[TMP6]], [[VEC_PHI]]
+; CHECK-MAXBW-NEXT: [[TMP7]] = fadd reassoc contract <vscale x 4 x float> [[TMP6]], [[VEC_PHI]]
; CHECK-MAXBW-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-MAXBW-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-MAXBW-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]
; CHECK-MAXBW: [[MIDDLE_BLOCK]]:
-; CHECK-MAXBW-NEXT: [[TMP9:%.*]] = call reassoc float @llvm.vector.reduce.fadd.nxv4f32(float -0.000000e+00, <vscale x 4 x float> [[TMP7]])
+; CHECK-MAXBW-NEXT: [[TMP9:%.*]] = call reassoc contract float @llvm.vector.reduce.fadd.nxv4f32(float -0.000000e+00, <vscale x 4 x float> [[TMP7]])
; CHECK-MAXBW-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
; CHECK-MAXBW-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
; CHECK-MAXBW: [[SCALAR_PH]]:
@@ -1049,7 +1049,7 @@ define float @fdotp_noext_f32(ptr %a, ptr %b) #0 {
; CHECK-MAXBW-NEXT: [[GEP_B:%.*]] = getelementptr float, ptr [[B]], i64 [[IV]]
; CHECK-MAXBW-NEXT: [[LOAD_B:%.*]] = load float, ptr [[GEP_B]], align 1
; CHECK-MAXBW-NEXT: [[MUL:%.*]] = fmul float [[LOAD_B]], [[LOAD_A]]
-; CHECK-MAXBW-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[ACCUM]]
+; CHECK-MAXBW-NEXT: [[ADD]] = fadd reassoc contract float [[MUL]], [[ACCUM]]
; CHECK-MAXBW-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
; CHECK-MAXBW-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
; CHECK-MAXBW-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]]
@@ -1078,7 +1078,7 @@ define float @fdotp_noext_f32(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP5:%.*]] = getelementptr float, ptr [[B]], i64 [[INDEX]]
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 4 x float>, ptr [[TMP5]], align 1
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP6:%.*]] = fmul <vscale x 4 x float> [[WIDE_LOAD1]], [[WIDE_LOAD]]
-; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP7]] = fadd reassoc <vscale x 4 x float> [[TMP6]], [[VEC_PHI]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP7]] = fadd reassoc contract <vscale x 4 x float> [[TMP6]], [[VEC_PHI]]
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-INTERLEAVE1-SVE2P1-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
@@ -1098,7 +1098,7 @@ define float @fdotp_noext_f32(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[GEP_B:%.*]] = getelementptr float, ptr [[B]], i64 [[IV]]
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[LOAD_B:%.*]] = load float, ptr [[GEP_B]], align 1
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[MUL:%.*]] = fmul float [[LOAD_B]], [[LOAD_A]]
-; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ADD]] = fadd reassoc contract float [[MUL]], [[ACCUM]]
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
; CHECK-INTERLEAVE1-SVE2P1-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
@@ -1116,7 +1116,7 @@ for.body: ; preds = %for.body, %entry
%gep.b = getelementptr float, ptr %b, i64 %iv
%load.b = load float, ptr %gep.b, align 1
%mul = fmul float %load.b, %load.a
- %add = fadd reassoc float %mul, %accum
+ %add = fadd reassoc contract float %mul, %accum
%iv.next = add i64 %iv, 1
%exitcond.not = icmp eq i64 %iv.next, 1024
br i1 %exitcond.not, label %for.exit, label %for.body
@@ -1147,12 +1147,12 @@ define double @fdotp_noext_f64(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-NEXT: [[TMP5:%.*]] = getelementptr double, ptr [[B]], i64 [[INDEX]]
; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 2 x double>, ptr [[TMP5]], align 1
; CHECK-INTERLEAVE1-NEXT: [[TMP6:%.*]] = fmul <vscale x 2 x double> [[WIDE_LOAD1]], [[WIDE_LOAD]]
-; CHECK-INTERLEAVE1-NEXT: [[TMP7]] = fadd reassoc <vscale x 2 x double> [[TMP6]], [[VEC_PHI]]
+; CHECK-INTERLEAVE1-NEXT: [[TMP7]] = fadd reassoc contract <vscale x 2 x double> [[TMP6]], [[VEC_PHI]]
; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-INTERLEAVE1-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]
; CHECK-INTERLEAVE1: [[MIDDLE_BLOCK]]:
-; CHECK-INTERLEAVE1-NEXT: [[TMP9:%.*]] = call reassoc double @llvm.vector.reduce.fadd.nxv2f64(double -0.000000e+00, <vscale x 2 x double> [[TMP7]])
+; CHECK-INTERLEAVE1-NEXT: [[TMP9:%.*]] = call reassoc contract double @llvm.vector.reduce.fadd.nxv2f64(double -0.000000e+00, <vscale x 2 x double> [[TMP7]])
; CHECK-INTERLEAVE1-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
; CHECK-INTERLEAVE1-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
; CHECK-INTERLEAVE1: [[SCALAR_PH]]:
@@ -1167,7 +1167,7 @@ define double @fdotp_noext_f64(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-NEXT: [[GEP_B:%.*]] = getelementptr double, ptr [[B]], i64 [[IV]]
; CHECK-INTERLEAVE1-NEXT: [[LOAD_B:%.*]] = load double, ptr [[GEP_B]], align 1
; CHECK-INTERLEAVE1-NEXT: [[MUL:%.*]] = fmul double [[LOAD_B]], [[LOAD_A]]
-; CHECK-INTERLEAVE1-NEXT: [[ADD]] = fadd reassoc double [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVE1-NEXT: [[ADD]] = fadd reassoc contract double [[MUL]], [[ACCUM]]
; CHECK-INTERLEAVE1-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
; CHECK-INTERLEAVE1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
; CHECK-INTERLEAVE1-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]]
@@ -1206,14 +1206,14 @@ define double @fdotp_noext_f64(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD4:%.*]] = load <vscale x 2 x double>, ptr [[TMP11]], align 1
; CHECK-INTERLEAVED-NEXT: [[TMP12:%.*]] = fmul <vscale x 2 x double> [[WIDE_LOAD3]], [[WIDE_LOAD]]
; CHECK-INTERLEAVED-NEXT: [[TMP13:%.*]] = fmul <vscale x 2 x double> [[WIDE_LOAD4]], [[WIDE_LOAD2]]
-; CHECK-INTERLEAVED-NEXT: [[TMP14]] = fadd reassoc <vscale x 2 x double> [[TMP12]], [[VEC_PHI]]
-; CHECK-INTERLEAVED-NEXT: [[TMP15]] = fadd reassoc <vscale x 2 x double> [[TMP13]], [[VEC_PHI1]]
+; CHECK-INTERLEAVED-NEXT: [[TMP14]] = fadd reassoc contract <vscale x 2 x double> [[TMP12]], [[VEC_PHI]]
+; CHECK-INTERLEAVED-NEXT: [[TMP15]] = fadd reassoc contract <vscale x 2 x double> [[TMP13]], [[VEC_PHI1]]
; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-INTERLEAVED-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-INTERLEAVED-NEXT: br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]
; CHECK-INTERLEAVED: [[MIDDLE_BLOCK]]:
-; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc <vscale x 2 x double> [[TMP15]], [[TMP14]]
-; CHECK-INTERLEAVED-NEXT: [[TMP17:%.*]] = call reassoc double @llvm.vector.reduce.fadd.nxv2f64(double -0.000000e+00, <vscale x 2 x double> [[BIN_RDX]])
+; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc contract <vscale x 2 x double> [[TMP15]], [[TMP14]]
+; CHECK-INTERLEAVED-NEXT: [[TMP17:%.*]] = call reassoc contract double @llvm.vector.reduce.fadd.nxv2f64(double -0.000000e+00, <vscale x 2 x double> [[BIN_RDX]])
; CHECK-INTERLEAVED-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
; CHECK-INTERLEAVED-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
; CHECK-INTERLEAVED: [[SCALAR_PH]]:
@@ -1228,7 +1228,7 @@ define double @fdotp_noext_f64(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVED-NEXT: [[GEP_B:%.*]] = getelementptr double, ptr [[B]], i64 [[IV]]
; CHECK-INTERLEAVED-NEXT: [[LOAD_B:%.*]] = load double, ptr [[GEP_B]], align 1
; CHECK-INTERLEAVED-NEXT: [[MUL:%.*]] = fmul double [[LOAD_B]], [[LOAD_A]]
-; CHECK-INTERLEAVED-NEXT: [[ADD]] = fadd reassoc double [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVED-NEXT: [[ADD]] = fadd reassoc contract double [[MUL]], [[ACCUM]]
; CHECK-INTERLEAVED-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
; CHECK-INTERLEAVED-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
; CHECK-INTERLEAVED-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]]
@@ -1257,12 +1257,12 @@ define double @fdotp_noext_f64(ptr %a, ptr %b) #0 {
; CHECK-MAXBW-NEXT: [[TMP5:%.*]] = getelementptr double, ptr [[B]], i64 [[INDEX]]
; CHECK-MAXBW-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 2 x double>, ptr [[TMP5]], align 1
; CHECK-MAXBW-NEXT: [[TMP6:%.*]] = fmul <vscale x 2 x double> [[WIDE_LOAD1]], [[WIDE_LOAD]]
-; CHECK-MAXBW-NEXT: [[TMP7]] = fadd reassoc <vscale x 2 x double> [[TMP6]], [[VEC_PHI]]
+; CHECK-MAXBW-NEXT: [[TMP7]] = fadd reassoc contract <vscale x 2 x double> [[TMP6]], [[VEC_PHI]]
; CHECK-MAXBW-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-MAXBW-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-MAXBW-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]
; CHECK-MAXBW: [[MIDDLE_BLOCK]]:
-; CHECK-MAXBW-NEXT: [[TMP9:%.*]] = call reassoc double @llvm.vector.reduce.fadd.nxv2f64(double -0.000000e+00, <vscale x 2 x double> [[TMP7]])
+; CHECK-MAXBW-NEXT: [[TMP9:%.*]] = call reassoc contract double @llvm.vector.reduce.fadd.nxv2f64(double -0.000000e+00, <vscale x 2 x double> [[TMP7]])
; CHECK-MAXBW-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
; CHECK-MAXBW-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
; CHECK-MAXBW: [[SCALAR_PH]]:
@@ -1277,7 +1277,7 @@ define double @fdotp_noext_f64(ptr %a, ptr %b) #0 {
; CHECK-MAXBW-NEXT: [[GEP_B:%.*]] = getelementptr double, ptr [[B]], i64 [[IV]]
; CHECK-MAXBW-NEXT: [[LOAD_B:%.*]] = load double, ptr [[GEP_B]], align 1
; CHECK-MAXBW-NEXT: [[MUL:%.*]] = fmul double [[LOAD_B]], [[LOAD_A]]
-; CHECK-MAXBW-NEXT: [[ADD]] = fadd reassoc double [[MUL]], [[ACCUM]]
+; CHECK-MAXBW-NEXT: [[ADD]] = fadd reassoc contract double [[MUL]], [[ACCUM]]
; CHECK-MAXBW-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
; CHECK-MAXBW-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
; CHECK-MAXBW-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]]
@@ -1306,7 +1306,7 @@ define double @fdotp_noext_f64(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP5:%.*]] = getelementptr double, ptr [[B]], i64 [[INDEX]]
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 2 x double>, ptr [[TMP5]], align 1
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP6:%.*]] = fmul <vscale x 2 x double> [[WIDE_LOAD1]], [[WIDE_LOAD]]
-; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP7]] = fadd reassoc <vscale x 2 x double> [[TMP6]], [[VEC_PHI]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP7]] = fadd reassoc contract <vscale x 2 x double> [[TMP6]], [[VEC_PHI]]
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-INTERLEAVE1-SVE2P1-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]]
@@ -1326,7 +1326,7 @@ define double @fdotp_noext_f64(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[GEP_B:%.*]] = getelementptr double, ptr [[B]], i64 [[IV]]
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[LOAD_B:%.*]] = load double, ptr [[GEP_B]], align 1
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[MUL:%.*]] = fmul double [[LOAD_B]], [[LOAD_A]]
-; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ADD]] = fadd reassoc double [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ADD]] = fadd reassoc contract double [[MUL]], [[ACCUM]]
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
; CHECK-INTERLEAVE1-SVE2P1-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]
@@ -1344,7 +1344,7 @@ for.body: ; preds = %for.body, %entry
%gep.b = getelementptr double, ptr %b, i64 %iv
%load.b = load double, ptr %gep.b, align 1
%mul = fmul double %load.b, %load.a
- %add = fadd reassoc double %mul, %accum
+ %add = fadd reassoc contract double %mul, %accum
%iv.next = add i64 %iv, 1
%exitcond.not = icmp eq i64 %iv.next, 1024
br i1 %exitcond.not, label %for.exit, label %for.body
@@ -1377,12 +1377,12 @@ define double @not_fdotp_different_types(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 8 x float>, ptr [[GEP_B]], align 2
; CHECK-INTERLEAVE1-NEXT: [[TMP7:%.*]] = fpext <vscale x 8 x float> [[WIDE_LOAD1]] to <vscale x 8 x double>
; CHECK-INTERLEAVE1-NEXT: [[TMP8:%.*]] = fmul <vscale x 8 x double> [[TMP7]], [[TMP5]]
-; CHECK-INTERLEAVE1-NEXT: [[TMP9]] = fadd reassoc <vscale x 8 x double> [[TMP8]], [[VEC_PHI]]
+; CHECK-INTERLEAVE1-NEXT: [[TMP9]] = fadd reassoc contract <vscale x 8 x double> [[TMP8]], [[VEC_PHI]]
; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], [[TMP3]]
; CHECK-INTERLEAVE1-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]]
; CHECK-INTERLEAVE1: [[MIDDLE_BLOCK]]:
-; CHECK-INTERLEAVE1-NEXT: [[TMP11:%.*]] = call reassoc double @llvm.vector.reduce.fadd.nxv8f64(double -0.000000e+00, <vscale x 8 x double> [[TMP9]])
+; CHECK-INTERLEAVE1-NEXT: [[TMP11:%.*]] = call reassoc contract double @llvm.vector.reduce.fadd.nxv8f64(double -0.000000e+00, <vscale x 8 x double> [[TMP9]])
; CHECK-INTERLEAVE1-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
; CHECK-INTERLEAVE1-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
; CHECK-INTERLEAVE1: [[SCALAR_PH]]:
@@ -1399,7 +1399,7 @@ define double @not_fdotp_different_types(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-NEXT: [[LOAD_B:%.*]] = load float, ptr [[GEP_B1]], align 2
; CHECK-INTERLEAVE1-NEXT: [[EXT_B:%.*]] = fpext float [[LOAD_B]] to double
; CHECK-INTERLEAVE1-NEXT: [[MUL:%.*]] = fmul double [[EXT_B]], [[EXT_A]]
-; CHECK-INTERLEAVE1-NEXT: [[ADD]] = fadd reassoc double [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVE1-NEXT: [[ADD]] = fadd reassoc contract double [[MUL]], [[ACCUM]]
; CHECK-INTERLEAVE1-NEXT: [[IV_NEXT]] = add i64 [[IV1]], 1
; CHECK-INTERLEAVE1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
; CHECK-INTERLEAVE1-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]]
@@ -1442,14 +1442,14 @@ define double @not_fdotp_different_types(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVED-NEXT: [[TMP15:%.*]] = fpext <vscale x 8 x float> [[WIDE_LOAD4]] to <vscale x 8 x double>
; CHECK-INTERLEAVED-NEXT: [[TMP16:%.*]] = fmul <vscale x 8 x double> [[TMP14]], [[TMP8]]
; CHECK-INTERLEAVED-NEXT: [[TMP17:%.*]] = fmul <vscale x 8 x double> [[TMP15]], [[TMP9]]
-; CHECK-INTERLEAVED-NEXT: [[TMP18]] = fadd reassoc <vscale x 8 x double> [[TMP16]], [[VEC_PHI]]
-; CHECK-INTERLEAVED-NEXT: [[TMP19]] = fadd reassoc <vscale x 8 x double> [[TMP17]], [[VEC_PHI1]]
+; CHECK-INTERLEAVED-NEXT: [[TMP18]] = fadd reassoc contract <vscale x 8 x double> [[TMP16]], [[VEC_PHI]]
+; CHECK-INTERLEAVED-NEXT: [[TMP19]] = fadd reassoc contract <vscale x 8 x double> [[TMP17]], [[VEC_PHI1]]
; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], [[TMP3]]
; CHECK-INTERLEAVED-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-INTERLEAVED-NEXT: br i1 [[TMP20]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]]
; CHECK-INTERLEAVED: [[MIDDLE_BLOCK]]:
-; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc <vscale x 8 x double> [[TMP19]], [[TMP18]]
-; CHECK-INTERLEAVED-NEXT: [[TMP21:%.*]] = call reassoc double @llvm.vector.reduce.fadd.nxv8f64(double -0.000000e+00, <vscale x 8 x double> [[BIN_RDX]])
+; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc contract <vscale x 8 x double> [[TMP19]], [[TMP18]]
+; CHECK-INTERLEAVED-NEXT: [[TMP21:%.*]] = call reassoc contract double @llvm.vector.reduce.fadd.nxv8f64(double -0.000000e+00, <vscale x 8 x double> [[BIN_RDX]])
; CHECK-INTERLEAVED-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
; CHECK-INTERLEAVED-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
; CHECK-INTERLEAVED: [[SCALAR_PH]]:
@@ -1466,7 +1466,7 @@ define double @not_fdotp_different_types(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVED-NEXT: [[LOAD_B:%.*]] = load float, ptr [[GEP_B1]], align 2
; CHECK-INTERLEAVED-NEXT: [[EXT_B:%.*]] = fpext float [[LOAD_B]] to double
; CHECK-INTERLEAVED-NEXT: [[MUL:%.*]] = fmul double [[EXT_B]], [[EXT_A]]
-; CHECK-INTERLEAVED-NEXT: [[ADD]] = fadd reassoc double [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVED-NEXT: [[ADD]] = fadd reassoc contract double [[MUL]], [[ACCUM]]
; CHECK-INTERLEAVED-NEXT: [[IV_NEXT]] = add i64 [[IV1]], 1
; CHECK-INTERLEAVED-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
; CHECK-INTERLEAVED-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]]
@@ -1497,12 +1497,12 @@ define double @not_fdotp_different_types(ptr %a, ptr %b) #0 {
; CHECK-MAXBW-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 8 x float>, ptr [[TMP6]], align 2
; CHECK-MAXBW-NEXT: [[TMP7:%.*]] = fpext <vscale x 8 x float> [[WIDE_LOAD1]] to <vscale x 8 x double>
; CHECK-MAXBW-NEXT: [[TMP8:%.*]] = fmul <vscale x 8 x double> [[TMP7]], [[TMP5]]
-; CHECK-MAXBW-NEXT: [[TMP9]] = fadd reassoc <vscale x 8 x double> [[TMP8]], [[VEC_PHI]]
+; CHECK-MAXBW-NEXT: [[TMP9]] = fadd reassoc contract <vscale x 8 x double> [[TMP8]], [[VEC_PHI]]
; CHECK-MAXBW-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-MAXBW-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-MAXBW-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]]
; CHECK-MAXBW: [[MIDDLE_BLOCK]]:
-; CHECK-MAXBW-NEXT: [[TMP11:%.*]] = call reassoc double @llvm.vector.reduce.fadd.nxv8f64(double -0.000000e+00, <vscale x 8 x double> [[TMP9]])
+; CHECK-MAXBW-NEXT: [[TMP11:%.*]] = call reassoc contract double @llvm.vector.reduce.fadd.nxv8f64(double -0.000000e+00, <vscale x 8 x double> [[TMP9]])
; CHECK-MAXBW-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
; CHECK-MAXBW-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
; CHECK-MAXBW: [[SCALAR_PH]]:
@@ -1519,7 +1519,7 @@ define double @not_fdotp_different_types(ptr %a, ptr %b) #0 {
; CHECK-MAXBW-NEXT: [[LOAD_B:%.*]] = load float, ptr [[GEP_B]], align 2
; CHECK-MAXBW-NEXT: [[EXT_B:%.*]] = fpext float [[LOAD_B]] to double
; CHECK-MAXBW-NEXT: [[MUL:%.*]] = fmul double [[EXT_B]], [[EXT_A]]
-; CHECK-MAXBW-NEXT: [[ADD]] = fadd reassoc double [[MUL]], [[ACCUM]]
+; CHECK-MAXBW-NEXT: [[ADD]] = fadd reassoc contract double [[MUL]], [[ACCUM]]
; CHECK-MAXBW-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
; CHECK-MAXBW-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
; CHECK-MAXBW-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]]
@@ -1543,7 +1543,7 @@ define double @not_fdotp_different_types(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[WIDE_LOAD1:%.*]] = load <8 x float>, ptr [[TMP2]], align 2
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP3:%.*]] = fpext <8 x float> [[WIDE_LOAD1]] to <8 x double>
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP4:%.*]] = fmul <8 x double> [[TMP3]], [[TMP1]]
-; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP5]] = fadd reassoc <8 x double> [[TMP4]], [[VEC_PHI]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP5]] = fadd reassoc contract <8 x double> [[TMP4]], [[VEC_PHI]]
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
; CHECK-INTERLEAVE1-SVE2P1-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]]
@@ -1565,7 +1565,7 @@ for.body: ; preds = %for.body, %entry
%load.b = load float, ptr %gep.b, align 2
%ext.b = fpext float %load.b to double
%mul = fmul double %ext.b, %ext.a
- %add = fadd reassoc double %mul, %accum
+ %add = fadd reassoc contract double %mul, %accum
%iv.next = add i64 %iv, 1
%exitcond.not = icmp eq i64 %iv.next, 1024
br i1 %exitcond.not, label %for.exit, label %for.body
@@ -1597,7 +1597,7 @@ define float @not_fdotp_not_phi(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 8 x half>, ptr [[TMP6]], align 1
; CHECK-INTERLEAVE1-NEXT: [[TMP7:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD1]] to <vscale x 8 x float>
; CHECK-INTERLEAVE1-NEXT: [[TMP8:%.*]] = fmul <vscale x 8 x float> [[TMP7]], [[TMP5]]
-; CHECK-INTERLEAVE1-NEXT: [[TMP9:%.*]] = fadd reassoc <vscale x 8 x float> [[TMP8]], [[TMP7]]
+; CHECK-INTERLEAVE1-NEXT: [[TMP9:%.*]] = fadd reassoc contract <vscale x 8 x float> [[TMP8]], [[TMP7]]
; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-INTERLEAVE1-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]]
@@ -1622,7 +1622,7 @@ define float @not_fdotp_not_phi(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
; CHECK-INTERLEAVE1-NEXT: [[EXT_B:%.*]] = fpext half [[LOAD_B]] to float
; CHECK-INTERLEAVE1-NEXT: [[MUL:%.*]] = fmul float [[EXT_B]], [[EXT_A]]
-; CHECK-INTERLEAVE1-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[EXT_B]]
+; CHECK-INTERLEAVE1-NEXT: [[ADD]] = fadd reassoc contract float [[MUL]], [[EXT_B]]
; CHECK-INTERLEAVE1-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
; CHECK-INTERLEAVE1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
; CHECK-INTERLEAVE1-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP17:![0-9]+]]
@@ -1658,7 +1658,7 @@ define float @not_fdotp_not_phi(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 8 x half>, ptr [[TMP12]], align 1
; CHECK-INTERLEAVED-NEXT: [[TMP13:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD1]] to <vscale x 8 x float>
; CHECK-INTERLEAVED-NEXT: [[TMP14:%.*]] = fmul <vscale x 8 x float> [[TMP13]], [[TMP8]]
-; CHECK-INTERLEAVED-NEXT: [[TMP15:%.*]] = fadd reassoc <vscale x 8 x float> [[TMP14]], [[TMP13]]
+; CHECK-INTERLEAVED-NEXT: [[TMP15:%.*]] = fadd reassoc contract <vscale x 8 x float> [[TMP14]], [[TMP13]]
; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-INTERLEAVED-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-INTERLEAVED-NEXT: br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]]
@@ -1683,7 +1683,7 @@ define float @not_fdotp_not_phi(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVED-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
; CHECK-INTERLEAVED-NEXT: [[EXT_B:%.*]] = fpext half [[LOAD_B]] to float
; CHECK-INTERLEAVED-NEXT: [[MUL:%.*]] = fmul float [[EXT_B]], [[EXT_A]]
-; CHECK-INTERLEAVED-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[EXT_B]]
+; CHECK-INTERLEAVED-NEXT: [[ADD]] = fadd reassoc contract float [[MUL]], [[EXT_B]]
; CHECK-INTERLEAVED-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
; CHECK-INTERLEAVED-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
; CHECK-INTERLEAVED-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP17:![0-9]+]]
@@ -1713,7 +1713,7 @@ define float @not_fdotp_not_phi(ptr %a, ptr %b) #0 {
; CHECK-MAXBW-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 8 x half>, ptr [[TMP6]], align 1
; CHECK-MAXBW-NEXT: [[TMP7:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD1]] to <vscale x 8 x float>
; CHECK-MAXBW-NEXT: [[TMP8:%.*]] = fmul <vscale x 8 x float> [[TMP7]], [[TMP5]]
-; CHECK-MAXBW-NEXT: [[TMP9:%.*]] = fadd reassoc <vscale x 8 x float> [[TMP8]], [[TMP7]]
+; CHECK-MAXBW-NEXT: [[TMP9:%.*]] = fadd reassoc contract <vscale x 8 x float> [[TMP8]], [[TMP7]]
; CHECK-MAXBW-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-MAXBW-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-MAXBW-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]]
@@ -1738,7 +1738,7 @@ define float @not_fdotp_not_phi(ptr %a, ptr %b) #0 {
; CHECK-MAXBW-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
; CHECK-MAXBW-NEXT: [[EXT_B:%.*]] = fpext half [[LOAD_B]] to float
; CHECK-MAXBW-NEXT: [[MUL:%.*]] = fmul float [[EXT_B]], [[EXT_A]]
-; CHECK-MAXBW-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[EXT_B]]
+; CHECK-MAXBW-NEXT: [[ADD]] = fadd reassoc contract float [[MUL]], [[EXT_B]]
; CHECK-MAXBW-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
; CHECK-MAXBW-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
; CHECK-MAXBW-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP17:![0-9]+]]
@@ -1768,7 +1768,7 @@ define float @not_fdotp_not_phi(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 8 x half>, ptr [[TMP6]], align 1
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP7:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD1]] to <vscale x 8 x float>
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP8:%.*]] = fmul <vscale x 8 x float> [[TMP7]], [[TMP5]]
-; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP9:%.*]] = fadd reassoc <vscale x 8 x float> [[TMP8]], [[TMP7]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP9:%.*]] = fadd reassoc contract <vscale x 8 x float> [[TMP8]], [[TMP7]]
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-INTERLEAVE1-SVE2P1-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]
@@ -1793,7 +1793,7 @@ define float @not_fdotp_not_phi(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[EXT_B:%.*]] = fpext half [[LOAD_B]] to float
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[MUL:%.*]] = fmul float [[EXT_B]], [[EXT_A]]
-; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[EXT_B]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ADD]] = fadd reassoc contract float [[MUL]], [[EXT_B]]
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
; CHECK-INTERLEAVE1-SVE2P1-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]]
@@ -1813,7 +1813,7 @@ for.body: ; preds = %for.body, %entry
%load.b = load half, ptr %gep.b, align 1
%ext.b = fpext half %load.b to float
%mul = fmul float %ext.b, %ext.a
- %add = fadd reassoc float %mul, %ext.b
+ %add = fadd reassoc contract float %mul, %ext.b
%iv.next = add i64 %iv, 1
%exitcond.not = icmp eq i64 %iv.next, 1024
br i1 %exitcond.not, label %for.exit, label %for.body
@@ -1876,7 +1876,7 @@ define float @not_fdotp_not_phi2(ptr %matrix, i32 %n, half %a, half %a1) #0 {
; CHECK-INTERLEAVE1-NEXT: [[TMP23:%.*]] = insertelement <4 x half> [[TMP22]], half [[TMP19]], i32 3
; CHECK-INTERLEAVE1-NEXT: [[TMP24:%.*]] = fpext <4 x half> [[TMP23]] to <4 x float>
; CHECK-INTERLEAVE1-NEXT: [[TMP25:%.*]] = fmul <4 x float> [[BROADCAST_SPLAT]], [[TMP24]]
-; CHECK-INTERLEAVE1-NEXT: [[TMP26:%.*]] = fadd reassoc <4 x float> [[TMP25]], [[VEC_PHI]]
+; CHECK-INTERLEAVE1-NEXT: [[TMP26:%.*]] = fadd reassoc contract <4 x float> [[TMP25]], [[VEC_PHI]]
; CHECK-INTERLEAVE1-NEXT: [[TMP27:%.*]] = load half, ptr [[TMP12]], align 1
; CHECK-INTERLEAVE1-NEXT: [[TMP28:%.*]] = load half, ptr [[TMP13]], align 1
; CHECK-INTERLEAVE1-NEXT: [[TMP29:%.*]] = load half, ptr [[TMP14]], align 1
@@ -1887,18 +1887,18 @@ define float @not_fdotp_not_phi2(ptr %matrix, i32 %n, half %a, half %a1) #0 {
; CHECK-INTERLEAVE1-NEXT: [[TMP34:%.*]] = insertelement <4 x half> [[TMP33]], half [[TMP30]], i32 3
; CHECK-INTERLEAVE1-NEXT: [[TMP35:%.*]] = fpext <4 x half> [[TMP34]] to <4 x float>
; CHECK-INTERLEAVE1-NEXT: [[TMP36:%.*]] = fmul <4 x float> [[BROADCAST_SPLAT2]], [[TMP35]]
-; CHECK-INTERLEAVE1-NEXT: [[TMP37]] = fadd reassoc <4 x float> [[TMP36]], [[TMP26]]
+; CHECK-INTERLEAVE1-NEXT: [[TMP37]] = fadd reassoc contract <4 x float> [[TMP36]], [[TMP26]]
; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-INTERLEAVE1-NEXT: [[TMP38:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP38]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP18:![0-9]+]]
; CHECK-INTERLEAVE1: [[MIDDLE_BLOCK]]:
-; CHECK-INTERLEAVE1-NEXT: [[TMP39:%.*]] = call reassoc float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[TMP37]])
+; CHECK-INTERLEAVE1-NEXT: [[TMP42:%.*]] = call reassoc contract float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[TMP37]])
; CHECK-INTERLEAVE1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]
; CHECK-INTERLEAVE1-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
; CHECK-INTERLEAVE1: [[SCALAR_PH]]:
; CHECK-INTERLEAVE1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[TMP1]], %[[MIDDLE_BLOCK]] ], [ 0, %[[FOR_PREHEADER]] ]
; CHECK-INTERLEAVE1-NEXT: [[BC_RESUME_VAL6:%.*]] = phi ptr [ [[TMP3]], %[[MIDDLE_BLOCK]] ], [ [[MATRIX]], %[[FOR_PREHEADER]] ]
-; CHECK-INTERLEAVE1-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP39]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[FOR_PREHEADER]] ]
+; CHECK-INTERLEAVE1-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP42]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[FOR_PREHEADER]] ]
; CHECK-INTERLEAVE1-NEXT: br label %[[FOR_BODY:.*]]
; CHECK-INTERLEAVE1: [[FOR_BODY]]:
; CHECK-INTERLEAVE1-NEXT: [[IV:%.*]] = phi i32 [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]
@@ -1909,17 +1909,17 @@ define float @not_fdotp_not_phi2(ptr %matrix, i32 %n, half %a, half %a1) #0 {
; CHECK-INTERLEAVE1-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
; CHECK-INTERLEAVE1-NEXT: [[B_EXT:%.*]] = fpext half [[LOAD_B]] to float
; CHECK-INTERLEAVE1-NEXT: [[MUL:%.*]] = fmul float [[A_EXT]], [[B_EXT]]
-; CHECK-INTERLEAVE1-NEXT: [[ADD:%.*]] = fadd reassoc float [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVE1-NEXT: [[ADD:%.*]] = fadd reassoc contract float [[MUL]], [[ACCUM]]
; CHECK-INTERLEAVE1-NEXT: [[LOAD_B1:%.*]] = load half, ptr [[GEP_B1]], align 1
; CHECK-INTERLEAVE1-NEXT: [[B_EXT1:%.*]] = fpext half [[LOAD_B1]] to float
; CHECK-INTERLEAVE1-NEXT: [[MUL_1:%.*]] = fmul float [[A_EXT1]], [[B_EXT1]]
-; CHECK-INTERLEAVE1-NEXT: [[ADD_1]] = fadd reassoc float [[MUL_1]], [[ADD]]
+; CHECK-INTERLEAVE1-NEXT: [[ADD_1]] = fadd reassoc contract float [[MUL_1]], [[ADD]]
; CHECK-INTERLEAVE1-NEXT: [[SCEVGEP]] = getelementptr half, ptr [[PTR]], i64 16
; CHECK-INTERLEAVE1-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
; CHECK-INTERLEAVE1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[IV_NEXT]], [[N]]
; CHECK-INTERLEAVE1-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP19:![0-9]+]]
; CHECK-INTERLEAVE1: [[FOR_EXIT]]:
-; CHECK-INTERLEAVE1-NEXT: [[ADD_FLOAT:%.*]] = phi float [ [[ADD_1]], %[[FOR_BODY]] ], [ [[TMP39]], %[[MIDDLE_BLOCK]] ]
+; CHECK-INTERLEAVE1-NEXT: [[ADD_FLOAT:%.*]] = phi float [ [[ADD_1]], %[[FOR_BODY]] ], [ [[TMP42]], %[[MIDDLE_BLOCK]] ]
; CHECK-INTERLEAVE1-NEXT: br label %[[EXIT:.*]]
; CHECK-INTERLEAVE1: [[EXIT]]:
; CHECK-INTERLEAVE1-NEXT: [[RESULT:%.*]] = phi float [ [[ADD_FLOAT]], %[[FOR_EXIT]] ]
@@ -2005,8 +2005,8 @@ define float @not_fdotp_not_phi2(ptr %matrix, i32 %n, half %a, half %a1) #0 {
; CHECK-INTERLEAVED-NEXT: [[TMP45:%.*]] = fpext <4 x half> [[TMP43]] to <4 x float>
; CHECK-INTERLEAVED-NEXT: [[TMP46:%.*]] = fmul <4 x float> [[BROADCAST_SPLAT]], [[TMP44]]
; CHECK-INTERLEAVED-NEXT: [[TMP47:%.*]] = fmul <4 x float> [[BROADCAST_SPLAT]], [[TMP45]]
-; CHECK-INTERLEAVED-NEXT: [[TMP48:%.*]] = fadd reassoc <4 x float> [[TMP46]], [[VEC_PHI]]
-; CHECK-INTERLEAVED-NEXT: [[TMP49:%.*]] = fadd reassoc <4 x float> [[TMP47]], [[VEC_PHI3]]
+; CHECK-INTERLEAVED-NEXT: [[TMP48:%.*]] = fadd reassoc contract <4 x float> [[TMP46]], [[VEC_PHI]]
+; CHECK-INTERLEAVED-NEXT: [[TMP49:%.*]] = fadd reassoc contract <4 x float> [[TMP47]], [[VEC_PHI3]]
; CHECK-INTERLEAVED-NEXT: [[TMP50:%.*]] = load half, ptr [[TMP20]], align 1
; CHECK-INTERLEAVED-NEXT: [[TMP51:%.*]] = load half, ptr [[TMP21]], align 1
; CHECK-INTERLEAVED-NEXT: [[TMP52:%.*]] = load half, ptr [[TMP22]], align 1
@@ -2027,20 +2027,20 @@ define float @not_fdotp_not_phi2(ptr %matrix, i32 %n, half %a, half %a1) #0 {
; CHECK-INTERLEAVED-NEXT: [[TMP67:%.*]] = fpext <4 x half> [[TMP65]] to <4 x float>
; CHECK-INTERLEAVED-NEXT: [[TMP68:%.*]] = fmul <4 x float> [[BROADCAST_SPLAT2]], [[TMP66]]
; CHECK-INTERLEAVED-NEXT: [[TMP69:%.*]] = fmul <4 x float> [[BROADCAST_SPLAT2]], [[TMP67]]
-; CHECK-INTERLEAVED-NEXT: [[TMP70]] = fadd reassoc <4 x float> [[TMP68]], [[TMP48]]
-; CHECK-INTERLEAVED-NEXT: [[TMP71]] = fadd reassoc <4 x float> [[TMP69]], [[TMP49]]
+; CHECK-INTERLEAVED-NEXT: [[TMP70]] = fadd reassoc contract <4 x float> [[TMP68]], [[TMP48]]
+; CHECK-INTERLEAVED-NEXT: [[TMP71]] = fadd reassoc contract <4 x float> [[TMP69]], [[TMP49]]
; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
; CHECK-INTERLEAVED-NEXT: [[TMP72:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-INTERLEAVED-NEXT: br i1 [[TMP72]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP18:![0-9]+]]
; CHECK-INTERLEAVED: [[MIDDLE_BLOCK]]:
-; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc <4 x float> [[TMP71]], [[TMP70]]
-; CHECK-INTERLEAVED-NEXT: [[TMP73:%.*]] = call reassoc float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[BIN_RDX]])
+; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc contract <4 x float> [[TMP71]], [[TMP70]]
+; CHECK-INTERLEAVED-NEXT: [[TMP76:%.*]] = call reassoc contract float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[BIN_RDX]])
; CHECK-INTERLEAVED-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]
; CHECK-INTERLEAVED-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
; CHECK-INTERLEAVED: [[SCALAR_PH]]:
; CHECK-INTERLEAVED-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[TMP1]], %[[MIDDLE_BLOCK]] ], [ 0, %[[FOR_PREHEADER]] ]
; CHECK-INTERLEAVED-NEXT: [[BC_RESUME_VAL11:%.*]] = phi ptr [ [[TMP3]], %[[MIDDLE_BLOCK]] ], [ [[MATRIX]], %[[FOR_PREHEADER]] ]
-; CHECK-INTERLEAVED-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP73]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[FOR_PREHEADER]] ]
+; CHECK-INTERLEAVED-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP76]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[FOR_PREHEADER]] ]
; CHECK-INTERLEAVED-NEXT: br label %[[FOR_BODY:.*]]
; CHECK-INTERLEAVED: [[FOR_BODY]]:
; CHECK-INTERLEAVED-NEXT: [[IV:%.*]] = phi i32 [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]
@@ -2051,17 +2051,17 @@ define float @not_fdotp_not_phi2(ptr %matrix, i32 %n, half %a, half %a1) #0 {
; CHECK-INTERLEAVED-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
; CHECK-INTERLEAVED-NEXT: [[B_EXT:%.*]] = fpext half [[LOAD_B]] to float
; CHECK-INTERLEAVED-NEXT: [[MUL:%.*]] = fmul float [[A_EXT]], [[B_EXT]]
-; CHECK-INTERLEAVED-NEXT: [[ADD:%.*]] = fadd reassoc float [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVED-NEXT: [[ADD:%.*]] = fadd reassoc contract float [[MUL]], [[ACCUM]]
; CHECK-INTERLEAVED-NEXT: [[LOAD_B1:%.*]] = load half, ptr [[GEP_B1]], align 1
; CHECK-INTERLEAVED-NEXT: [[B_EXT1:%.*]] = fpext half [[LOAD_B1]] to float
; CHECK-INTERLEAVED-NEXT: [[MUL_1:%.*]] = fmul float [[A_EXT1]], [[B_EXT1]]
-; CHECK-INTERLEAVED-NEXT: [[ADD_1]] = fadd reassoc float [[MUL_1]], [[ADD]]
+; CHECK-INTERLEAVED-NEXT: [[ADD_1]] = fadd reassoc contract float [[MUL_1]], [[ADD]]
; CHECK-INTERLEAVED-NEXT: [[SCEVGEP]] = getelementptr half, ptr [[PTR]], i64 16
; CHECK-INTERLEAVED-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
; CHECK-INTERLEAVED-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[IV_NEXT]], [[N]]
; CHECK-INTERLEAVED-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP19:![0-9]+]]
; CHECK-INTERLEAVED: [[FOR_EXIT]]:
-; CHECK-INTERLEAVED-NEXT: [[ADD_FLOAT:%.*]] = phi float [ [[ADD_1]], %[[FOR_BODY]] ], [ [[TMP73]], %[[MIDDLE_BLOCK]] ]
+; CHECK-INTERLEAVED-NEXT: [[ADD_FLOAT:%.*]] = phi float [ [[ADD_1]], %[[FOR_BODY]] ], [ [[TMP76]], %[[MIDDLE_BLOCK]] ]
; CHECK-INTERLEAVED-NEXT: br label %[[EXIT:.*]]
; CHECK-INTERLEAVED: [[EXIT]]:
; CHECK-INTERLEAVED-NEXT: [[RESULT:%.*]] = phi float [ [[ADD_FLOAT]], %[[FOR_EXIT]] ]
@@ -2120,7 +2120,7 @@ define float @not_fdotp_not_phi2(ptr %matrix, i32 %n, half %a, half %a1) #0 {
; CHECK-MAXBW-NEXT: [[TMP23:%.*]] = insertelement <4 x half> [[TMP22]], half [[TMP19]], i32 3
; CHECK-MAXBW-NEXT: [[TMP24:%.*]] = fpext <4 x half> [[TMP23]] to <4 x float>
; CHECK-MAXBW-NEXT: [[TMP25:%.*]] = fmul <4 x float> [[BROADCAST_SPLAT]], [[TMP24]]
-; CHECK-MAXBW-NEXT: [[TMP26:%.*]] = fadd reassoc <4 x float> [[TMP25]], [[VEC_PHI]]
+; CHECK-MAXBW-NEXT: [[TMP26:%.*]] = fadd reassoc contract <4 x float> [[TMP25]], [[VEC_PHI]]
; CHECK-MAXBW-NEXT: [[TMP27:%.*]] = load half, ptr [[TMP12]], align 1
; CHECK-MAXBW-NEXT: [[TMP28:%.*]] = load half, ptr [[TMP13]], align 1
; CHECK-MAXBW-NEXT: [[TMP29:%.*]] = load half, ptr [[TMP14]], align 1
@@ -2131,18 +2131,18 @@ define float @not_fdotp_not_phi2(ptr %matrix, i32 %n, half %a, half %a1) #0 {
; CHECK-MAXBW-NEXT: [[TMP34:%.*]] = insertelement <4 x half> [[TMP33]], half [[TMP30]], i32 3
; CHECK-MAXBW-NEXT: [[TMP35:%.*]] = fpext <4 x half> [[TMP34]] to <4 x float>
; CHECK-MAXBW-NEXT: [[TMP36:%.*]] = fmul <4 x float> [[BROADCAST_SPLAT2]], [[TMP35]]
-; CHECK-MAXBW-NEXT: [[TMP37]] = fadd reassoc <4 x float> [[TMP36]], [[TMP26]]
+; CHECK-MAXBW-NEXT: [[TMP37]] = fadd reassoc contract <4 x float> [[TMP36]], [[TMP26]]
; CHECK-MAXBW-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-MAXBW-NEXT: [[TMP38:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-MAXBW-NEXT: br i1 [[TMP38]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP18:![0-9]+]]
; CHECK-MAXBW: [[MIDDLE_BLOCK]]:
-; CHECK-MAXBW-NEXT: [[TMP39:%.*]] = call reassoc float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[TMP37]])
+; CHECK-MAXBW-NEXT: [[TMP42:%.*]] = call reassoc contract float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[TMP37]])
; CHECK-MAXBW-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]
; CHECK-MAXBW-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
; CHECK-MAXBW: [[SCALAR_PH]]:
; CHECK-MAXBW-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[TMP1]], %[[MIDDLE_BLOCK]] ], [ 0, %[[FOR_PREHEADER]] ]
; CHECK-MAXBW-NEXT: [[BC_RESUME_VAL6:%.*]] = phi ptr [ [[TMP3]], %[[MIDDLE_BLOCK]] ], [ [[MATRIX]], %[[FOR_PREHEADER]] ]
-; CHECK-MAXBW-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP39]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[FOR_PREHEADER]] ]
+; CHECK-MAXBW-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP42]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[FOR_PREHEADER]] ]
; CHECK-MAXBW-NEXT: br label %[[FOR_BODY:.*]]
; CHECK-MAXBW: [[FOR_BODY]]:
; CHECK-MAXBW-NEXT: [[IV:%.*]] = phi i32 [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]
@@ -2153,17 +2153,17 @@ define float @not_fdotp_not_phi2(ptr %matrix, i32 %n, half %a, half %a1) #0 {
; CHECK-MAXBW-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
; CHECK-MAXBW-NEXT: [[B_EXT:%.*]] = fpext half [[LOAD_B]] to float
; CHECK-MAXBW-NEXT: [[MUL:%.*]] = fmul float [[A_EXT]], [[B_EXT]]
-; CHECK-MAXBW-NEXT: [[ADD:%.*]] = fadd reassoc float [[MUL]], [[ACCUM]]
+; CHECK-MAXBW-NEXT: [[ADD:%.*]] = fadd reassoc contract float [[MUL]], [[ACCUM]]
; CHECK-MAXBW-NEXT: [[LOAD_B1:%.*]] = load half, ptr [[GEP_B1]], align 1
; CHECK-MAXBW-NEXT: [[B_EXT1:%.*]] = fpext half [[LOAD_B1]] to float
; CHECK-MAXBW-NEXT: [[MUL_1:%.*]] = fmul float [[A_EXT1]], [[B_EXT1]]
-; CHECK-MAXBW-NEXT: [[ADD_1]] = fadd reassoc float [[MUL_1]], [[ADD]]
+; CHECK-MAXBW-NEXT: [[ADD_1]] = fadd reassoc contract float [[MUL_1]], [[ADD]]
; CHECK-MAXBW-NEXT: [[SCEVGEP]] = getelementptr half, ptr [[PTR]], i64 16
; CHECK-MAXBW-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
; CHECK-MAXBW-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[IV_NEXT]], [[N]]
; CHECK-MAXBW-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP19:![0-9]+]]
; CHECK-MAXBW: [[FOR_EXIT]]:
-; CHECK-MAXBW-NEXT: [[ADD_FLOAT:%.*]] = phi float [ [[ADD_1]], %[[FOR_BODY]] ], [ [[TMP39]], %[[MIDDLE_BLOCK]] ]
+; CHECK-MAXBW-NEXT: [[ADD_FLOAT:%.*]] = phi float [ [[ADD_1]], %[[FOR_BODY]] ], [ [[TMP42]], %[[MIDDLE_BLOCK]] ]
; CHECK-MAXBW-NEXT: br label %[[EXIT:.*]]
; CHECK-MAXBW: [[EXIT]]:
; CHECK-MAXBW-NEXT: [[RESULT:%.*]] = phi float [ [[ADD_FLOAT]], %[[FOR_EXIT]] ]
@@ -2222,7 +2222,7 @@ define float @not_fdotp_not_phi2(ptr %matrix, i32 %n, half %a, half %a1) #0 {
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP25:%.*]] = insertelement <4 x half> [[TMP24]], half [[TMP21]], i32 3
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP26:%.*]] = fpext <4 x half> [[TMP25]] to <4 x float>
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP27:%.*]] = fmul <4 x float> [[BROADCAST_SPLAT]], [[TMP26]]
-; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP28:%.*]] = fadd reassoc <4 x float> [[TMP27]], [[VEC_PHI]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP28:%.*]] = fadd reassoc contract <4 x float> [[TMP27]], [[VEC_PHI]]
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP29:%.*]] = load half, ptr [[TMP14]], align 1
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP30:%.*]] = load half, ptr [[TMP15]], align 1
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP31:%.*]] = load half, ptr [[TMP16]], align 1
@@ -2233,7 +2233,7 @@ define float @not_fdotp_not_phi2(ptr %matrix, i32 %n, half %a, half %a1) #0 {
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP36:%.*]] = insertelement <4 x half> [[TMP35]], half [[TMP32]], i32 3
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP37:%.*]] = fpext <4 x half> [[TMP36]] to <4 x float>
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP38:%.*]] = fmul <4 x float> [[BROADCAST_SPLAT2]], [[TMP37]]
-; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP39]] = fadd reassoc <4 x float> [[TMP38]], [[TMP28]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP39]] = fadd reassoc contract <4 x float> [[TMP38]], [[TMP28]]
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP40:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-INTERLEAVE1-SVE2P1-NEXT: br i1 [[TMP40]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]]
@@ -2255,11 +2255,11 @@ define float @not_fdotp_not_phi2(ptr %matrix, i32 %n, half %a, half %a1) #0 {
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[B_EXT:%.*]] = fpext half [[LOAD_B]] to float
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[MUL:%.*]] = fmul float [[A_EXT]], [[B_EXT]]
-; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ADD:%.*]] = fadd reassoc float [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ADD:%.*]] = fadd reassoc contract float [[MUL]], [[ACCUM]]
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[LOAD_B1:%.*]] = load half, ptr [[GEP_B1]], align 1
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[B_EXT1:%.*]] = fpext half [[LOAD_B1]] to float
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[MUL_1:%.*]] = fmul float [[A_EXT1]], [[B_EXT1]]
-; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ADD_1]] = fadd reassoc float [[MUL_1]], [[ADD]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ADD_1]] = fadd reassoc contract float [[MUL_1]], [[ADD]]
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[PTR_IV_NEXT]] = getelementptr half, ptr [[PTR_IV]], i64 16
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[IV_NEXT]], [[N]]
@@ -2287,11 +2287,11 @@ for.body: ; preds = %for.preheader, %for.body
%load.b = load half, ptr %gep.b, align 1
%b.ext = fpext half %load.b to float
%mul = fmul float %a.ext, %b.ext
- %add = fadd reassoc float %mul, %accum
+ %add = fadd reassoc contract float %mul, %accum
%load.b1 = load half, ptr %gep.b1, align 1
%b.ext1 = fpext half %load.b1 to float
%mul.1 = fmul float %a.ext1, %b.ext1
- %add.1 = fadd reassoc float %mul.1, %add
+ %add.1 = fadd reassoc contract float %mul.1, %add
%ptr.iv.next = getelementptr half, ptr %ptr.iv, i64 16
%iv.next = add nuw nsw i32 %iv, 1
%exitcond.not = icmp eq i32 %iv.next, %n
@@ -2332,12 +2332,12 @@ define float @not_fdotp_ext_outside_plan(ptr %a, half %b, i64 %n) #0 {
; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 8 x half>, ptr [[TMP0]], align 2
; CHECK-INTERLEAVE1-NEXT: [[TMP5:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD]] to <vscale x 8 x float>
; CHECK-INTERLEAVE1-NEXT: [[TMP6:%.*]] = fmul <vscale x 8 x float> [[TMP5]], [[BROADCAST_SPLAT]]
-; CHECK-INTERLEAVE1-NEXT: [[TMP7]] = fadd reassoc <vscale x 8 x float> [[TMP6]], [[VEC_PHI]]
+; CHECK-INTERLEAVE1-NEXT: [[TMP7]] = fadd reassoc contract <vscale x 8 x float> [[TMP6]], [[VEC_PHI]]
; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-INTERLEAVE1-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP20:![0-9]+]]
; CHECK-INTERLEAVE1: [[MIDDLE_BLOCK]]:
-; CHECK-INTERLEAVE1-NEXT: [[TMP9:%.*]] = call reassoc float @llvm.vector.reduce.fadd.nxv8f32(float -0.000000e+00, <vscale x 8 x float> [[TMP7]])
+; CHECK-INTERLEAVE1-NEXT: [[TMP9:%.*]] = call reassoc contract float @llvm.vector.reduce.fadd.nxv8f32(float -0.000000e+00, <vscale x 8 x float> [[TMP7]])
; CHECK-INTERLEAVE1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
; CHECK-INTERLEAVE1-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
; CHECK-INTERLEAVE1: [[SCALAR_PH]]:
@@ -2351,7 +2351,7 @@ define float @not_fdotp_ext_outside_plan(ptr %a, half %b, i64 %n) #0 {
; CHECK-INTERLEAVE1-NEXT: [[LOAD_A:%.*]] = load half, ptr [[GEP_A]], align 2
; CHECK-INTERLEAVE1-NEXT: [[EXT_A:%.*]] = fpext half [[LOAD_A]] to float
; CHECK-INTERLEAVE1-NEXT: [[MUL:%.*]] = fmul float [[EXT_A]], [[EXT_B]]
-; CHECK-INTERLEAVE1-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVE1-NEXT: [[ADD]] = fadd reassoc contract float [[MUL]], [[ACCUM]]
; CHECK-INTERLEAVE1-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-INTERLEAVE1-NEXT: [[CMP_1:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
; CHECK-INTERLEAVE1-NEXT: br i1 [[CMP_1]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP21:![0-9]+]]
@@ -2391,14 +2391,14 @@ define float @not_fdotp_ext_outside_plan(ptr %a, half %b, i64 %n) #0 {
; CHECK-INTERLEAVED-NEXT: [[TMP9:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD2]] to <vscale x 8 x float>
; CHECK-INTERLEAVED-NEXT: [[TMP10:%.*]] = fmul <vscale x 8 x float> [[TMP14]], [[BROADCAST_SPLAT]]
; CHECK-INTERLEAVED-NEXT: [[TMP11:%.*]] = fmul <vscale x 8 x float> [[TMP9]], [[BROADCAST_SPLAT]]
-; CHECK-INTERLEAVED-NEXT: [[TMP12]] = fadd reassoc <vscale x 8 x float> [[TMP10]], [[VEC_PHI]]
-; CHECK-INTERLEAVED-NEXT: [[TMP13]] = fadd reassoc <vscale x 8 x float> [[TMP11]], [[VEC_PHI1]]
+; CHECK-INTERLEAVED-NEXT: [[TMP12]] = fadd reassoc contract <vscale x 8 x float> [[TMP10]], [[VEC_PHI]]
+; CHECK-INTERLEAVED-NEXT: [[TMP13]] = fadd reassoc contract <vscale x 8 x float> [[TMP11]], [[VEC_PHI1]]
; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-INTERLEAVED-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-INTERLEAVED-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP20:![0-9]+]]
; CHECK-INTERLEAVED: [[MIDDLE_BLOCK]]:
-; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc <vscale x 8 x float> [[TMP13]], [[TMP12]]
-; CHECK-INTERLEAVED-NEXT: [[TMP15:%.*]] = call reassoc float @llvm.vector.reduce.fadd.nxv8f32(float -0.000000e+00, <vscale x 8 x float> [[BIN_RDX]])
+; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc contract <vscale x 8 x float> [[TMP13]], [[TMP12]]
+; CHECK-INTERLEAVED-NEXT: [[TMP15:%.*]] = call reassoc contract float @llvm.vector.reduce.fadd.nxv8f32(float -0.000000e+00, <vscale x 8 x float> [[BIN_RDX]])
; CHECK-INTERLEAVED-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
; CHECK-INTERLEAVED-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
; CHECK-INTERLEAVED: [[SCALAR_PH]]:
@@ -2412,7 +2412,7 @@ define float @not_fdotp_ext_outside_plan(ptr %a, half %b, i64 %n) #0 {
; CHECK-INTERLEAVED-NEXT: [[LOAD_A:%.*]] = load half, ptr [[GEP_A]], align 2
; CHECK-INTERLEAVED-NEXT: [[EXT_A:%.*]] = fpext half [[LOAD_A]] to float
; CHECK-INTERLEAVED-NEXT: [[MUL:%.*]] = fmul float [[EXT_A]], [[EXT_B]]
-; CHECK-INTERLEAVED-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVED-NEXT: [[ADD]] = fadd reassoc contract float [[MUL]], [[ACCUM]]
; CHECK-INTERLEAVED-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-INTERLEAVED-NEXT: [[CMP_1:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
; CHECK-INTERLEAVED-NEXT: br i1 [[CMP_1]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP21:![0-9]+]]
@@ -2445,12 +2445,12 @@ define float @not_fdotp_ext_outside_plan(ptr %a, half %b, i64 %n) #0 {
; CHECK-MAXBW-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 8 x half>, ptr [[TMP4]], align 2
; CHECK-MAXBW-NEXT: [[TMP5:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD]] to <vscale x 8 x float>
; CHECK-MAXBW-NEXT: [[TMP6:%.*]] = fmul <vscale x 8 x float> [[TMP5]], [[BROADCAST_SPLAT]]
-; CHECK-MAXBW-NEXT: [[TMP7]] = fadd reassoc <vscale x 8 x float> [[TMP6]], [[VEC_PHI]]
+; CHECK-MAXBW-NEXT: [[TMP7]] = fadd reassoc contract <vscale x 8 x float> [[TMP6]], [[VEC_PHI]]
; CHECK-MAXBW-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-MAXBW-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-MAXBW-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP20:![0-9]+]]
; CHECK-MAXBW: [[MIDDLE_BLOCK]]:
-; CHECK-MAXBW-NEXT: [[TMP9:%.*]] = call reassoc float @llvm.vector.reduce.fadd.nxv8f32(float -0.000000e+00, <vscale x 8 x float> [[TMP7]])
+; CHECK-MAXBW-NEXT: [[TMP9:%.*]] = call reassoc contract float @llvm.vector.reduce.fadd.nxv8f32(float -0.000000e+00, <vscale x 8 x float> [[TMP7]])
; CHECK-MAXBW-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
; CHECK-MAXBW-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
; CHECK-MAXBW: [[SCALAR_PH]]:
@@ -2464,7 +2464,7 @@ define float @not_fdotp_ext_outside_plan(ptr %a, half %b, i64 %n) #0 {
; CHECK-MAXBW-NEXT: [[LOAD_A:%.*]] = load half, ptr [[GEP_A]], align 2
; CHECK-MAXBW-NEXT: [[EXT_A:%.*]] = fpext half [[LOAD_A]] to float
; CHECK-MAXBW-NEXT: [[MUL:%.*]] = fmul float [[EXT_A]], [[EXT_B]]
-; CHECK-MAXBW-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[ACCUM]]
+; CHECK-MAXBW-NEXT: [[ADD]] = fadd reassoc contract float [[MUL]], [[ACCUM]]
; CHECK-MAXBW-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-MAXBW-NEXT: [[CMP_1:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
; CHECK-MAXBW-NEXT: br i1 [[CMP_1]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP21:![0-9]+]]
@@ -2493,7 +2493,7 @@ define float @not_fdotp_ext_outside_plan(ptr %a, half %b, i64 %n) #0 {
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[WIDE_LOAD:%.*]] = load <8 x half>, ptr [[TMP0]], align 2
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP1:%.*]] = fpext <8 x half> [[WIDE_LOAD]] to <8 x float>
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP2:%.*]] = fmul <8 x float> [[TMP1]], [[BROADCAST_SPLAT]]
-; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP3]] = fadd reassoc <8 x float> [[TMP2]], [[VEC_PHI]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP3]] = fadd reassoc contract <8 x float> [[TMP2]], [[VEC_PHI]]
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-INTERLEAVE1-SVE2P1-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]]
@@ -2512,7 +2512,7 @@ define float @not_fdotp_ext_outside_plan(ptr %a, half %b, i64 %n) #0 {
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[LOAD_A:%.*]] = load half, ptr [[GEP_A]], align 2
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[EXT_A:%.*]] = fpext half [[LOAD_A]] to float
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[MUL:%.*]] = fmul float [[EXT_A]], [[EXT_B]]
-; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[ADD]] = fadd reassoc contract float [[MUL]], [[ACCUM]]
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-INTERLEAVE1-SVE2P1-NEXT: [[CMP_1:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
; CHECK-INTERLEAVE1-SVE2P1-NEXT: br i1 [[CMP_1]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP17:![0-9]+]]
@@ -2533,7 +2533,7 @@ for.body: ; preds = %for.body.lr.ph, %fo
%load.a = load half, ptr %gep.a, align 2
%ext.a = fpext half %load.a to float
%mul = fmul float %ext.a, %ext.b
- %add = fadd reassoc float %mul, %accum
+ %add = fadd reassoc contract float %mul, %accum
%iv.next = add nuw nsw i64 %iv, 1
%cmp.1 = icmp eq i64 %iv.next, %n
br i1 %cmp.1, label %exit, label %for.body
@@ -2542,3 +2542,199 @@ exit: ; preds = %for.cond.cleanup.loopexit, %ent
%result = phi float [ %add, %for.body ]
ret float %result
}
+
+define float @fdotp_f16_f32_nocontract(ptr %a, ptr %b) #0 {
+; CHECK-INTERLEAVE1-LABEL: define float @fdotp_f16_f32_nocontract(
+; CHECK-INTERLEAVE1-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
+; CHECK-INTERLEAVE1-NEXT: [[ENTRY:.*]]:
+; CHECK-INTERLEAVE1-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVE1-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 3
+; CHECK-INTERLEAVE1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK-INTERLEAVE1: [[VECTOR_PH]]:
+; CHECK-INTERLEAVE1-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVE1-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 8
+; CHECK-INTERLEAVE1-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
+; CHECK-INTERLEAVE1-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
+; CHECK-INTERLEAVE1-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-INTERLEAVE1: [[VECTOR_BODY]]:
+; CHECK-INTERLEAVE1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 8 x float> [ insertelement (<vscale x 8 x float> splat (float -0.000000e+00), float 0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[TMP9:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[TMP4:%.*]] = getelementptr half, ptr [[A]], i64 [[INDEX]]
+; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 8 x half>, ptr [[TMP4]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP5:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD]] to <vscale x 8 x float>
+; CHECK-INTERLEAVE1-NEXT: [[TMP6:%.*]] = getelementptr half, ptr [[B]], i64 [[INDEX]]
+; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 8 x half>, ptr [[TMP6]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[TMP7:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD1]] to <vscale x 8 x float>
+; CHECK-INTERLEAVE1-NEXT: [[TMP8:%.*]] = fmul <vscale x 8 x float> [[TMP7]], [[TMP5]]
+; CHECK-INTERLEAVE1-NEXT: [[TMP9]] = fadd reassoc <vscale x 8 x float> [[TMP8]], [[VEC_PHI]]
+; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
+; CHECK-INTERLEAVE1-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP22:![0-9]+]]
+; CHECK-INTERLEAVE1: [[MIDDLE_BLOCK]]:
+; CHECK-INTERLEAVE1-NEXT: [[TMP11:%.*]] = call reassoc float @llvm.vector.reduce.fadd.nxv8f32(float -0.000000e+00, <vscale x 8 x float> [[TMP9]])
+; CHECK-INTERLEAVE1-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
+; CHECK-INTERLEAVE1-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-INTERLEAVE1: [[SCALAR_PH]]:
+; CHECK-INTERLEAVE1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP11]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
+; CHECK-INTERLEAVE1-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-INTERLEAVE1: [[FOR_BODY]]:
+; CHECK-INTERLEAVE1-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[ACCUM:%.*]] = phi float [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVE1-NEXT: [[GEP_A:%.*]] = getelementptr half, ptr [[A]], i64 [[IV]]
+; CHECK-INTERLEAVE1-NEXT: [[LOAD_A:%.*]] = load half, ptr [[GEP_A]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[EXT_A:%.*]] = fpext half [[LOAD_A]] to float
+; CHECK-INTERLEAVE1-NEXT: [[GEP_B:%.*]] = getelementptr half, ptr [[B]], i64 [[IV]]
+; CHECK-INTERLEAVE1-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
+; CHECK-INTERLEAVE1-NEXT: [[EXT_B:%.*]] = fpext half [[LOAD_B]] to float
+; CHECK-INTERLEAVE1-NEXT: [[MUL:%.*]] = fmul float [[EXT_B]], [[EXT_A]]
+; CHECK-INTERLEAVE1-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVE1-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-INTERLEAVE1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
+; CHECK-INTERLEAVE1-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP23:![0-9]+]]
+; CHECK-INTERLEAVE1: [[FOR_EXIT]]:
+; CHECK-INTERLEAVE1-NEXT: [[ADD_LCSSA:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP11]], %[[MIDDLE_BLOCK]] ]
+; CHECK-INTERLEAVE1-NEXT: ret float [[ADD_LCSSA]]
+;
+; CHECK-INTERLEAVED-LABEL: define float @fdotp_f16_f32_nocontract(
+; CHECK-INTERLEAVED-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
+; CHECK-INTERLEAVED-NEXT: [[ENTRY:.*]]:
+; CHECK-INTERLEAVED-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVED-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 4
+; CHECK-INTERLEAVED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK-INTERLEAVED: [[VECTOR_PH]]:
+; CHECK-INTERLEAVED-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVED-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 16
+; CHECK-INTERLEAVED-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
+; CHECK-INTERLEAVED-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
+; CHECK-INTERLEAVED-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-INTERLEAVED: [[VECTOR_BODY]]:
+; CHECK-INTERLEAVED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 8 x float> [ insertelement (<vscale x 8 x float> splat (float -0.000000e+00), float 0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[TMP18:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[VEC_PHI1:%.*]] = phi <vscale x 8 x float> [ splat (float -0.000000e+00), %[[VECTOR_PH]] ], [ [[TMP19:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[TMP4:%.*]] = getelementptr half, ptr [[A]], i64 [[INDEX]]
+; CHECK-INTERLEAVED-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVED-NEXT: [[TMP6:%.*]] = shl nuw i64 [[TMP5]], 3
+; CHECK-INTERLEAVED-NEXT: [[TMP7:%.*]] = getelementptr half, ptr [[TMP4]], i64 [[TMP6]]
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 8 x half>, ptr [[TMP4]], align 1
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD2:%.*]] = load <vscale x 8 x half>, ptr [[TMP7]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP8:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD]] to <vscale x 8 x float>
+; CHECK-INTERLEAVED-NEXT: [[TMP9:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD2]] to <vscale x 8 x float>
+; CHECK-INTERLEAVED-NEXT: [[TMP10:%.*]] = getelementptr half, ptr [[B]], i64 [[INDEX]]
+; CHECK-INTERLEAVED-NEXT: [[TMP11:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-INTERLEAVED-NEXT: [[TMP12:%.*]] = shl nuw i64 [[TMP11]], 3
+; CHECK-INTERLEAVED-NEXT: [[TMP13:%.*]] = getelementptr half, ptr [[TMP10]], i64 [[TMP12]]
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD3:%.*]] = load <vscale x 8 x half>, ptr [[TMP10]], align 1
+; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD4:%.*]] = load <vscale x 8 x half>, ptr [[TMP13]], align 1
+; CHECK-INTERLEAVED-NEXT: [[TMP14:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD3]] to <vscale x 8 x float>
+; CHECK-INTERLEAVED-NEXT: [[TMP15:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD4]] to <vscale x 8 x float>
+; CHECK-INTERLEAVED-NEXT: [[TMP16:%.*]] = fmul <vscale x 8 x float> [[TMP14]], [[TMP8]]
+; CHECK-INTERLEAVED-NEXT: [[TMP17:%.*]] = fmul <vscale x 8 x float> [[TMP15]], [[TMP9]]
+; CHECK-INTERLEAVED-NEXT: [[TMP18]] = fadd reassoc <vscale x 8 x float> [[TMP16]], [[VEC_PHI]]
+; CHECK-INTERLEAVED-NEXT: [[TMP19]] = fadd reassoc <vscale x 8 x float> [[TMP17]], [[VEC_PHI1]]
+; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
+; CHECK-INTERLEAVED-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[TMP20]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP22:![0-9]+]]
+; CHECK-INTERLEAVED: [[MIDDLE_BLOCK]]:
+; CHECK-INTERLEAVED-NEXT: [[BIN_RDX:%.*]] = fadd reassoc <vscale x 8 x float> [[TMP19]], [[TMP18]]
+; CHECK-INTERLEAVED-NEXT: [[TMP21:%.*]] = call reassoc float @llvm.vector.reduce.fadd.nxv8f32(float -0.000000e+00, <vscale x 8 x float> [[BIN_RDX]])
+; CHECK-INTERLEAVED-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
+; CHECK-INTERLEAVED-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-INTERLEAVED: [[SCALAR_PH]]:
+; CHECK-INTERLEAVED-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-INTERLEAVED-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP21]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
+; CHECK-INTERLEAVED-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-INTERLEAVED: [[FOR_BODY]]:
+; CHECK-INTERLEAVED-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[ACCUM:%.*]] = phi float [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[FOR_BODY]] ]
+; CHECK-INTERLEAVED-NEXT: [[GEP_A:%.*]] = getelementptr half, ptr [[A]], i64 [[IV]]
+; CHECK-INTERLEAVED-NEXT: [[LOAD_A:%.*]] = load half, ptr [[GEP_A]], align 1
+; CHECK-INTERLEAVED-NEXT: [[EXT_A:%.*]] = fpext half [[LOAD_A]] to float
+; CHECK-INTERLEAVED-NEXT: [[GEP_B:%.*]] = getelementptr half, ptr [[B]], i64 [[IV]]
+; CHECK-INTERLEAVED-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
+; CHECK-INTERLEAVED-NEXT: [[EXT_B:%.*]] = fpext half [[LOAD_B]] to float
+; CHECK-INTERLEAVED-NEXT: [[MUL:%.*]] = fmul float [[EXT_B]], [[EXT_A]]
+; CHECK-INTERLEAVED-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[ACCUM]]
+; CHECK-INTERLEAVED-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-INTERLEAVED-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
+; CHECK-INTERLEAVED-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP23:![0-9]+]]
+; CHECK-INTERLEAVED: [[FOR_EXIT]]:
+; CHECK-INTERLEAVED-NEXT: [[ADD_LCSSA:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP21]], %[[MIDDLE_BLOCK]] ]
+; CHECK-INTERLEAVED-NEXT: ret float [[ADD_LCSSA]]
+;
+; CHECK-MAXBW-LABEL: define float @fdotp_f16_f32_nocontract(
+; CHECK-MAXBW-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {
+; CHECK-MAXBW-NEXT: [[ENTRY:.*]]:
+; CHECK-MAXBW-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-MAXBW-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 3
+; CHECK-MAXBW-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
+; CHECK-MAXBW-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK-MAXBW: [[VECTOR_PH]]:
+; CHECK-MAXBW-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-MAXBW-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 8
+; CHECK-MAXBW-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
+; CHECK-MAXBW-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
+; CHECK-MAXBW-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-MAXBW: [[VECTOR_BODY]]:
+; CHECK-MAXBW-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 8 x float> [ insertelement (<vscale x 8 x float> splat (float -0.000000e+00), float 0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[TMP9:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[TMP4:%.*]] = getelementptr half, ptr [[A]], i64 [[INDEX]]
+; CHECK-MAXBW-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 8 x half>, ptr [[TMP4]], align 1
+; CHECK-MAXBW-NEXT: [[TMP5:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD]] to <vscale x 8 x float>
+; CHECK-MAXBW-NEXT: [[TMP6:%.*]] = getelementptr half, ptr [[B]], i64 [[INDEX]]
+; CHECK-MAXBW-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 8 x half>, ptr [[TMP6]], align 1
+; CHECK-MAXBW-NEXT: [[TMP7:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD1]] to <vscale x 8 x float>
+; CHECK-MAXBW-NEXT: [[TMP8:%.*]] = fmul <vscale x 8 x float> [[TMP7]], [[TMP5]]
+; CHECK-MAXBW-NEXT: [[TMP9]] = fadd reassoc <vscale x 8 x float> [[TMP8]], [[VEC_PHI]]
+; CHECK-MAXBW-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
+; CHECK-MAXBW-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-MAXBW-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP22:![0-9]+]]
+; CHECK-MAXBW: [[MIDDLE_BLOCK]]:
+; CHECK-MAXBW-NEXT: [[TMP11:%.*]] = call reassoc float @llvm.vector.reduce.fadd.nxv8f32(float -0.000000e+00, <vscale x 8 x float> [[TMP9]])
+; CHECK-MAXBW-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
+; CHECK-MAXBW-NEXT: br i1 [[CMP_N]], label %[[FOR_EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK-MAXBW: [[SCALAR_PH]]:
+; CHECK-MAXBW-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-MAXBW-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP11]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
+; CHECK-MAXBW-NEXT: br label %[[FOR_BODY:.*]]
+; CHECK-MAXBW: [[FOR_BODY]]:
+; CHECK-MAXBW-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[ACCUM:%.*]] = phi float [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[ADD:%.*]], %[[FOR_BODY]] ]
+; CHECK-MAXBW-NEXT: [[GEP_A:%.*]] = getelementptr half, ptr [[A]], i64 [[IV]]
+; CHECK-MAXBW-NEXT: [[LOAD_A:%.*]] = load half, ptr [[GEP_A]], align 1
+; CHECK-MAXBW-NEXT: [[EXT_A:%.*]] = fpext half [[LOAD_A]] to float
+; CHECK-MAXBW-NEXT: [[GEP_B:%.*]] = getelementptr half, ptr [[B]], i64 [[IV]]
+; CHECK-MAXBW-NEXT: [[LOAD_B:%.*]] = load half, ptr [[GEP_B]], align 1
+; CHECK-MAXBW-NEXT: [[EXT_B:%.*]] = fpext half [[LOAD_B]] to float
+; CHECK-MAXBW-NEXT: [[MUL:%.*]] = fmul float [[EXT_B]], [[EXT_A]]
+; CHECK-MAXBW-NEXT: [[ADD]] = fadd reassoc float [[MUL]], [[ACCUM]]
+; CHECK-MAXBW-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-MAXBW-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
+; CHECK-MAXBW-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP23:![0-9]+]]
+; CHECK-MAXBW: [[FOR_EXIT]]:
+; CHECK-MAXBW-NEXT: [[ADD_LCSSA:%.*]] = phi float [ [[ADD]], %[[FOR_BODY]] ], [ [[TMP11]], %[[MIDDLE_BLOCK]] ]
+; CHECK-MAXBW-NEXT: ret float [[ADD_LCSSA]]
+;
+entry:
+ br label %for.body
+
+for.body: ; preds = %for.body, %entry
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+ %accum = phi float [ 0.0, %entry ], [ %add, %for.body ]
+ %gep.a = getelementptr half, ptr %a, i64 %iv
+ %load.a = load half, ptr %gep.a, align 1
+ %ext.a = fpext half %load.a to float
+ %gep.b = getelementptr half, ptr %b, i64 %iv
+ %load.b = load half, ptr %gep.b, align 1
+ %ext.b = fpext half %load.b to float
+ %mul = fmul float %ext.b, %ext.a
+ %add = fadd reassoc float %mul, %accum
+ %iv.next = add i64 %iv, 1
+ %exitcond.not = icmp eq i64 %iv.next, 1024
+ br i1 %exitcond.not, label %for.exit, label %for.body
+
+for.exit: ; preds = %for.body
+ ret float %add
+}
>From 49fe53f058f7cf9e4c724735355ef0fae2d0aa00 Mon Sep 17 00:00:00 2001
From: Damian Heaton <Damian.Heaton at arm.com>
Date: Thu, 11 Dec 2025 11:39:02 +0000
Subject: [PATCH 9/9] Use VPExpressionRecipe handling for widening and fix
building on WASM/RISC-V
---
.../Target/RISCV/RISCVTargetTransformInfo.cpp | 4 +-
.../Target/RISCV/RISCVTargetTransformInfo.h | 3 +-
.../WebAssemblyTargetTransformInfo.cpp | 2 +-
.../WebAssemblyTargetTransformInfo.h | 3 +-
.../Transforms/Vectorize/LoopVectorize.cpp | 28 +-------
.../Transforms/Vectorize/VPlanPatternMatch.h | 5 ++
.../lib/Transforms/Vectorize/VPlanRecipes.cpp | 66 +++----------------
.../Transforms/Vectorize/VPlanTransforms.cpp | 27 +++++++-
.../AArch64/partial-reduce-fdot-product.ll | 36 +++++-----
9 files changed, 65 insertions(+), 109 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 4788a428d7e64..fa54ceb195a8d 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -336,7 +336,9 @@ InstructionCost RISCVTTIImpl::getPartialReductionCost(
unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType,
ElementCount VF, TTI::PartialReductionExtendKind OpAExtend,
TTI::PartialReductionExtendKind OpBExtend, std::optional<unsigned> BinOp,
- TTI::TargetCostKind CostKind) const {
+ TTI::TargetCostKind CostKind, std::optional<FastMathFlags> FMF) const {
+ if (Opcode == Instruction::FAdd)
+ return InstructionCost::getInvalid();
// zve32x is broken for partial_reduce_umla, but let's make sure we
// don't generate them.
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
index 5efa330b3ad71..11367c0c60041 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -104,7 +104,8 @@ class RISCVTTIImpl final : public BasicTTIImplBase<RISCVTTIImpl> {
unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType,
ElementCount VF, TTI::PartialReductionExtendKind OpAExtend,
TTI::PartialReductionExtendKind OpBExtend, std::optional<unsigned> BinOp,
- TTI::TargetCostKind CostKind) const override;
+ TTI::TargetCostKind CostKind,
+ std::optional<FastMathFlags> FMF) const override;
bool shouldExpandReduction(const IntrinsicInst *II) const override;
bool supportsScalableVectors() const override {
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
index 70f7b889551a4..db3ce8ac950bc 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
@@ -372,7 +372,7 @@ InstructionCost WebAssemblyTTIImpl::getPartialReductionCost(
unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType,
ElementCount VF, TTI::PartialReductionExtendKind OpAExtend,
TTI::PartialReductionExtendKind OpBExtend, std::optional<unsigned> BinOp,
- TTI::TargetCostKind CostKind) const {
+ TTI::TargetCostKind CostKind, std::optional<FastMathFlags> FMF) const {
InstructionCost Invalid = InstructionCost::getInvalid();
if (!VF.isFixed() || !ST->hasSIMD128())
return Invalid;
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
index 4146c0ec6ab07..2f644ac63e261 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
@@ -94,7 +94,8 @@ class WebAssemblyTTIImpl final : public BasicTTIImplBase<WebAssemblyTTIImpl> {
unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType,
ElementCount VF, TTI::PartialReductionExtendKind OpAExtend,
TTI::PartialReductionExtendKind OpBExtend, std::optional<unsigned> BinOp,
- TTI::TargetCostKind CostKind) const override;
+ TTI::TargetCostKind CostKind,
+ std::optional<FastMathFlags> FMF) const override;
TTI::ReductionShuffle
getPreferredExpandedReductionShuffle(const IntrinsicInst *II) const override;
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index 672d1ef58e683..31ff1acb55b04 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -6220,33 +6220,7 @@ LoopVectorizationCostModel::getInstructionCost(Instruction *I,
}
[[fallthrough]];
}
- case Instruction::FAdd: {
- // Skip this when falling through from Add/Sub.
- if (I->getOpcode() == Instruction::FAdd) {
- Value *Op0 = I->getOperand(0);
- Value *Op1 = I->getOperand(1);
- if (Op0 && Op1) {
- Instruction *Mul = dyn_cast<Instruction>(Op0);
- if (Mul && Mul->getOpcode() == Instruction::FMul) {
- Value *MulOp0 = Mul->getOperand(0);
- Value *MulOp1 = Mul->getOperand(1);
- if (isa<Instruction>(MulOp0) && isa<Instruction>(MulOp1)) {
- auto Cost = TTI.getPartialReductionCost(
- I->getOpcode(), MulOp0->getType(), MulOp1->getType(),
- VectorTy->getScalarType(), VF,
- TTI.getPartialReductionExtendKind(
- dyn_cast<Instruction>(MulOp0)),
- TTI.getPartialReductionExtendKind(
- dyn_cast<Instruction>(MulOp1)),
- Mul->getOpcode(), CostKind, I->getFastMathFlags());
- if (Cost.isValid())
- return Cost;
- }
- }
- }
- }
- [[fallthrough]];
- }
+ case Instruction::FAdd:
case Instruction::FSub:
case Instruction::Mul:
case Instruction::FMul:
diff --git a/llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h b/llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
index 49858bf47b93c..ec99b23d64027 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
+++ b/llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
@@ -478,6 +478,11 @@ inline AllRecipe_match<Instruction::SExt, Op0_t> m_SExt(const Op0_t &Op0) {
return m_Unary<Instruction::SExt, Op0_t>(Op0);
}
+template <typename Op0_t>
+inline AllRecipe_match<Instruction::FPExt, Op0_t> m_FPExt(const Op0_t &Op0) {
+ return m_Unary<Instruction::FPExt, Op0_t>(Op0);
+}
+
template <typename Op0_t>
inline match_combine_or<AllRecipe_match<Instruction::ZExt, Op0_t>,
AllRecipe_match<Instruction::SExt, Op0_t>>
diff --git a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
index fc3a52dc4ac81..8e986eb22f682 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
@@ -2707,60 +2707,12 @@ InstructionCost VPReductionRecipe::computeCost(ElementCount VF,
CondCost = Ctx.TTI.getCmpSelInstrCost(Instruction::Select, VectorTy,
CondTy, Pred, Ctx.CostKind);
}
- if (!match(getVecOp(), m_FMul(m_VPValue(), m_VPValue()))) {
- auto *PhiType = Ctx.Types.inferScalarType(getChainOp());
- auto *InputType = Ctx.Types.inferScalarType(getVecOp());
- return CondCost + Ctx.TTI.getPartialReductionCost(
- Opcode, InputType, InputType, PhiType, VF,
- TTI::PR_None, TTI::PR_None, {}, Ctx.CostKind,
- OptionalFMF);
- }
-
- VPRecipeBase *OpR = getVecOp()->getDefiningRecipe();
- Type *InputTypeA = nullptr, *InputTypeB = nullptr;
- TTI::PartialReductionExtendKind ExtAType = TTI::PR_None,
- ExtBType = TTI::PR_None;
-
- auto GetExtendKind = [](VPRecipeBase *R) {
- if (!R)
- return TTI::PR_None;
- auto *WidenCastR = dyn_cast<VPWidenCastRecipe>(R);
- if (!WidenCastR)
- return TTI::PR_None;
- if (WidenCastR->getOpcode() == Instruction::CastOps::ZExt)
- return TTI::PR_ZeroExtend;
- if (WidenCastR->getOpcode() == Instruction::CastOps::SExt)
- return TTI::PR_SignExtend;
- if (WidenCastR->getOpcode() == Instruction::CastOps::FPExt)
- return TTI::PR_FPExtend;
- return TTI::PR_None;
- };
-
- if (auto Widen = dyn_cast<VPWidenRecipe>(OpR)) {
- unsigned WidenOpcode = Widen->getOpcode();
- VPRecipeBase *ExtAR = Widen->getOperand(0)->getDefiningRecipe();
- VPRecipeBase *ExtBR = Widen->getOperand(1)->getDefiningRecipe();
- InputTypeA = Ctx.Types.inferScalarType(ExtAR ? ExtAR->getOperand(0)
- : Widen->getOperand(0));
- InputTypeB = Ctx.Types.inferScalarType(ExtBR ? ExtBR->getOperand(0)
- : Widen->getOperand(1));
- ExtAType = GetExtendKind(ExtAR);
- ExtBType = GetExtendKind(ExtBR);
-
- using namespace VPlanPatternMatch;
- const APInt *C;
- if (!ExtBR && match(Widen->getOperand(1), m_APInt(C)) &&
- canConstantBeExtended(C, InputTypeA, ExtAType)) {
- InputTypeB = InputTypeA;
- ExtBType = ExtAType;
- }
-
- auto *PhiType = Ctx.Types.inferScalarType(getOperand(1));
- return CondCost + Ctx.TTI.getPartialReductionCost(
- Opcode, InputTypeA, InputTypeB, PhiType, VF,
- ExtAType, ExtBType, WidenOpcode, Ctx.CostKind,
- OptionalFMF);
- }
+ auto *PhiType = Ctx.Types.inferScalarType(getChainOp());
+ auto *InputType = Ctx.Types.inferScalarType(getVecOp());
+ return CondCost + Ctx.TTI.getPartialReductionCost(
+ Opcode, InputType, InputType, PhiType, VF,
+ TTI::PR_None, TTI::PR_None, {}, Ctx.CostKind,
+ OptionalFMF);
}
// TODO: Support any-of reductions.
@@ -2859,8 +2811,6 @@ InstructionCost VPExpressionRecipe::computeCost(ElementCount VF,
Type *RedTy = Ctx.Types.inferScalarType(this);
auto *SrcVecTy = cast<VectorType>(
toVectorTy(Ctx.Types.inferScalarType(getOperand(0)), VF));
- assert(RedTy->isIntegerTy() &&
- "VPExpressionRecipe only supports integer types currently.");
unsigned Opcode = RecurrenceDescriptor::getOpcode(
cast<VPReductionRecipe>(ExpressionRecipes.back())->getRecurrenceKind());
switch (ExpressionType) {
@@ -2903,7 +2853,9 @@ InstructionCost VPExpressionRecipe::computeCost(ElementCount VF,
Ext0R->getOpcode()),
TargetTransformInfo::getPartialReductionExtendKind(
Ext1R->getOpcode()),
- Mul->getOpcode(), Ctx.CostKind, std::nullopt);
+ Mul->getOpcode(), Ctx.CostKind,
+ RedTy->isFloatingPointTy() ? std::optional{RedR->getFastMathFlags()}
+ : std::nullopt);
}
return Ctx.TTI.getMulAccReductionCost(
cast<VPWidenCastRecipe>(ExpressionRecipes.front())->getOpcode() ==
diff --git a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
index 64891e2cb4ca5..eb32766ee00e6 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
@@ -3833,11 +3833,13 @@ tryToMatchAndCreateExtendedReduction(VPReductionRecipe *Red, VPCostContext &Ctx,
/// reduce.add(mul(...)),
/// reduce.add(mul(ext(A), ext(B))),
/// reduce.add(ext(mul(ext(A), ext(B)))).
+/// reduce.fadd(fmul(ext(A), ext(B)))
static VPExpressionRecipe *
tryToMatchAndCreateMulAccumulateReduction(VPReductionRecipe *Red,
VPCostContext &Ctx, VFRange &Range) {
unsigned Opcode = RecurrenceDescriptor::getOpcode(Red->getRecurrenceKind());
- if (Opcode != Instruction::Add && Opcode != Instruction::Sub)
+ if (Opcode != Instruction::Add && Opcode != Instruction::Sub &&
+ Opcode != Instruction::FAdd)
return nullptr;
Type *RedTy = Ctx.Types.inferScalarType(Red);
@@ -3866,7 +3868,10 @@ tryToMatchAndCreateMulAccumulateReduction(VPReductionRecipe *Red,
Ext1 ? TargetTransformInfo::getPartialReductionExtendKind(
Ext1->getOpcode())
: TargetTransformInfo::PR_None,
- Mul->getOpcode(), CostKind, std::nullopt);
+ Mul->getOpcode(), CostKind,
+ RedTy->isFloatingPointTy()
+ ? std::optional{Red->getFastMathFlags()}
+ : std::nullopt);
} else {
// Only partial reductions support mixed extends at the moment.
if (Ext0 && Ext1 && Ext0->getOpcode() != Ext1->getOpcode())
@@ -3935,7 +3940,23 @@ tryToMatchAndCreateMulAccumulateReduction(VPReductionRecipe *Red,
Mul->setOperand(1, ExtB);
};
- // Try to match reduce.add(mul(...)).
+ // Try to match reduce.add(fmul(...)).
+ if (match(VecOp, m_FMul(m_VPValue(A), m_VPValue(B)))) {
+ auto *RecipeA = dyn_cast_if_present<VPWidenCastRecipe>(A);
+ auto *RecipeB = dyn_cast_if_present<VPWidenCastRecipe>(B);
+ auto *FMul = dyn_cast<VPWidenRecipe>(VecOp);
+
+ // Match reduce.fadd(fmul(ext, ext)).
+ if (FMul && RecipeA && RecipeB && match(RecipeA, m_FPExt(m_VPValue())) &&
+ match(RecipeB, m_FPExt(m_VPValue())) &&
+ IsMulAccValidAndClampRange(FMul, RecipeA, RecipeB, nullptr)) {
+ return new VPExpressionRecipe(RecipeA, RecipeB, FMul, Red);
+ }
+ }
+ if (Opcode == Instruction::FAdd)
+ return nullptr;
+
+ // Try to match reduce.add(mul(...)) or reduce.add(fmul(...)).
if (match(VecOp, m_Mul(m_VPValue(A), m_VPValue(B)))) {
auto *RecipeA = dyn_cast_if_present<VPWidenCastRecipe>(A);
auto *RecipeB = dyn_cast_if_present<VPWidenCastRecipe>(B);
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fdot-product.ll b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fdot-product.ll
index 91a22a2229318..dcfe3e0adc64d 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fdot-product.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-fdot-product.ll
@@ -25,10 +25,10 @@ define float @fdotp_f16_f32(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x float> [ insertelement (<vscale x 4 x float> splat (float -0.000000e+00), float 0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], %[[VECTOR_BODY]] ]
; CHECK-INTERLEAVE1-NEXT: [[TMP0:%.*]] = getelementptr half, ptr [[A]], i64 [[INDEX]]
; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 8 x half>, ptr [[TMP0]], align 1
-; CHECK-INTERLEAVE1-NEXT: [[TMP11:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD]] to <vscale x 8 x float>
; CHECK-INTERLEAVE1-NEXT: [[TMP2:%.*]] = getelementptr half, ptr [[B]], i64 [[INDEX]]
; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 8 x half>, ptr [[TMP2]], align 1
; CHECK-INTERLEAVE1-NEXT: [[TMP7:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD1]] to <vscale x 8 x float>
+; CHECK-INTERLEAVE1-NEXT: [[TMP11:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD]] to <vscale x 8 x float>
; CHECK-INTERLEAVE1-NEXT: [[TMP8:%.*]] = fmul <vscale x 8 x float> [[TMP7]], [[TMP11]]
; CHECK-INTERLEAVE1-NEXT: [[PARTIAL_REDUCE]] = call reassoc contract <vscale x 4 x float> @llvm.vector.partial.reduce.fadd.nxv4f32.nxv8f32(<vscale x 4 x float> [[VEC_PHI]], <vscale x 8 x float> [[TMP8]])
; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT1]] = add nuw i64 [[INDEX]], [[TMP3]]
@@ -83,8 +83,6 @@ define float @fdotp_f16_f32(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVED-NEXT: [[TMP7:%.*]] = getelementptr half, ptr [[TMP0]], i64 [[TMP6]]
; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 8 x half>, ptr [[TMP0]], align 1
; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD2:%.*]] = load <vscale x 8 x half>, ptr [[TMP7]], align 1
-; CHECK-INTERLEAVED-NEXT: [[TMP8:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD]] to <vscale x 8 x float>
-; CHECK-INTERLEAVED-NEXT: [[TMP9:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD2]] to <vscale x 8 x float>
; CHECK-INTERLEAVED-NEXT: [[TMP4:%.*]] = getelementptr half, ptr [[B]], i64 [[INDEX]]
; CHECK-INTERLEAVED-NEXT: [[TMP20:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-INTERLEAVED-NEXT: [[TMP21:%.*]] = shl nuw i64 [[TMP20]], 3
@@ -92,10 +90,12 @@ define float @fdotp_f16_f32(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD3:%.*]] = load <vscale x 8 x half>, ptr [[TMP4]], align 1
; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD4:%.*]] = load <vscale x 8 x half>, ptr [[TMP13]], align 1
; CHECK-INTERLEAVED-NEXT: [[TMP14:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD3]] to <vscale x 8 x float>
-; CHECK-INTERLEAVED-NEXT: [[TMP15:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD4]] to <vscale x 8 x float>
+; CHECK-INTERLEAVED-NEXT: [[TMP8:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD]] to <vscale x 8 x float>
; CHECK-INTERLEAVED-NEXT: [[TMP16:%.*]] = fmul <vscale x 8 x float> [[TMP14]], [[TMP8]]
-; CHECK-INTERLEAVED-NEXT: [[TMP17:%.*]] = fmul <vscale x 8 x float> [[TMP15]], [[TMP9]]
; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE]] = call reassoc contract <vscale x 4 x float> @llvm.vector.partial.reduce.fadd.nxv4f32.nxv8f32(<vscale x 4 x float> [[VEC_PHI]], <vscale x 8 x float> [[TMP16]])
+; CHECK-INTERLEAVED-NEXT: [[TMP15:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD4]] to <vscale x 8 x float>
+; CHECK-INTERLEAVED-NEXT: [[TMP22:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD2]] to <vscale x 8 x float>
+; CHECK-INTERLEAVED-NEXT: [[TMP17:%.*]] = fmul <vscale x 8 x float> [[TMP15]], [[TMP22]]
; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE5]] = call reassoc contract <vscale x 4 x float> @llvm.vector.partial.reduce.fadd.nxv4f32.nxv8f32(<vscale x 4 x float> [[VEC_PHI1]], <vscale x 8 x float> [[TMP17]])
; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT1]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-INTERLEAVED-NEXT: [[TMP18:%.*]] = icmp eq i64 [[INDEX_NEXT1]], [[N_VEC]]
@@ -145,10 +145,10 @@ define float @fdotp_f16_f32(ptr %a, ptr %b) #0 {
; CHECK-MAXBW-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 4 x float> [ insertelement (<vscale x 4 x float> splat (float -0.000000e+00), float 0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], %[[VECTOR_BODY]] ]
; CHECK-MAXBW-NEXT: [[TMP4:%.*]] = getelementptr half, ptr [[A]], i64 [[INDEX]]
; CHECK-MAXBW-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 8 x half>, ptr [[TMP4]], align 1
-; CHECK-MAXBW-NEXT: [[TMP5:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD]] to <vscale x 8 x float>
; CHECK-MAXBW-NEXT: [[TMP6:%.*]] = getelementptr half, ptr [[B]], i64 [[INDEX]]
; CHECK-MAXBW-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 8 x half>, ptr [[TMP6]], align 1
; CHECK-MAXBW-NEXT: [[TMP7:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD1]] to <vscale x 8 x float>
+; CHECK-MAXBW-NEXT: [[TMP5:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD]] to <vscale x 8 x float>
; CHECK-MAXBW-NEXT: [[TMP8:%.*]] = fmul <vscale x 8 x float> [[TMP7]], [[TMP5]]
; CHECK-MAXBW-NEXT: [[PARTIAL_REDUCE]] = call reassoc contract <vscale x 4 x float> @llvm.vector.partial.reduce.fadd.nxv4f32.nxv8f32(<vscale x 4 x float> [[VEC_PHI]], <vscale x 8 x float> [[TMP8]])
; CHECK-MAXBW-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
@@ -246,10 +246,10 @@ define double @fdotp_f16_f64(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 2 x double> [ insertelement (<vscale x 2 x double> splat (double -0.000000e+00), double 0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], %[[VECTOR_BODY]] ]
; CHECK-INTERLEAVE1-NEXT: [[TMP0:%.*]] = getelementptr half, ptr [[A]], i64 [[INDEX]]
; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 8 x half>, ptr [[TMP0]], align 1
-; CHECK-INTERLEAVE1-NEXT: [[TMP12:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD]] to <vscale x 8 x double>
; CHECK-INTERLEAVE1-NEXT: [[TMP2:%.*]] = getelementptr half, ptr [[B]], i64 [[INDEX]]
; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 8 x half>, ptr [[TMP2]], align 1
; CHECK-INTERLEAVE1-NEXT: [[TMP7:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD1]] to <vscale x 8 x double>
+; CHECK-INTERLEAVE1-NEXT: [[TMP12:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD]] to <vscale x 8 x double>
; CHECK-INTERLEAVE1-NEXT: [[TMP8:%.*]] = fmul <vscale x 8 x double> [[TMP7]], [[TMP12]]
; CHECK-INTERLEAVE1-NEXT: [[PARTIAL_REDUCE]] = call reassoc contract <vscale x 2 x double> @llvm.vector.partial.reduce.fadd.nxv2f64.nxv8f64(<vscale x 2 x double> [[VEC_PHI]], <vscale x 8 x double> [[TMP8]])
; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT1]] = add nuw i64 [[INDEX]], [[TMP3]]
@@ -304,8 +304,6 @@ define double @fdotp_f16_f64(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVED-NEXT: [[TMP7:%.*]] = getelementptr half, ptr [[TMP0]], i64 [[TMP6]]
; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 8 x half>, ptr [[TMP0]], align 1
; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD2:%.*]] = load <vscale x 8 x half>, ptr [[TMP7]], align 1
-; CHECK-INTERLEAVED-NEXT: [[TMP8:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD]] to <vscale x 8 x double>
-; CHECK-INTERLEAVED-NEXT: [[TMP9:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD2]] to <vscale x 8 x double>
; CHECK-INTERLEAVED-NEXT: [[TMP4:%.*]] = getelementptr half, ptr [[B]], i64 [[INDEX]]
; CHECK-INTERLEAVED-NEXT: [[TMP21:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-INTERLEAVED-NEXT: [[TMP12:%.*]] = shl nuw i64 [[TMP21]], 3
@@ -313,10 +311,12 @@ define double @fdotp_f16_f64(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD3:%.*]] = load <vscale x 8 x half>, ptr [[TMP4]], align 1
; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD4:%.*]] = load <vscale x 8 x half>, ptr [[TMP13]], align 1
; CHECK-INTERLEAVED-NEXT: [[TMP14:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD3]] to <vscale x 8 x double>
-; CHECK-INTERLEAVED-NEXT: [[TMP15:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD4]] to <vscale x 8 x double>
+; CHECK-INTERLEAVED-NEXT: [[TMP8:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD]] to <vscale x 8 x double>
; CHECK-INTERLEAVED-NEXT: [[TMP16:%.*]] = fmul <vscale x 8 x double> [[TMP14]], [[TMP8]]
-; CHECK-INTERLEAVED-NEXT: [[TMP17:%.*]] = fmul <vscale x 8 x double> [[TMP15]], [[TMP9]]
; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE]] = call reassoc contract <vscale x 2 x double> @llvm.vector.partial.reduce.fadd.nxv2f64.nxv8f64(<vscale x 2 x double> [[VEC_PHI]], <vscale x 8 x double> [[TMP16]])
+; CHECK-INTERLEAVED-NEXT: [[TMP15:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD4]] to <vscale x 8 x double>
+; CHECK-INTERLEAVED-NEXT: [[TMP22:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD2]] to <vscale x 8 x double>
+; CHECK-INTERLEAVED-NEXT: [[TMP17:%.*]] = fmul <vscale x 8 x double> [[TMP15]], [[TMP22]]
; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE5]] = call reassoc contract <vscale x 2 x double> @llvm.vector.partial.reduce.fadd.nxv2f64.nxv8f64(<vscale x 2 x double> [[VEC_PHI1]], <vscale x 8 x double> [[TMP17]])
; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT1]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-INTERLEAVED-NEXT: [[TMP18:%.*]] = icmp eq i64 [[INDEX_NEXT1]], [[N_VEC]]
@@ -366,10 +366,10 @@ define double @fdotp_f16_f64(ptr %a, ptr %b) #0 {
; CHECK-MAXBW-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 2 x double> [ insertelement (<vscale x 2 x double> splat (double -0.000000e+00), double 0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], %[[VECTOR_BODY]] ]
; CHECK-MAXBW-NEXT: [[TMP4:%.*]] = getelementptr half, ptr [[A]], i64 [[INDEX]]
; CHECK-MAXBW-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 8 x half>, ptr [[TMP4]], align 1
-; CHECK-MAXBW-NEXT: [[TMP5:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD]] to <vscale x 8 x double>
; CHECK-MAXBW-NEXT: [[TMP6:%.*]] = getelementptr half, ptr [[B]], i64 [[INDEX]]
; CHECK-MAXBW-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 8 x half>, ptr [[TMP6]], align 1
; CHECK-MAXBW-NEXT: [[TMP7:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD1]] to <vscale x 8 x double>
+; CHECK-MAXBW-NEXT: [[TMP5:%.*]] = fpext <vscale x 8 x half> [[WIDE_LOAD]] to <vscale x 8 x double>
; CHECK-MAXBW-NEXT: [[TMP8:%.*]] = fmul <vscale x 8 x double> [[TMP7]], [[TMP5]]
; CHECK-MAXBW-NEXT: [[PARTIAL_REDUCE]] = call reassoc contract <vscale x 2 x double> @llvm.vector.partial.reduce.fadd.nxv2f64.nxv8f64(<vscale x 2 x double> [[VEC_PHI]], <vscale x 8 x double> [[TMP8]])
; CHECK-MAXBW-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
@@ -467,10 +467,10 @@ define double @fdotp_f32_f64(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVE1-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 2 x double> [ insertelement (<vscale x 2 x double> splat (double -0.000000e+00), double 0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], %[[VECTOR_BODY]] ]
; CHECK-INTERLEAVE1-NEXT: [[TMP0:%.*]] = getelementptr float, ptr [[A]], i64 [[INDEX]]
; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x float>, ptr [[TMP0]], align 1
-; CHECK-INTERLEAVE1-NEXT: [[TMP12:%.*]] = fpext <vscale x 4 x float> [[WIDE_LOAD]] to <vscale x 4 x double>
; CHECK-INTERLEAVE1-NEXT: [[TMP2:%.*]] = getelementptr float, ptr [[B]], i64 [[INDEX]]
; CHECK-INTERLEAVE1-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 4 x float>, ptr [[TMP2]], align 1
; CHECK-INTERLEAVE1-NEXT: [[TMP7:%.*]] = fpext <vscale x 4 x float> [[WIDE_LOAD1]] to <vscale x 4 x double>
+; CHECK-INTERLEAVE1-NEXT: [[TMP12:%.*]] = fpext <vscale x 4 x float> [[WIDE_LOAD]] to <vscale x 4 x double>
; CHECK-INTERLEAVE1-NEXT: [[TMP8:%.*]] = fmul <vscale x 4 x double> [[TMP7]], [[TMP12]]
; CHECK-INTERLEAVE1-NEXT: [[PARTIAL_REDUCE]] = call reassoc contract <vscale x 2 x double> @llvm.vector.partial.reduce.fadd.nxv2f64.nxv4f64(<vscale x 2 x double> [[VEC_PHI]], <vscale x 4 x double> [[TMP8]])
; CHECK-INTERLEAVE1-NEXT: [[INDEX_NEXT1]] = add nuw i64 [[INDEX]], [[TMP3]]
@@ -525,8 +525,6 @@ define double @fdotp_f32_f64(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVED-NEXT: [[TMP7:%.*]] = getelementptr float, ptr [[TMP0]], i64 [[TMP6]]
; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x float>, ptr [[TMP0]], align 1
; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD2:%.*]] = load <vscale x 4 x float>, ptr [[TMP7]], align 1
-; CHECK-INTERLEAVED-NEXT: [[TMP8:%.*]] = fpext <vscale x 4 x float> [[WIDE_LOAD]] to <vscale x 4 x double>
-; CHECK-INTERLEAVED-NEXT: [[TMP9:%.*]] = fpext <vscale x 4 x float> [[WIDE_LOAD2]] to <vscale x 4 x double>
; CHECK-INTERLEAVED-NEXT: [[TMP4:%.*]] = getelementptr float, ptr [[B]], i64 [[INDEX]]
; CHECK-INTERLEAVED-NEXT: [[TMP21:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-INTERLEAVED-NEXT: [[TMP12:%.*]] = shl nuw i64 [[TMP21]], 2
@@ -534,10 +532,12 @@ define double @fdotp_f32_f64(ptr %a, ptr %b) #0 {
; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD3:%.*]] = load <vscale x 4 x float>, ptr [[TMP4]], align 1
; CHECK-INTERLEAVED-NEXT: [[WIDE_LOAD4:%.*]] = load <vscale x 4 x float>, ptr [[TMP13]], align 1
; CHECK-INTERLEAVED-NEXT: [[TMP14:%.*]] = fpext <vscale x 4 x float> [[WIDE_LOAD3]] to <vscale x 4 x double>
-; CHECK-INTERLEAVED-NEXT: [[TMP15:%.*]] = fpext <vscale x 4 x float> [[WIDE_LOAD4]] to <vscale x 4 x double>
+; CHECK-INTERLEAVED-NEXT: [[TMP8:%.*]] = fpext <vscale x 4 x float> [[WIDE_LOAD]] to <vscale x 4 x double>
; CHECK-INTERLEAVED-NEXT: [[TMP16:%.*]] = fmul <vscale x 4 x double> [[TMP14]], [[TMP8]]
-; CHECK-INTERLEAVED-NEXT: [[TMP17:%.*]] = fmul <vscale x 4 x double> [[TMP15]], [[TMP9]]
; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE]] = call reassoc contract <vscale x 2 x double> @llvm.vector.partial.reduce.fadd.nxv2f64.nxv4f64(<vscale x 2 x double> [[VEC_PHI]], <vscale x 4 x double> [[TMP16]])
+; CHECK-INTERLEAVED-NEXT: [[TMP15:%.*]] = fpext <vscale x 4 x float> [[WIDE_LOAD4]] to <vscale x 4 x double>
+; CHECK-INTERLEAVED-NEXT: [[TMP22:%.*]] = fpext <vscale x 4 x float> [[WIDE_LOAD2]] to <vscale x 4 x double>
+; CHECK-INTERLEAVED-NEXT: [[TMP17:%.*]] = fmul <vscale x 4 x double> [[TMP15]], [[TMP22]]
; CHECK-INTERLEAVED-NEXT: [[PARTIAL_REDUCE5]] = call reassoc contract <vscale x 2 x double> @llvm.vector.partial.reduce.fadd.nxv2f64.nxv4f64(<vscale x 2 x double> [[VEC_PHI1]], <vscale x 4 x double> [[TMP17]])
; CHECK-INTERLEAVED-NEXT: [[INDEX_NEXT1]] = add nuw i64 [[INDEX]], [[TMP3]]
; CHECK-INTERLEAVED-NEXT: [[TMP18:%.*]] = icmp eq i64 [[INDEX_NEXT1]], [[N_VEC]]
@@ -587,10 +587,10 @@ define double @fdotp_f32_f64(ptr %a, ptr %b) #0 {
; CHECK-MAXBW-NEXT: [[VEC_PHI:%.*]] = phi <vscale x 2 x double> [ insertelement (<vscale x 2 x double> splat (double -0.000000e+00), double 0.000000e+00, i32 0), %[[VECTOR_PH]] ], [ [[PARTIAL_REDUCE:%.*]], %[[VECTOR_BODY]] ]
; CHECK-MAXBW-NEXT: [[TMP4:%.*]] = getelementptr float, ptr [[A]], i64 [[INDEX]]
; CHECK-MAXBW-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x float>, ptr [[TMP4]], align 1
-; CHECK-MAXBW-NEXT: [[TMP5:%.*]] = fpext <vscale x 4 x float> [[WIDE_LOAD]] to <vscale x 4 x double>
; CHECK-MAXBW-NEXT: [[TMP6:%.*]] = getelementptr float, ptr [[B]], i64 [[INDEX]]
; CHECK-MAXBW-NEXT: [[WIDE_LOAD1:%.*]] = load <vscale x 4 x float>, ptr [[TMP6]], align 1
; CHECK-MAXBW-NEXT: [[TMP7:%.*]] = fpext <vscale x 4 x float> [[WIDE_LOAD1]] to <vscale x 4 x double>
+; CHECK-MAXBW-NEXT: [[TMP5:%.*]] = fpext <vscale x 4 x float> [[WIDE_LOAD]] to <vscale x 4 x double>
; CHECK-MAXBW-NEXT: [[TMP8:%.*]] = fmul <vscale x 4 x double> [[TMP7]], [[TMP5]]
; CHECK-MAXBW-NEXT: [[PARTIAL_REDUCE]] = call reassoc contract <vscale x 2 x double> @llvm.vector.partial.reduce.fadd.nxv2f64.nxv4f64(<vscale x 2 x double> [[VEC_PHI]], <vscale x 4 x double> [[TMP8]])
; CHECK-MAXBW-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
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