[llvm] SelectionDAG: Support FMINIMUMNUM and FMINIMUM in combineMinNumMaxNumImpl (PR #137449)
YunQiang Su via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 10 23:48:09 PST 2025
https://github.com/wzssyqa updated https://github.com/llvm/llvm-project/pull/137449
>From 1dfda32064fd55b7e5205afcd7e3575c145217ea Mon Sep 17 00:00:00 2001
From: YunQiang Su <yunqiang at isrc.iscas.ac.cn>
Date: Sat, 26 Apr 2025 17:04:18 +0800
Subject: [PATCH 1/6] SelectionDAG: Support FMINIMUMNUM and FMINIMUM in
combineMinNumMaxNumImpl
We also use `isOperationLegal` instead of `isOperationLegalOrCustom`,
as `Custom` implemention of these FMAX/FMIN operation normally much
more expensive than just 2 fcmp operations.
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 32 +-
.../AMDGPU/select-flags-to-fmin-fmax.ll | 42 +-
llvm/test/CodeGen/WebAssembly/f32.ll | 31 +-
llvm/test/CodeGen/WebAssembly/f64.ll | 40 +-
llvm/test/CodeGen/WebAssembly/simd-arith.ll | 460 +++++++-----------
.../test/CodeGen/WebAssembly/vector-reduce.ll | 12 +-
6 files changed, 256 insertions(+), 361 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 282dc4470238d..2ad5d631e94b6 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -11516,15 +11516,24 @@ static SDValue combineMinNumMaxNumImpl(const SDLoc &DL, EVT VT, SDValue LHS,
case ISD::SETLE:
case ISD::SETULT:
case ISD::SETULE: {
- // Since it's known never nan to get here already, either fminnum or
- // fminnum_ieee are OK. Try the ieee version first, since it's fminnum is
- // expanded in terms of it.
+ // Since it's known never nan to get here already, either fminimumnum,
+ // fminimum, fminnum, or fminnum_ieee are OK. Try the ieee version first,
+ // since it's fminnum is expanded in terms of it.
+ unsigned IEEE2019NumOpcode =
+ (LHS == True) ? ISD::FMINIMUMNUM : ISD::FMAXIMUMNUM;
+ if (TLI.isOperationLegal(IEEE2019NumOpcode, VT))
+ return DAG.getNode(IEEE2019NumOpcode, DL, VT, LHS, RHS);
+
+ unsigned IEEE2019Opcode = (LHS == True) ? ISD::FMINIMUM : ISD::FMAXIMUM;
+ if (TLI.isOperationLegal(IEEE2019Opcode, VT))
+ return DAG.getNode(IEEE2019Opcode, DL, VT, LHS, RHS);
+
unsigned IEEEOpcode = (LHS == True) ? ISD::FMINNUM_IEEE : ISD::FMAXNUM_IEEE;
- if (TLI.isOperationLegalOrCustom(IEEEOpcode, VT))
+ if (TLI.isOperationLegal(IEEEOpcode, VT))
return DAG.getNode(IEEEOpcode, DL, VT, LHS, RHS);
unsigned Opcode = (LHS == True) ? ISD::FMINNUM : ISD::FMAXNUM;
- if (TLI.isOperationLegalOrCustom(Opcode, TransformVT))
+ if (TLI.isOperationLegal(Opcode, TransformVT))
return DAG.getNode(Opcode, DL, VT, LHS, RHS);
return SDValue();
}
@@ -11534,12 +11543,21 @@ static SDValue combineMinNumMaxNumImpl(const SDLoc &DL, EVT VT, SDValue LHS,
case ISD::SETGE:
case ISD::SETUGT:
case ISD::SETUGE: {
+ unsigned IEEE2019NumOpcode =
+ (LHS == True) ? ISD::FMAXIMUMNUM : ISD::FMINIMUMNUM;
+ if (TLI.isOperationLegal(IEEE2019NumOpcode, VT))
+ return DAG.getNode(IEEE2019NumOpcode, DL, VT, LHS, RHS);
+
+ unsigned IEEE2019Opcode = (LHS == True) ? ISD::FMAXIMUM : ISD::FMINIMUM;
+ if (TLI.isOperationLegal(IEEE2019Opcode, VT))
+ return DAG.getNode(IEEE2019Opcode, DL, VT, LHS, RHS);
+
unsigned IEEEOpcode = (LHS == True) ? ISD::FMAXNUM_IEEE : ISD::FMINNUM_IEEE;
- if (TLI.isOperationLegalOrCustom(IEEEOpcode, VT))
+ if (TLI.isOperationLegal(IEEEOpcode, VT))
return DAG.getNode(IEEEOpcode, DL, VT, LHS, RHS);
unsigned Opcode = (LHS == True) ? ISD::FMAXNUM : ISD::FMINNUM;
- if (TLI.isOperationLegalOrCustom(Opcode, TransformVT))
+ if (TLI.isOperationLegal(Opcode, TransformVT))
return DAG.getNode(Opcode, DL, VT, LHS, RHS);
return SDValue();
}
diff --git a/llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll b/llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
index f7bd5f8d5bfb4..1fb3eb5c215e7 100644
--- a/llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
@@ -119,7 +119,7 @@ define float @v_test_fmin_legacy_ule_f32_nnan_nsz_flag(float %a, float %b) {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX12-NEXT: v_minimum_f32 v0, v0, v1
; GFX12-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp ule float %a, %b
%val = select nnan nsz i1 %cmp, float %a, float %b
@@ -236,7 +236,7 @@ define float @v_test_fmax_legacy_uge_f32_nnan_nsz_flag(float %a, float %b) {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX12-NEXT: v_maximum_f32 v0, v0, v1
; GFX12-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp uge float %a, %b
%val = select nnan nsz i1 %cmp, float %a, float %b
@@ -693,7 +693,7 @@ define half @v_test_fmin_legacy_ule_f16_nnan_nsz_flag(half %a, half %b) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v1.l
+; GFX12-TRUE16-NEXT: v_minimum_f16 v0.l, v0.l, v1.l
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_test_fmin_legacy_ule_f16_nnan_nsz_flag:
@@ -703,7 +703,7 @@ define half @v_test_fmin_legacy_ule_f16_nnan_nsz_flag(half %a, half %b) {
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-NEXT: v_minimum_f16 v0, v0, v1
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp ule half %a, %b
%val = select nnan nsz i1 %cmp, half %a, half %b
@@ -872,7 +872,7 @@ define half @v_test_fmax_legacy_uge_f16_nnan_nsz_flag(half %a, half %b) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v1.l
+; GFX12-TRUE16-NEXT: v_maximum_f16 v0.l, v0.l, v1.l
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_test_fmax_legacy_uge_f16_nnan_nsz_flag:
@@ -882,7 +882,7 @@ define half @v_test_fmax_legacy_uge_f16_nnan_nsz_flag(half %a, half %b) {
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
+; GFX12-FAKE16-NEXT: v_maximum_f16 v0, v0, v1
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp uge half %a, %b
%val = select nnan nsz i1 %cmp, half %a, half %b
@@ -1122,7 +1122,7 @@ define <2 x half> @v_test_fmin_legacy_ule_v2f16_nnan_nsz_flag(<2 x half> %a, <2
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v1
+; GFX12-NEXT: v_pk_minimum_f16 v0, v0, v1
; GFX12-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp ule <2 x half> %a, %b
%val = select nnan nsz <2 x i1> %cmp, <2 x half> %a, <2 x half> %b
@@ -1362,7 +1362,7 @@ define <2 x half> @v_test_fmax_legacy_uge_v2f16_nnan_nsz_flag(<2 x half> %a, <2
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v1
+; GFX12-NEXT: v_pk_maximum_f16 v0, v0, v1
; GFX12-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp uge <2 x half> %a, %b
%val = select nnan nsz <2 x i1> %cmp, <2 x half> %a, <2 x half> %b
@@ -1692,8 +1692,12 @@ define <4 x half> @v_test_fmin_legacy_ule_v4f16_nnan_nsz_flag(<4 x half> %a, <4
; GFX9-LABEL: v_test_fmin_legacy_ule_v4f16_nnan_nsz_flag:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_pk_max_f16 v2, v2, v2
+; GFX9-NEXT: v_pk_max_f16 v0, v0, v0
; GFX9-NEXT: v_pk_min_f16 v0, v0, v2
-; GFX9-NEXT: v_pk_min_f16 v1, v1, v3
+; GFX9-NEXT: v_pk_max_f16 v2, v3, v3
+; GFX9-NEXT: v_pk_max_f16 v1, v1, v1
+; GFX9-NEXT: v_pk_min_f16 v1, v1, v2
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_test_fmin_legacy_ule_v4f16_nnan_nsz_flag:
@@ -1703,6 +1707,11 @@ define <4 x half> @v_test_fmin_legacy_ule_v4f16_nnan_nsz_flag(<4 x half> %a, <4
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
+; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v0
+; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v3
+; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v2
; GFX12-NEXT: v_pk_min_num_f16 v1, v1, v3
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -2034,8 +2043,12 @@ define <4 x half> @v_test_fmax_legacy_uge_v4f16_nnan_nsz_flag(<4 x half> %a, <4
; GFX9-LABEL: v_test_fmax_legacy_uge_v4f16_nnan_nsz_flag:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_pk_max_f16 v2, v2, v2
+; GFX9-NEXT: v_pk_max_f16 v0, v0, v0
; GFX9-NEXT: v_pk_max_f16 v0, v0, v2
-; GFX9-NEXT: v_pk_max_f16 v1, v1, v3
+; GFX9-NEXT: v_pk_max_f16 v2, v3, v3
+; GFX9-NEXT: v_pk_max_f16 v1, v1, v1
+; GFX9-NEXT: v_pk_max_f16 v1, v1, v2
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_test_fmax_legacy_uge_v4f16_nnan_nsz_flag:
@@ -2045,6 +2058,11 @@ define <4 x half> @v_test_fmax_legacy_uge_v4f16_nnan_nsz_flag(<4 x half> %a, <4
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
+; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v0
+; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v3
+; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v2
; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v3
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -2079,7 +2097,7 @@ define float @v_test_fmin_legacy_uge_f32_nsz_flag__nnan_srcs(float %arg0, float
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_dual_add_f32 v0, v0, v0 :: v_dual_add_f32 v1, v1, v1
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_min_num_f32_e32 v0, v0, v1
+; GFX12-NEXT: v_minimum_f32 v0, v0, v1
; GFX12-NEXT: s_setpc_b64 s[30:31]
%a = fadd nnan float %arg0, %arg0
%b = fadd nnan float %arg1, %arg1
@@ -2114,7 +2132,7 @@ define float @v_test_fmax_legacy_uge_f32_nsz_flag__nnan_srcs(float %arg0, float
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_dual_add_f32 v0, v0, v0 :: v_dual_add_f32 v1, v1, v1
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v1
+; GFX12-NEXT: v_maximum_f32 v0, v0, v1
; GFX12-NEXT: s_setpc_b64 s[30:31]
%a = fadd nnan float %arg0, %arg0
%b = fadd nnan float %arg1, %arg1
diff --git a/llvm/test/CodeGen/WebAssembly/f32.ll b/llvm/test/CodeGen/WebAssembly/f32.ll
index 7410fa43e4081..a7c35317f1da8 100644
--- a/llvm/test/CodeGen/WebAssembly/f32.ll
+++ b/llvm/test/CodeGen/WebAssembly/f32.ll
@@ -229,13 +229,10 @@ define float @fminnum32_intrinsic(float %x, float %y) {
; CHECK-LABEL: fminnum32_intrinsic:
; CHECK: .functype fminnum32_intrinsic (f32, f32) -> (f32)
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: local.get $push5=, 0
-; CHECK-NEXT: local.get $push4=, 1
-; CHECK-NEXT: local.get $push3=, 0
-; CHECK-NEXT: local.get $push2=, 1
-; CHECK-NEXT: f32.lt $push0=, $pop3, $pop2
-; CHECK-NEXT: f32.select $push1=, $pop5, $pop4, $pop0
-; CHECK-NEXT: return $pop1
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: f32.min $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
%a = call nnan float @llvm.minnum.f32(float %x, float %y)
ret float %a
}
@@ -282,13 +279,10 @@ define float @fmaxnum32_intrinsic(float %x, float %y) {
; CHECK-LABEL: fmaxnum32_intrinsic:
; CHECK: .functype fmaxnum32_intrinsic (f32, f32) -> (f32)
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: local.get $push5=, 0
-; CHECK-NEXT: local.get $push4=, 1
-; CHECK-NEXT: local.get $push3=, 0
-; CHECK-NEXT: local.get $push2=, 1
-; CHECK-NEXT: f32.gt $push0=, $pop3, $pop2
-; CHECK-NEXT: f32.select $push1=, $pop5, $pop4, $pop0
-; CHECK-NEXT: return $pop1
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: f32.max $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
%a = call nnan float @llvm.maxnum.f32(float %x, float %y)
ret float %a
}
@@ -309,13 +303,10 @@ define float @fmaxnum32_zero_intrinsic(float %x) {
; CHECK-LABEL: fmaxnum32_zero_intrinsic:
; CHECK: .functype fmaxnum32_zero_intrinsic (f32) -> (f32)
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: local.get $push5=, 0
+; CHECK-NEXT: local.get $push2=, 0
; CHECK-NEXT: f32.const $push0=, 0x0p0
-; CHECK-NEXT: local.get $push4=, 0
-; CHECK-NEXT: f32.const $push3=, 0x0p0
-; CHECK-NEXT: f32.gt $push1=, $pop4, $pop3
-; CHECK-NEXT: f32.select $push2=, $pop5, $pop0, $pop1
-; CHECK-NEXT: return $pop2
+; CHECK-NEXT: f32.max $push1=, $pop2, $pop0
+; CHECK-NEXT: return $pop1
%a = call nnan float @llvm.maxnum.f32(float %x, float 0.0)
ret float %a
}
diff --git a/llvm/test/CodeGen/WebAssembly/f64.ll b/llvm/test/CodeGen/WebAssembly/f64.ll
index d79f34185eb87..c5af777888d36 100644
--- a/llvm/test/CodeGen/WebAssembly/f64.ll
+++ b/llvm/test/CodeGen/WebAssembly/f64.ll
@@ -229,13 +229,10 @@ define double @fminnum64_intrinsic(double %x, double %y) {
; CHECK-LABEL: fminnum64_intrinsic:
; CHECK: .functype fminnum64_intrinsic (f64, f64) -> (f64)
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: local.get $push5=, 0
-; CHECK-NEXT: local.get $push4=, 1
-; CHECK-NEXT: local.get $push3=, 0
-; CHECK-NEXT: local.get $push2=, 1
-; CHECK-NEXT: f64.lt $push0=, $pop3, $pop2
-; CHECK-NEXT: f64.select $push1=, $pop5, $pop4, $pop0
-; CHECK-NEXT: return $pop1
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: f64.min $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
%a = call nnan double @llvm.minnum.f64(double %x, double %y)
ret double %a
}
@@ -256,13 +253,10 @@ define double @fminnum64_zero_intrinsic(double %x) {
; CHECK-LABEL: fminnum64_zero_intrinsic:
; CHECK: .functype fminnum64_zero_intrinsic (f64) -> (f64)
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: local.get $push5=, 0
+; CHECK-NEXT: local.get $push2=, 0
; CHECK-NEXT: f64.const $push0=, -0x0p0
-; CHECK-NEXT: local.get $push4=, 0
-; CHECK-NEXT: f64.const $push3=, -0x0p0
-; CHECK-NEXT: f64.lt $push1=, $pop4, $pop3
-; CHECK-NEXT: f64.select $push2=, $pop5, $pop0, $pop1
-; CHECK-NEXT: return $pop2
+; CHECK-NEXT: f64.min $push1=, $pop2, $pop0
+; CHECK-NEXT: return $pop1
%a = call nnan double @llvm.minnum.f64(double %x, double -0.0)
ret double %a
}
@@ -297,13 +291,10 @@ define double at fmaxnum64_intrinsic(double %x, double %y) {
; CHECK-LABEL: fmaxnum64_intrinsic:
; CHECK: .functype fmaxnum64_intrinsic (f64, f64) -> (f64)
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: local.get $push5=, 0
-; CHECK-NEXT: local.get $push4=, 1
-; CHECK-NEXT: local.get $push3=, 0
-; CHECK-NEXT: local.get $push2=, 1
-; CHECK-NEXT: f64.gt $push0=, $pop3, $pop2
-; CHECK-NEXT: f64.select $push1=, $pop5, $pop4, $pop0
-; CHECK-NEXT: return $pop1
+; CHECK-NEXT: local.get $push2=, 0
+; CHECK-NEXT: local.get $push1=, 1
+; CHECK-NEXT: f64.max $push0=, $pop2, $pop1
+; CHECK-NEXT: return $pop0
%a = call nnan double @llvm.maxnum.f64(double %x, double %y)
ret double %a
}
@@ -324,13 +315,10 @@ define double @fmaxnum64_zero_intrinsic(double %x) {
; CHECK-LABEL: fmaxnum64_zero_intrinsic:
; CHECK: .functype fmaxnum64_zero_intrinsic (f64) -> (f64)
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: local.get $push5=, 0
+; CHECK-NEXT: local.get $push2=, 0
; CHECK-NEXT: f64.const $push0=, 0x0p0
-; CHECK-NEXT: local.get $push4=, 0
-; CHECK-NEXT: f64.const $push3=, 0x0p0
-; CHECK-NEXT: f64.gt $push1=, $pop4, $pop3
-; CHECK-NEXT: f64.select $push2=, $pop5, $pop0, $pop1
-; CHECK-NEXT: return $pop2
+; CHECK-NEXT: f64.max $push1=, $pop2, $pop0
+; CHECK-NEXT: return $pop1
%a = call nnan double @llvm.maxnum.f64(double %x, double 0.0)
ret double %a
}
diff --git a/llvm/test/CodeGen/WebAssembly/simd-arith.ll b/llvm/test/CodeGen/WebAssembly/simd-arith.ll
index 185c46aa5681e..875fe6924fbd2 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-arith.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-arith.ll
@@ -11722,101 +11722,69 @@ define <4 x float> @minnum_intrinsic_v4f32(<4 x float> %x, <4 x float> %y) {
; SIMD128-LABEL: minnum_intrinsic_v4f32:
; SIMD128: .functype minnum_intrinsic_v4f32 (v128, v128) -> (v128)
; SIMD128-NEXT: # %bb.0:
-; SIMD128-NEXT: f32x4.extract_lane $push27=, $0, 0
-; SIMD128-NEXT: local.tee $push26=, $3=, $pop27
-; SIMD128-NEXT: f32x4.extract_lane $push25=, $1, 0
-; SIMD128-NEXT: local.tee $push24=, $2=, $pop25
-; SIMD128-NEXT: f32.lt $push2=, $3, $2
-; SIMD128-NEXT: f32.select $push3=, $pop26, $pop24, $pop2
-; SIMD128-NEXT: f32x4.splat $push4=, $pop3
-; SIMD128-NEXT: f32x4.extract_lane $push23=, $0, 1
-; SIMD128-NEXT: local.tee $push22=, $3=, $pop23
-; SIMD128-NEXT: f32x4.extract_lane $push21=, $1, 1
-; SIMD128-NEXT: local.tee $push20=, $2=, $pop21
-; SIMD128-NEXT: f32.lt $push0=, $3, $2
-; SIMD128-NEXT: f32.select $push1=, $pop22, $pop20, $pop0
-; SIMD128-NEXT: f32x4.replace_lane $push5=, $pop4, 1, $pop1
-; SIMD128-NEXT: f32x4.extract_lane $push19=, $0, 2
-; SIMD128-NEXT: local.tee $push18=, $3=, $pop19
-; SIMD128-NEXT: f32x4.extract_lane $push17=, $1, 2
-; SIMD128-NEXT: local.tee $push16=, $2=, $pop17
-; SIMD128-NEXT: f32.lt $push6=, $3, $2
-; SIMD128-NEXT: f32.select $push7=, $pop18, $pop16, $pop6
-; SIMD128-NEXT: f32x4.replace_lane $push8=, $pop5, 2, $pop7
-; SIMD128-NEXT: f32x4.extract_lane $push15=, $0, 3
-; SIMD128-NEXT: local.tee $push14=, $3=, $pop15
-; SIMD128-NEXT: f32x4.extract_lane $push13=, $1, 3
-; SIMD128-NEXT: local.tee $push12=, $2=, $pop13
-; SIMD128-NEXT: f32.lt $push9=, $3, $2
-; SIMD128-NEXT: f32.select $push10=, $pop14, $pop12, $pop9
-; SIMD128-NEXT: f32x4.replace_lane $push11=, $pop8, 3, $pop10
-; SIMD128-NEXT: return $pop11
+; SIMD128-NEXT: f32x4.extract_lane $push4=, $0, 0
+; SIMD128-NEXT: f32x4.extract_lane $push3=, $1, 0
+; SIMD128-NEXT: f32.min $push5=, $pop4, $pop3
+; SIMD128-NEXT: f32x4.splat $push6=, $pop5
+; SIMD128-NEXT: f32x4.extract_lane $push1=, $0, 1
+; SIMD128-NEXT: f32x4.extract_lane $push0=, $1, 1
+; SIMD128-NEXT: f32.min $push2=, $pop1, $pop0
+; SIMD128-NEXT: f32x4.replace_lane $push7=, $pop6, 1, $pop2
+; SIMD128-NEXT: f32x4.extract_lane $push9=, $0, 2
+; SIMD128-NEXT: f32x4.extract_lane $push8=, $1, 2
+; SIMD128-NEXT: f32.min $push10=, $pop9, $pop8
+; SIMD128-NEXT: f32x4.replace_lane $push11=, $pop7, 2, $pop10
+; SIMD128-NEXT: f32x4.extract_lane $push13=, $0, 3
+; SIMD128-NEXT: f32x4.extract_lane $push12=, $1, 3
+; SIMD128-NEXT: f32.min $push14=, $pop13, $pop12
+; SIMD128-NEXT: f32x4.replace_lane $push15=, $pop11, 3, $pop14
+; SIMD128-NEXT: return $pop15
;
; SIMD128-FAST-LABEL: minnum_intrinsic_v4f32:
; SIMD128-FAST: .functype minnum_intrinsic_v4f32 (v128, v128) -> (v128)
; SIMD128-FAST-NEXT: # %bb.0:
-; SIMD128-FAST-NEXT: f32x4.extract_lane $push27=, $0, 0
-; SIMD128-FAST-NEXT: local.tee $push26=, $3=, $pop27
-; SIMD128-FAST-NEXT: f32x4.extract_lane $push25=, $1, 0
-; SIMD128-FAST-NEXT: local.tee $push24=, $2=, $pop25
-; SIMD128-FAST-NEXT: f32.lt $push3=, $3, $2
-; SIMD128-FAST-NEXT: f32.select $push4=, $pop26, $pop24, $pop3
-; SIMD128-FAST-NEXT: f32x4.splat $push5=, $pop4
-; SIMD128-FAST-NEXT: f32x4.extract_lane $push23=, $0, 1
-; SIMD128-FAST-NEXT: local.tee $push22=, $3=, $pop23
-; SIMD128-FAST-NEXT: f32x4.extract_lane $push21=, $1, 1
-; SIMD128-FAST-NEXT: local.tee $push20=, $2=, $pop21
-; SIMD128-FAST-NEXT: f32.lt $push1=, $3, $2
-; SIMD128-FAST-NEXT: f32.select $push2=, $pop22, $pop20, $pop1
-; SIMD128-FAST-NEXT: f32x4.replace_lane $push6=, $pop5, 1, $pop2
-; SIMD128-FAST-NEXT: f32x4.extract_lane $push19=, $0, 2
-; SIMD128-FAST-NEXT: local.tee $push18=, $3=, $pop19
-; SIMD128-FAST-NEXT: f32x4.extract_lane $push17=, $1, 2
-; SIMD128-FAST-NEXT: local.tee $push16=, $2=, $pop17
-; SIMD128-FAST-NEXT: f32.lt $push7=, $3, $2
-; SIMD128-FAST-NEXT: f32.select $push8=, $pop18, $pop16, $pop7
-; SIMD128-FAST-NEXT: f32x4.replace_lane $push9=, $pop6, 2, $pop8
-; SIMD128-FAST-NEXT: f32x4.extract_lane $push15=, $0, 3
-; SIMD128-FAST-NEXT: local.tee $push14=, $3=, $pop15
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push5=, $0, 0
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push4=, $1, 0
+; SIMD128-FAST-NEXT: f32.min $push6=, $pop5, $pop4
+; SIMD128-FAST-NEXT: f32x4.splat $push7=, $pop6
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push2=, $0, 1
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push1=, $1, 1
+; SIMD128-FAST-NEXT: f32.min $push3=, $pop2, $pop1
+; SIMD128-FAST-NEXT: f32x4.replace_lane $push8=, $pop7, 1, $pop3
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push10=, $0, 2
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push9=, $1, 2
+; SIMD128-FAST-NEXT: f32.min $push11=, $pop10, $pop9
+; SIMD128-FAST-NEXT: f32x4.replace_lane $push12=, $pop8, 2, $pop11
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push14=, $0, 3
; SIMD128-FAST-NEXT: f32x4.extract_lane $push13=, $1, 3
-; SIMD128-FAST-NEXT: local.tee $push12=, $2=, $pop13
-; SIMD128-FAST-NEXT: f32.lt $push10=, $3, $2
-; SIMD128-FAST-NEXT: f32.select $push11=, $pop14, $pop12, $pop10
-; SIMD128-FAST-NEXT: f32x4.replace_lane $push0=, $pop9, 3, $pop11
+; SIMD128-FAST-NEXT: f32.min $push15=, $pop14, $pop13
+; SIMD128-FAST-NEXT: f32x4.replace_lane $push0=, $pop12, 3, $pop15
; SIMD128-FAST-NEXT: return $pop0
;
; NO-SIMD128-LABEL: minnum_intrinsic_v4f32:
; NO-SIMD128: .functype minnum_intrinsic_v4f32 (i32, f32, f32, f32, f32, f32, f32, f32, f32) -> ()
; NO-SIMD128-NEXT: # %bb.0:
-; NO-SIMD128-NEXT: f32.lt $push0=, $4, $8
-; NO-SIMD128-NEXT: f32.select $push1=, $4, $8, $pop0
-; NO-SIMD128-NEXT: f32.store 12($0), $pop1
-; NO-SIMD128-NEXT: f32.lt $push2=, $3, $7
-; NO-SIMD128-NEXT: f32.select $push3=, $3, $7, $pop2
-; NO-SIMD128-NEXT: f32.store 8($0), $pop3
-; NO-SIMD128-NEXT: f32.lt $push4=, $2, $6
-; NO-SIMD128-NEXT: f32.select $push5=, $2, $6, $pop4
-; NO-SIMD128-NEXT: f32.store 4($0), $pop5
-; NO-SIMD128-NEXT: f32.lt $push6=, $1, $5
-; NO-SIMD128-NEXT: f32.select $push7=, $1, $5, $pop6
-; NO-SIMD128-NEXT: f32.store 0($0), $pop7
+; NO-SIMD128-NEXT: f32.min $push0=, $4, $8
+; NO-SIMD128-NEXT: f32.store 12($0), $pop0
+; NO-SIMD128-NEXT: f32.min $push1=, $3, $7
+; NO-SIMD128-NEXT: f32.store 8($0), $pop1
+; NO-SIMD128-NEXT: f32.min $push2=, $2, $6
+; NO-SIMD128-NEXT: f32.store 4($0), $pop2
+; NO-SIMD128-NEXT: f32.min $push3=, $1, $5
+; NO-SIMD128-NEXT: f32.store 0($0), $pop3
; NO-SIMD128-NEXT: return
;
; NO-SIMD128-FAST-LABEL: minnum_intrinsic_v4f32:
; NO-SIMD128-FAST: .functype minnum_intrinsic_v4f32 (i32, f32, f32, f32, f32, f32, f32, f32, f32) -> ()
; NO-SIMD128-FAST-NEXT: # %bb.0:
-; NO-SIMD128-FAST-NEXT: f32.lt $push0=, $1, $5
-; NO-SIMD128-FAST-NEXT: f32.select $push1=, $1, $5, $pop0
-; NO-SIMD128-FAST-NEXT: f32.store 0($0), $pop1
-; NO-SIMD128-FAST-NEXT: f32.lt $push2=, $2, $6
-; NO-SIMD128-FAST-NEXT: f32.select $push3=, $2, $6, $pop2
-; NO-SIMD128-FAST-NEXT: f32.store 4($0), $pop3
-; NO-SIMD128-FAST-NEXT: f32.lt $push4=, $3, $7
-; NO-SIMD128-FAST-NEXT: f32.select $push5=, $3, $7, $pop4
-; NO-SIMD128-FAST-NEXT: f32.store 8($0), $pop5
-; NO-SIMD128-FAST-NEXT: f32.lt $push6=, $4, $8
-; NO-SIMD128-FAST-NEXT: f32.select $push7=, $4, $8, $pop6
-; NO-SIMD128-FAST-NEXT: f32.store 12($0), $pop7
+; NO-SIMD128-FAST-NEXT: f32.min $push0=, $1, $5
+; NO-SIMD128-FAST-NEXT: f32.store 0($0), $pop0
+; NO-SIMD128-FAST-NEXT: f32.min $push1=, $2, $6
+; NO-SIMD128-FAST-NEXT: f32.store 4($0), $pop1
+; NO-SIMD128-FAST-NEXT: f32.min $push2=, $3, $7
+; NO-SIMD128-FAST-NEXT: f32.store 8($0), $pop2
+; NO-SIMD128-FAST-NEXT: f32.min $push3=, $4, $8
+; NO-SIMD128-FAST-NEXT: f32.store 12($0), $pop3
; NO-SIMD128-FAST-NEXT: return
%a = call nnan <4 x float> @llvm.minnum.v4f32(<4 x float> %x, <4 x float> %y)
ret <4 x float> %a
@@ -11920,66 +11888,42 @@ define <4 x float> @fminnumv432_one_zero_intrinsic(<4 x float> %x) {
; SIMD128-LABEL: fminnumv432_one_zero_intrinsic:
; SIMD128: .functype fminnumv432_one_zero_intrinsic (v128) -> (v128)
; SIMD128-NEXT: # %bb.0:
-; SIMD128-NEXT: f32x4.extract_lane $push27=, $0, 0
-; SIMD128-NEXT: local.tee $push26=, $1=, $pop27
-; SIMD128-NEXT: f32.const $push3=, -0x1p0
-; SIMD128-NEXT: f32.const $push25=, -0x1p0
-; SIMD128-NEXT: f32.lt $push4=, $1, $pop25
-; SIMD128-NEXT: f32.select $push5=, $pop26, $pop3, $pop4
+; SIMD128-NEXT: f32x4.extract_lane $push3=, $0, 0
+; SIMD128-NEXT: f32.const $push4=, -0x1p0
+; SIMD128-NEXT: f32.min $push5=, $pop3, $pop4
; SIMD128-NEXT: f32x4.splat $push6=, $pop5
-; SIMD128-NEXT: f32x4.extract_lane $push24=, $0, 1
-; SIMD128-NEXT: local.tee $push23=, $1=, $pop24
-; SIMD128-NEXT: f32.const $push0=, 0x0p0
-; SIMD128-NEXT: f32.const $push22=, 0x0p0
-; SIMD128-NEXT: f32.lt $push1=, $1, $pop22
-; SIMD128-NEXT: f32.select $push2=, $pop23, $pop0, $pop1
+; SIMD128-NEXT: f32x4.extract_lane $push0=, $0, 1
+; SIMD128-NEXT: f32.const $push1=, 0x0p0
+; SIMD128-NEXT: f32.min $push2=, $pop0, $pop1
; SIMD128-NEXT: f32x4.replace_lane $push7=, $pop6, 1, $pop2
-; SIMD128-NEXT: f32x4.extract_lane $push21=, $0, 2
-; SIMD128-NEXT: local.tee $push20=, $1=, $pop21
-; SIMD128-NEXT: f32.const $push19=, -0x1p0
-; SIMD128-NEXT: f32.const $push18=, -0x1p0
-; SIMD128-NEXT: f32.lt $push8=, $1, $pop18
-; SIMD128-NEXT: f32.select $push9=, $pop20, $pop19, $pop8
-; SIMD128-NEXT: f32x4.replace_lane $push10=, $pop7, 2, $pop9
-; SIMD128-NEXT: f32x4.extract_lane $push17=, $0, 3
-; SIMD128-NEXT: local.tee $push16=, $1=, $pop17
+; SIMD128-NEXT: f32x4.extract_lane $push8=, $0, 2
; SIMD128-NEXT: f32.const $push15=, -0x1p0
+; SIMD128-NEXT: f32.min $push9=, $pop8, $pop15
+; SIMD128-NEXT: f32x4.replace_lane $push10=, $pop7, 2, $pop9
+; SIMD128-NEXT: f32x4.extract_lane $push11=, $0, 3
; SIMD128-NEXT: f32.const $push14=, -0x1p0
-; SIMD128-NEXT: f32.lt $push11=, $1, $pop14
-; SIMD128-NEXT: f32.select $push12=, $pop16, $pop15, $pop11
+; SIMD128-NEXT: f32.min $push12=, $pop11, $pop14
; SIMD128-NEXT: f32x4.replace_lane $push13=, $pop10, 3, $pop12
; SIMD128-NEXT: return $pop13
;
; SIMD128-FAST-LABEL: fminnumv432_one_zero_intrinsic:
; SIMD128-FAST: .functype fminnumv432_one_zero_intrinsic (v128) -> (v128)
; SIMD128-FAST-NEXT: # %bb.0:
-; SIMD128-FAST-NEXT: f32x4.extract_lane $push27=, $0, 0
-; SIMD128-FAST-NEXT: local.tee $push26=, $1=, $pop27
-; SIMD128-FAST-NEXT: f32.const $push4=, -0x1p0
-; SIMD128-FAST-NEXT: f32.const $push25=, -0x1p0
-; SIMD128-FAST-NEXT: f32.lt $push5=, $1, $pop25
-; SIMD128-FAST-NEXT: f32.select $push6=, $pop26, $pop4, $pop5
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push4=, $0, 0
+; SIMD128-FAST-NEXT: f32.const $push5=, -0x1p0
+; SIMD128-FAST-NEXT: f32.min $push6=, $pop4, $pop5
; SIMD128-FAST-NEXT: f32x4.splat $push7=, $pop6
-; SIMD128-FAST-NEXT: f32x4.extract_lane $push24=, $0, 1
-; SIMD128-FAST-NEXT: local.tee $push23=, $1=, $pop24
-; SIMD128-FAST-NEXT: f32.const $push1=, 0x0p0
-; SIMD128-FAST-NEXT: f32.const $push22=, 0x0p0
-; SIMD128-FAST-NEXT: f32.lt $push2=, $1, $pop22
-; SIMD128-FAST-NEXT: f32.select $push3=, $pop23, $pop1, $pop2
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push1=, $0, 1
+; SIMD128-FAST-NEXT: f32.const $push2=, 0x0p0
+; SIMD128-FAST-NEXT: f32.min $push3=, $pop1, $pop2
; SIMD128-FAST-NEXT: f32x4.replace_lane $push8=, $pop7, 1, $pop3
-; SIMD128-FAST-NEXT: f32x4.extract_lane $push21=, $0, 2
-; SIMD128-FAST-NEXT: local.tee $push20=, $1=, $pop21
-; SIMD128-FAST-NEXT: f32.const $push19=, -0x1p0
-; SIMD128-FAST-NEXT: f32.const $push18=, -0x1p0
-; SIMD128-FAST-NEXT: f32.lt $push9=, $1, $pop18
-; SIMD128-FAST-NEXT: f32.select $push10=, $pop20, $pop19, $pop9
-; SIMD128-FAST-NEXT: f32x4.replace_lane $push11=, $pop8, 2, $pop10
-; SIMD128-FAST-NEXT: f32x4.extract_lane $push17=, $0, 3
-; SIMD128-FAST-NEXT: local.tee $push16=, $1=, $pop17
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push9=, $0, 2
; SIMD128-FAST-NEXT: f32.const $push15=, -0x1p0
+; SIMD128-FAST-NEXT: f32.min $push10=, $pop9, $pop15
+; SIMD128-FAST-NEXT: f32x4.replace_lane $push11=, $pop8, 2, $pop10
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push12=, $0, 3
; SIMD128-FAST-NEXT: f32.const $push14=, -0x1p0
-; SIMD128-FAST-NEXT: f32.lt $push12=, $1, $pop14
-; SIMD128-FAST-NEXT: f32.select $push13=, $pop16, $pop15, $pop12
+; SIMD128-FAST-NEXT: f32.min $push13=, $pop12, $pop14
; SIMD128-FAST-NEXT: f32x4.replace_lane $push0=, $pop11, 3, $pop13
; SIMD128-FAST-NEXT: return $pop0
;
@@ -11989,17 +11933,15 @@ define <4 x float> @fminnumv432_one_zero_intrinsic(<4 x float> %x) {
; NO-SIMD128-NEXT: f32.const $push0=, -0x1p0
; NO-SIMD128-NEXT: f32.min $push1=, $4, $pop0
; NO-SIMD128-NEXT: f32.store 12($0), $pop1
-; NO-SIMD128-NEXT: f32.const $push9=, -0x1p0
-; NO-SIMD128-NEXT: f32.min $push2=, $3, $pop9
+; NO-SIMD128-NEXT: f32.const $push7=, -0x1p0
+; NO-SIMD128-NEXT: f32.min $push2=, $3, $pop7
; NO-SIMD128-NEXT: f32.store 8($0), $pop2
; NO-SIMD128-NEXT: f32.const $push3=, 0x0p0
-; NO-SIMD128-NEXT: f32.const $push8=, 0x0p0
-; NO-SIMD128-NEXT: f32.lt $push4=, $2, $pop8
-; NO-SIMD128-NEXT: f32.select $push5=, $2, $pop3, $pop4
-; NO-SIMD128-NEXT: f32.store 4($0), $pop5
-; NO-SIMD128-NEXT: f32.const $push7=, -0x1p0
-; NO-SIMD128-NEXT: f32.min $push6=, $1, $pop7
-; NO-SIMD128-NEXT: f32.store 0($0), $pop6
+; NO-SIMD128-NEXT: f32.min $push4=, $2, $pop3
+; NO-SIMD128-NEXT: f32.store 4($0), $pop4
+; NO-SIMD128-NEXT: f32.const $push6=, -0x1p0
+; NO-SIMD128-NEXT: f32.min $push5=, $1, $pop6
+; NO-SIMD128-NEXT: f32.store 0($0), $pop5
; NO-SIMD128-NEXT: return
;
; NO-SIMD128-FAST-LABEL: fminnumv432_one_zero_intrinsic:
@@ -12008,17 +11950,15 @@ define <4 x float> @fminnumv432_one_zero_intrinsic(<4 x float> %x) {
; NO-SIMD128-FAST-NEXT: f32.const $push0=, -0x1p0
; NO-SIMD128-FAST-NEXT: f32.min $push1=, $1, $pop0
; NO-SIMD128-FAST-NEXT: f32.store 0($0), $pop1
-; NO-SIMD128-FAST-NEXT: f32.const $push9=, -0x1p0
-; NO-SIMD128-FAST-NEXT: f32.min $push2=, $3, $pop9
-; NO-SIMD128-FAST-NEXT: f32.store 8($0), $pop2
-; NO-SIMD128-FAST-NEXT: f32.const $push3=, 0x0p0
-; NO-SIMD128-FAST-NEXT: f32.const $push8=, 0x0p0
-; NO-SIMD128-FAST-NEXT: f32.lt $push4=, $2, $pop8
-; NO-SIMD128-FAST-NEXT: f32.select $push5=, $2, $pop3, $pop4
-; NO-SIMD128-FAST-NEXT: f32.store 4($0), $pop5
+; NO-SIMD128-FAST-NEXT: f32.const $push2=, 0x0p0
+; NO-SIMD128-FAST-NEXT: f32.min $push3=, $2, $pop2
+; NO-SIMD128-FAST-NEXT: f32.store 4($0), $pop3
; NO-SIMD128-FAST-NEXT: f32.const $push7=, -0x1p0
-; NO-SIMD128-FAST-NEXT: f32.min $push6=, $4, $pop7
-; NO-SIMD128-FAST-NEXT: f32.store 12($0), $pop6
+; NO-SIMD128-FAST-NEXT: f32.min $push4=, $3, $pop7
+; NO-SIMD128-FAST-NEXT: f32.store 8($0), $pop4
+; NO-SIMD128-FAST-NEXT: f32.const $push6=, -0x1p0
+; NO-SIMD128-FAST-NEXT: f32.min $push5=, $4, $pop6
+; NO-SIMD128-FAST-NEXT: f32.store 12($0), $pop5
; NO-SIMD128-FAST-NEXT: return
%a = call nnan <4 x float> @llvm.minnum.v4f32(<4 x float> %x, <4 x float><float -1.0, float 0.0, float -1.0, float -1.0>)
ret <4 x float> %a
@@ -12072,101 +12012,69 @@ define <4 x float> @maxnum_intrinsic_v4f32(<4 x float> %x, <4 x float> %y) {
; SIMD128-LABEL: maxnum_intrinsic_v4f32:
; SIMD128: .functype maxnum_intrinsic_v4f32 (v128, v128) -> (v128)
; SIMD128-NEXT: # %bb.0:
-; SIMD128-NEXT: f32x4.extract_lane $push27=, $0, 0
-; SIMD128-NEXT: local.tee $push26=, $3=, $pop27
-; SIMD128-NEXT: f32x4.extract_lane $push25=, $1, 0
-; SIMD128-NEXT: local.tee $push24=, $2=, $pop25
-; SIMD128-NEXT: f32.gt $push2=, $3, $2
-; SIMD128-NEXT: f32.select $push3=, $pop26, $pop24, $pop2
-; SIMD128-NEXT: f32x4.splat $push4=, $pop3
-; SIMD128-NEXT: f32x4.extract_lane $push23=, $0, 1
-; SIMD128-NEXT: local.tee $push22=, $3=, $pop23
-; SIMD128-NEXT: f32x4.extract_lane $push21=, $1, 1
-; SIMD128-NEXT: local.tee $push20=, $2=, $pop21
-; SIMD128-NEXT: f32.gt $push0=, $3, $2
-; SIMD128-NEXT: f32.select $push1=, $pop22, $pop20, $pop0
-; SIMD128-NEXT: f32x4.replace_lane $push5=, $pop4, 1, $pop1
-; SIMD128-NEXT: f32x4.extract_lane $push19=, $0, 2
-; SIMD128-NEXT: local.tee $push18=, $3=, $pop19
-; SIMD128-NEXT: f32x4.extract_lane $push17=, $1, 2
-; SIMD128-NEXT: local.tee $push16=, $2=, $pop17
-; SIMD128-NEXT: f32.gt $push6=, $3, $2
-; SIMD128-NEXT: f32.select $push7=, $pop18, $pop16, $pop6
-; SIMD128-NEXT: f32x4.replace_lane $push8=, $pop5, 2, $pop7
-; SIMD128-NEXT: f32x4.extract_lane $push15=, $0, 3
-; SIMD128-NEXT: local.tee $push14=, $3=, $pop15
-; SIMD128-NEXT: f32x4.extract_lane $push13=, $1, 3
-; SIMD128-NEXT: local.tee $push12=, $2=, $pop13
-; SIMD128-NEXT: f32.gt $push9=, $3, $2
-; SIMD128-NEXT: f32.select $push10=, $pop14, $pop12, $pop9
-; SIMD128-NEXT: f32x4.replace_lane $push11=, $pop8, 3, $pop10
-; SIMD128-NEXT: return $pop11
+; SIMD128-NEXT: f32x4.extract_lane $push4=, $0, 0
+; SIMD128-NEXT: f32x4.extract_lane $push3=, $1, 0
+; SIMD128-NEXT: f32.max $push5=, $pop4, $pop3
+; SIMD128-NEXT: f32x4.splat $push6=, $pop5
+; SIMD128-NEXT: f32x4.extract_lane $push1=, $0, 1
+; SIMD128-NEXT: f32x4.extract_lane $push0=, $1, 1
+; SIMD128-NEXT: f32.max $push2=, $pop1, $pop0
+; SIMD128-NEXT: f32x4.replace_lane $push7=, $pop6, 1, $pop2
+; SIMD128-NEXT: f32x4.extract_lane $push9=, $0, 2
+; SIMD128-NEXT: f32x4.extract_lane $push8=, $1, 2
+; SIMD128-NEXT: f32.max $push10=, $pop9, $pop8
+; SIMD128-NEXT: f32x4.replace_lane $push11=, $pop7, 2, $pop10
+; SIMD128-NEXT: f32x4.extract_lane $push13=, $0, 3
+; SIMD128-NEXT: f32x4.extract_lane $push12=, $1, 3
+; SIMD128-NEXT: f32.max $push14=, $pop13, $pop12
+; SIMD128-NEXT: f32x4.replace_lane $push15=, $pop11, 3, $pop14
+; SIMD128-NEXT: return $pop15
;
; SIMD128-FAST-LABEL: maxnum_intrinsic_v4f32:
; SIMD128-FAST: .functype maxnum_intrinsic_v4f32 (v128, v128) -> (v128)
; SIMD128-FAST-NEXT: # %bb.0:
-; SIMD128-FAST-NEXT: f32x4.extract_lane $push27=, $0, 0
-; SIMD128-FAST-NEXT: local.tee $push26=, $3=, $pop27
-; SIMD128-FAST-NEXT: f32x4.extract_lane $push25=, $1, 0
-; SIMD128-FAST-NEXT: local.tee $push24=, $2=, $pop25
-; SIMD128-FAST-NEXT: f32.gt $push3=, $3, $2
-; SIMD128-FAST-NEXT: f32.select $push4=, $pop26, $pop24, $pop3
-; SIMD128-FAST-NEXT: f32x4.splat $push5=, $pop4
-; SIMD128-FAST-NEXT: f32x4.extract_lane $push23=, $0, 1
-; SIMD128-FAST-NEXT: local.tee $push22=, $3=, $pop23
-; SIMD128-FAST-NEXT: f32x4.extract_lane $push21=, $1, 1
-; SIMD128-FAST-NEXT: local.tee $push20=, $2=, $pop21
-; SIMD128-FAST-NEXT: f32.gt $push1=, $3, $2
-; SIMD128-FAST-NEXT: f32.select $push2=, $pop22, $pop20, $pop1
-; SIMD128-FAST-NEXT: f32x4.replace_lane $push6=, $pop5, 1, $pop2
-; SIMD128-FAST-NEXT: f32x4.extract_lane $push19=, $0, 2
-; SIMD128-FAST-NEXT: local.tee $push18=, $3=, $pop19
-; SIMD128-FAST-NEXT: f32x4.extract_lane $push17=, $1, 2
-; SIMD128-FAST-NEXT: local.tee $push16=, $2=, $pop17
-; SIMD128-FAST-NEXT: f32.gt $push7=, $3, $2
-; SIMD128-FAST-NEXT: f32.select $push8=, $pop18, $pop16, $pop7
-; SIMD128-FAST-NEXT: f32x4.replace_lane $push9=, $pop6, 2, $pop8
-; SIMD128-FAST-NEXT: f32x4.extract_lane $push15=, $0, 3
-; SIMD128-FAST-NEXT: local.tee $push14=, $3=, $pop15
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push5=, $0, 0
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push4=, $1, 0
+; SIMD128-FAST-NEXT: f32.max $push6=, $pop5, $pop4
+; SIMD128-FAST-NEXT: f32x4.splat $push7=, $pop6
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push2=, $0, 1
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push1=, $1, 1
+; SIMD128-FAST-NEXT: f32.max $push3=, $pop2, $pop1
+; SIMD128-FAST-NEXT: f32x4.replace_lane $push8=, $pop7, 1, $pop3
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push10=, $0, 2
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push9=, $1, 2
+; SIMD128-FAST-NEXT: f32.max $push11=, $pop10, $pop9
+; SIMD128-FAST-NEXT: f32x4.replace_lane $push12=, $pop8, 2, $pop11
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push14=, $0, 3
; SIMD128-FAST-NEXT: f32x4.extract_lane $push13=, $1, 3
-; SIMD128-FAST-NEXT: local.tee $push12=, $2=, $pop13
-; SIMD128-FAST-NEXT: f32.gt $push10=, $3, $2
-; SIMD128-FAST-NEXT: f32.select $push11=, $pop14, $pop12, $pop10
-; SIMD128-FAST-NEXT: f32x4.replace_lane $push0=, $pop9, 3, $pop11
+; SIMD128-FAST-NEXT: f32.max $push15=, $pop14, $pop13
+; SIMD128-FAST-NEXT: f32x4.replace_lane $push0=, $pop12, 3, $pop15
; SIMD128-FAST-NEXT: return $pop0
;
; NO-SIMD128-LABEL: maxnum_intrinsic_v4f32:
; NO-SIMD128: .functype maxnum_intrinsic_v4f32 (i32, f32, f32, f32, f32, f32, f32, f32, f32) -> ()
; NO-SIMD128-NEXT: # %bb.0:
-; NO-SIMD128-NEXT: f32.gt $push0=, $4, $8
-; NO-SIMD128-NEXT: f32.select $push1=, $4, $8, $pop0
-; NO-SIMD128-NEXT: f32.store 12($0), $pop1
-; NO-SIMD128-NEXT: f32.gt $push2=, $3, $7
-; NO-SIMD128-NEXT: f32.select $push3=, $3, $7, $pop2
-; NO-SIMD128-NEXT: f32.store 8($0), $pop3
-; NO-SIMD128-NEXT: f32.gt $push4=, $2, $6
-; NO-SIMD128-NEXT: f32.select $push5=, $2, $6, $pop4
-; NO-SIMD128-NEXT: f32.store 4($0), $pop5
-; NO-SIMD128-NEXT: f32.gt $push6=, $1, $5
-; NO-SIMD128-NEXT: f32.select $push7=, $1, $5, $pop6
-; NO-SIMD128-NEXT: f32.store 0($0), $pop7
+; NO-SIMD128-NEXT: f32.max $push0=, $4, $8
+; NO-SIMD128-NEXT: f32.store 12($0), $pop0
+; NO-SIMD128-NEXT: f32.max $push1=, $3, $7
+; NO-SIMD128-NEXT: f32.store 8($0), $pop1
+; NO-SIMD128-NEXT: f32.max $push2=, $2, $6
+; NO-SIMD128-NEXT: f32.store 4($0), $pop2
+; NO-SIMD128-NEXT: f32.max $push3=, $1, $5
+; NO-SIMD128-NEXT: f32.store 0($0), $pop3
; NO-SIMD128-NEXT: return
;
; NO-SIMD128-FAST-LABEL: maxnum_intrinsic_v4f32:
; NO-SIMD128-FAST: .functype maxnum_intrinsic_v4f32 (i32, f32, f32, f32, f32, f32, f32, f32, f32) -> ()
; NO-SIMD128-FAST-NEXT: # %bb.0:
-; NO-SIMD128-FAST-NEXT: f32.gt $push0=, $1, $5
-; NO-SIMD128-FAST-NEXT: f32.select $push1=, $1, $5, $pop0
-; NO-SIMD128-FAST-NEXT: f32.store 0($0), $pop1
-; NO-SIMD128-FAST-NEXT: f32.gt $push2=, $2, $6
-; NO-SIMD128-FAST-NEXT: f32.select $push3=, $2, $6, $pop2
-; NO-SIMD128-FAST-NEXT: f32.store 4($0), $pop3
-; NO-SIMD128-FAST-NEXT: f32.gt $push4=, $3, $7
-; NO-SIMD128-FAST-NEXT: f32.select $push5=, $3, $7, $pop4
-; NO-SIMD128-FAST-NEXT: f32.store 8($0), $pop5
-; NO-SIMD128-FAST-NEXT: f32.gt $push6=, $4, $8
-; NO-SIMD128-FAST-NEXT: f32.select $push7=, $4, $8, $pop6
-; NO-SIMD128-FAST-NEXT: f32.store 12($0), $pop7
+; NO-SIMD128-FAST-NEXT: f32.max $push0=, $1, $5
+; NO-SIMD128-FAST-NEXT: f32.store 0($0), $pop0
+; NO-SIMD128-FAST-NEXT: f32.max $push1=, $2, $6
+; NO-SIMD128-FAST-NEXT: f32.store 4($0), $pop1
+; NO-SIMD128-FAST-NEXT: f32.max $push2=, $3, $7
+; NO-SIMD128-FAST-NEXT: f32.store 8($0), $pop2
+; NO-SIMD128-FAST-NEXT: f32.max $push3=, $4, $8
+; NO-SIMD128-FAST-NEXT: f32.store 12($0), $pop3
; NO-SIMD128-FAST-NEXT: return
%a = call nnan <4 x float> @llvm.maxnum.v4f32(<4 x float> %x, <4 x float> %y)
ret <4 x float> %a
@@ -12218,66 +12126,42 @@ define <4 x float> @maxnum_one_zero_intrinsic_v4f32(<4 x float> %x, <4 x float>
; SIMD128-LABEL: maxnum_one_zero_intrinsic_v4f32:
; SIMD128: .functype maxnum_one_zero_intrinsic_v4f32 (v128, v128) -> (v128)
; SIMD128-NEXT: # %bb.0:
-; SIMD128-NEXT: f32x4.extract_lane $push27=, $0, 0
-; SIMD128-NEXT: local.tee $push26=, $2=, $pop27
-; SIMD128-NEXT: f32.const $push3=, -0x1p0
-; SIMD128-NEXT: f32.const $push25=, -0x1p0
-; SIMD128-NEXT: f32.gt $push4=, $2, $pop25
-; SIMD128-NEXT: f32.select $push5=, $pop26, $pop3, $pop4
+; SIMD128-NEXT: f32x4.extract_lane $push3=, $0, 0
+; SIMD128-NEXT: f32.const $push4=, -0x1p0
+; SIMD128-NEXT: f32.max $push5=, $pop3, $pop4
; SIMD128-NEXT: f32x4.splat $push6=, $pop5
-; SIMD128-NEXT: f32x4.extract_lane $push24=, $0, 1
-; SIMD128-NEXT: local.tee $push23=, $2=, $pop24
-; SIMD128-NEXT: f32.const $push0=, 0x0p0
-; SIMD128-NEXT: f32.const $push22=, 0x0p0
-; SIMD128-NEXT: f32.gt $push1=, $2, $pop22
-; SIMD128-NEXT: f32.select $push2=, $pop23, $pop0, $pop1
+; SIMD128-NEXT: f32x4.extract_lane $push0=, $0, 1
+; SIMD128-NEXT: f32.const $push1=, 0x0p0
+; SIMD128-NEXT: f32.max $push2=, $pop0, $pop1
; SIMD128-NEXT: f32x4.replace_lane $push7=, $pop6, 1, $pop2
-; SIMD128-NEXT: f32x4.extract_lane $push21=, $0, 2
-; SIMD128-NEXT: local.tee $push20=, $2=, $pop21
-; SIMD128-NEXT: f32.const $push19=, -0x1p0
-; SIMD128-NEXT: f32.const $push18=, -0x1p0
-; SIMD128-NEXT: f32.gt $push8=, $2, $pop18
-; SIMD128-NEXT: f32.select $push9=, $pop20, $pop19, $pop8
-; SIMD128-NEXT: f32x4.replace_lane $push10=, $pop7, 2, $pop9
-; SIMD128-NEXT: f32x4.extract_lane $push17=, $0, 3
-; SIMD128-NEXT: local.tee $push16=, $2=, $pop17
+; SIMD128-NEXT: f32x4.extract_lane $push8=, $0, 2
; SIMD128-NEXT: f32.const $push15=, -0x1p0
+; SIMD128-NEXT: f32.max $push9=, $pop8, $pop15
+; SIMD128-NEXT: f32x4.replace_lane $push10=, $pop7, 2, $pop9
+; SIMD128-NEXT: f32x4.extract_lane $push11=, $0, 3
; SIMD128-NEXT: f32.const $push14=, -0x1p0
-; SIMD128-NEXT: f32.gt $push11=, $2, $pop14
-; SIMD128-NEXT: f32.select $push12=, $pop16, $pop15, $pop11
+; SIMD128-NEXT: f32.max $push12=, $pop11, $pop14
; SIMD128-NEXT: f32x4.replace_lane $push13=, $pop10, 3, $pop12
; SIMD128-NEXT: return $pop13
;
; SIMD128-FAST-LABEL: maxnum_one_zero_intrinsic_v4f32:
; SIMD128-FAST: .functype maxnum_one_zero_intrinsic_v4f32 (v128, v128) -> (v128)
; SIMD128-FAST-NEXT: # %bb.0:
-; SIMD128-FAST-NEXT: f32x4.extract_lane $push27=, $0, 0
-; SIMD128-FAST-NEXT: local.tee $push26=, $2=, $pop27
-; SIMD128-FAST-NEXT: f32.const $push4=, -0x1p0
-; SIMD128-FAST-NEXT: f32.const $push25=, -0x1p0
-; SIMD128-FAST-NEXT: f32.gt $push5=, $2, $pop25
-; SIMD128-FAST-NEXT: f32.select $push6=, $pop26, $pop4, $pop5
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push4=, $0, 0
+; SIMD128-FAST-NEXT: f32.const $push5=, -0x1p0
+; SIMD128-FAST-NEXT: f32.max $push6=, $pop4, $pop5
; SIMD128-FAST-NEXT: f32x4.splat $push7=, $pop6
-; SIMD128-FAST-NEXT: f32x4.extract_lane $push24=, $0, 1
-; SIMD128-FAST-NEXT: local.tee $push23=, $2=, $pop24
-; SIMD128-FAST-NEXT: f32.const $push1=, 0x0p0
-; SIMD128-FAST-NEXT: f32.const $push22=, 0x0p0
-; SIMD128-FAST-NEXT: f32.gt $push2=, $2, $pop22
-; SIMD128-FAST-NEXT: f32.select $push3=, $pop23, $pop1, $pop2
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push1=, $0, 1
+; SIMD128-FAST-NEXT: f32.const $push2=, 0x0p0
+; SIMD128-FAST-NEXT: f32.max $push3=, $pop1, $pop2
; SIMD128-FAST-NEXT: f32x4.replace_lane $push8=, $pop7, 1, $pop3
-; SIMD128-FAST-NEXT: f32x4.extract_lane $push21=, $0, 2
-; SIMD128-FAST-NEXT: local.tee $push20=, $2=, $pop21
-; SIMD128-FAST-NEXT: f32.const $push19=, -0x1p0
-; SIMD128-FAST-NEXT: f32.const $push18=, -0x1p0
-; SIMD128-FAST-NEXT: f32.gt $push9=, $2, $pop18
-; SIMD128-FAST-NEXT: f32.select $push10=, $pop20, $pop19, $pop9
-; SIMD128-FAST-NEXT: f32x4.replace_lane $push11=, $pop8, 2, $pop10
-; SIMD128-FAST-NEXT: f32x4.extract_lane $push17=, $0, 3
-; SIMD128-FAST-NEXT: local.tee $push16=, $2=, $pop17
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push9=, $0, 2
; SIMD128-FAST-NEXT: f32.const $push15=, -0x1p0
+; SIMD128-FAST-NEXT: f32.max $push10=, $pop9, $pop15
+; SIMD128-FAST-NEXT: f32x4.replace_lane $push11=, $pop8, 2, $pop10
+; SIMD128-FAST-NEXT: f32x4.extract_lane $push12=, $0, 3
; SIMD128-FAST-NEXT: f32.const $push14=, -0x1p0
-; SIMD128-FAST-NEXT: f32.gt $push12=, $2, $pop14
-; SIMD128-FAST-NEXT: f32.select $push13=, $pop16, $pop15, $pop12
+; SIMD128-FAST-NEXT: f32.max $push13=, $pop12, $pop14
; SIMD128-FAST-NEXT: f32x4.replace_lane $push0=, $pop11, 3, $pop13
; SIMD128-FAST-NEXT: return $pop0
;
@@ -12287,17 +12171,15 @@ define <4 x float> @maxnum_one_zero_intrinsic_v4f32(<4 x float> %x, <4 x float>
; NO-SIMD128-NEXT: f32.const $push0=, -0x1p0
; NO-SIMD128-NEXT: f32.max $push1=, $4, $pop0
; NO-SIMD128-NEXT: f32.store 12($0), $pop1
-; NO-SIMD128-NEXT: f32.const $push9=, -0x1p0
-; NO-SIMD128-NEXT: f32.max $push2=, $3, $pop9
+; NO-SIMD128-NEXT: f32.const $push7=, -0x1p0
+; NO-SIMD128-NEXT: f32.max $push2=, $3, $pop7
; NO-SIMD128-NEXT: f32.store 8($0), $pop2
; NO-SIMD128-NEXT: f32.const $push3=, 0x0p0
-; NO-SIMD128-NEXT: f32.const $push8=, 0x0p0
-; NO-SIMD128-NEXT: f32.gt $push4=, $2, $pop8
-; NO-SIMD128-NEXT: f32.select $push5=, $2, $pop3, $pop4
-; NO-SIMD128-NEXT: f32.store 4($0), $pop5
-; NO-SIMD128-NEXT: f32.const $push7=, -0x1p0
-; NO-SIMD128-NEXT: f32.max $push6=, $1, $pop7
-; NO-SIMD128-NEXT: f32.store 0($0), $pop6
+; NO-SIMD128-NEXT: f32.max $push4=, $2, $pop3
+; NO-SIMD128-NEXT: f32.store 4($0), $pop4
+; NO-SIMD128-NEXT: f32.const $push6=, -0x1p0
+; NO-SIMD128-NEXT: f32.max $push5=, $1, $pop6
+; NO-SIMD128-NEXT: f32.store 0($0), $pop5
; NO-SIMD128-NEXT: return
;
; NO-SIMD128-FAST-LABEL: maxnum_one_zero_intrinsic_v4f32:
@@ -12306,17 +12188,15 @@ define <4 x float> @maxnum_one_zero_intrinsic_v4f32(<4 x float> %x, <4 x float>
; NO-SIMD128-FAST-NEXT: f32.const $push0=, -0x1p0
; NO-SIMD128-FAST-NEXT: f32.max $push1=, $1, $pop0
; NO-SIMD128-FAST-NEXT: f32.store 0($0), $pop1
-; NO-SIMD128-FAST-NEXT: f32.const $push9=, -0x1p0
-; NO-SIMD128-FAST-NEXT: f32.max $push2=, $3, $pop9
-; NO-SIMD128-FAST-NEXT: f32.store 8($0), $pop2
-; NO-SIMD128-FAST-NEXT: f32.const $push3=, 0x0p0
-; NO-SIMD128-FAST-NEXT: f32.const $push8=, 0x0p0
-; NO-SIMD128-FAST-NEXT: f32.gt $push4=, $2, $pop8
-; NO-SIMD128-FAST-NEXT: f32.select $push5=, $2, $pop3, $pop4
-; NO-SIMD128-FAST-NEXT: f32.store 4($0), $pop5
+; NO-SIMD128-FAST-NEXT: f32.const $push2=, 0x0p0
+; NO-SIMD128-FAST-NEXT: f32.max $push3=, $2, $pop2
+; NO-SIMD128-FAST-NEXT: f32.store 4($0), $pop3
; NO-SIMD128-FAST-NEXT: f32.const $push7=, -0x1p0
-; NO-SIMD128-FAST-NEXT: f32.max $push6=, $4, $pop7
-; NO-SIMD128-FAST-NEXT: f32.store 12($0), $pop6
+; NO-SIMD128-FAST-NEXT: f32.max $push4=, $3, $pop7
+; NO-SIMD128-FAST-NEXT: f32.store 8($0), $pop4
+; NO-SIMD128-FAST-NEXT: f32.const $push6=, -0x1p0
+; NO-SIMD128-FAST-NEXT: f32.max $push5=, $4, $pop6
+; NO-SIMD128-FAST-NEXT: f32.store 12($0), $pop5
; NO-SIMD128-FAST-NEXT: return
%a = call nnan <4 x float> @llvm.maxnum.v4f32(<4 x float> %x, <4 x float><float -1.0, float 0.0, float -1.0, float -1.0>)
ret <4 x float> %a
diff --git a/llvm/test/CodeGen/WebAssembly/vector-reduce.ll b/llvm/test/CodeGen/WebAssembly/vector-reduce.ll
index 1d194b640eab2..fa3711d6d2ddf 100644
--- a/llvm/test/CodeGen/WebAssembly/vector-reduce.ll
+++ b/llvm/test/CodeGen/WebAssembly/vector-reduce.ll
@@ -792,7 +792,7 @@ define double @pairwise_max_v2f64_fast(<2 x double> %arg) {
; SIMD128: .functype pairwise_max_v2f64_fast (v128) -> (f64)
; SIMD128-NEXT: # %bb.0:
; SIMD128-NEXT: i8x16.shuffle $push0=, $0, $0, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7
-; SIMD128-NEXT: f64x2.pmax $push1=, $0, $pop0
+; SIMD128-NEXT: f64x2.max $push1=, $0, $pop0
; SIMD128-NEXT: f64x2.extract_lane $push2=, $pop1, 0
; SIMD128-NEXT: return $pop2
%res = tail call fast double @llvm.vector.reduce.fmax.v2f64(<2 x double> %arg)
@@ -820,10 +820,10 @@ define float @pairwise_max_v4f32_fast(<4 x float> %arg) {
; SIMD128: .functype pairwise_max_v4f32_fast (v128) -> (f32)
; SIMD128-NEXT: # %bb.0:
; SIMD128-NEXT: i8x16.shuffle $push0=, $0, $0, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 0, 1, 2, 3
-; SIMD128-NEXT: f32x4.pmax $push5=, $0, $pop0
+; SIMD128-NEXT: f32x4.max $push5=, $0, $pop0
; SIMD128-NEXT: local.tee $push4=, $0=, $pop5
; SIMD128-NEXT: i8x16.shuffle $push1=, $0, $0, 4, 5, 6, 7, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3
-; SIMD128-NEXT: f32x4.pmax $push2=, $pop4, $pop1
+; SIMD128-NEXT: f32x4.max $push2=, $pop4, $pop1
; SIMD128-NEXT: f32x4.extract_lane $push3=, $pop2, 0
; SIMD128-NEXT: return $pop3
%res = tail call fast float @llvm.vector.reduce.fmax.v4f32(<4 x float> %arg)
@@ -863,7 +863,7 @@ define double @pairwise_min_v2f64_fast(<2 x double> %arg) {
; SIMD128: .functype pairwise_min_v2f64_fast (v128) -> (f64)
; SIMD128-NEXT: # %bb.0:
; SIMD128-NEXT: i8x16.shuffle $push0=, $0, $0, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7
-; SIMD128-NEXT: f64x2.pmin $push1=, $0, $pop0
+; SIMD128-NEXT: f64x2.min $push1=, $0, $pop0
; SIMD128-NEXT: f64x2.extract_lane $push2=, $pop1, 0
; SIMD128-NEXT: return $pop2
%res = tail call fast double @llvm.vector.reduce.fmin.v2f64(<2 x double> %arg)
@@ -891,10 +891,10 @@ define float @pairwise_min_v4f32_fast(<4 x float> %arg) {
; SIMD128: .functype pairwise_min_v4f32_fast (v128) -> (f32)
; SIMD128-NEXT: # %bb.0:
; SIMD128-NEXT: i8x16.shuffle $push0=, $0, $0, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 0, 1, 2, 3
-; SIMD128-NEXT: f32x4.pmin $push5=, $0, $pop0
+; SIMD128-NEXT: f32x4.min $push5=, $0, $pop0
; SIMD128-NEXT: local.tee $push4=, $0=, $pop5
; SIMD128-NEXT: i8x16.shuffle $push1=, $0, $0, 4, 5, 6, 7, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3
-; SIMD128-NEXT: f32x4.pmin $push2=, $pop4, $pop1
+; SIMD128-NEXT: f32x4.min $push2=, $pop4, $pop1
; SIMD128-NEXT: f32x4.extract_lane $push3=, $pop2, 0
; SIMD128-NEXT: return $pop3
%res = tail call fast float @llvm.vector.reduce.fmin.v4f32(<4 x float> %arg)
>From 5928cfcbf88eaec67c62de5120172ccbbe9296f5 Mon Sep 17 00:00:00 2001
From: YunQiang Su <yunqiang at isrc.iscas.ac.cn>
Date: Sun, 27 Apr 2025 08:35:21 +0800
Subject: [PATCH 2/6] Use FMAXNUM with Custom
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 2ad5d631e94b6..97421c7eb3868 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -11529,11 +11529,11 @@ static SDValue combineMinNumMaxNumImpl(const SDLoc &DL, EVT VT, SDValue LHS,
return DAG.getNode(IEEE2019Opcode, DL, VT, LHS, RHS);
unsigned IEEEOpcode = (LHS == True) ? ISD::FMINNUM_IEEE : ISD::FMAXNUM_IEEE;
- if (TLI.isOperationLegal(IEEEOpcode, VT))
+ if (TLI.isOperationLegalOrCustom(IEEEOpcode, VT))
return DAG.getNode(IEEEOpcode, DL, VT, LHS, RHS);
unsigned Opcode = (LHS == True) ? ISD::FMINNUM : ISD::FMAXNUM;
- if (TLI.isOperationLegal(Opcode, TransformVT))
+ if (TLI.isOperationLegalOrCustom(Opcode, TransformVT))
return DAG.getNode(Opcode, DL, VT, LHS, RHS);
return SDValue();
}
@@ -11553,11 +11553,11 @@ static SDValue combineMinNumMaxNumImpl(const SDLoc &DL, EVT VT, SDValue LHS,
return DAG.getNode(IEEE2019Opcode, DL, VT, LHS, RHS);
unsigned IEEEOpcode = (LHS == True) ? ISD::FMAXNUM_IEEE : ISD::FMINNUM_IEEE;
- if (TLI.isOperationLegal(IEEEOpcode, VT))
+ if (TLI.isOperationLegalOrCustom(IEEEOpcode, VT))
return DAG.getNode(IEEEOpcode, DL, VT, LHS, RHS);
unsigned Opcode = (LHS == True) ? ISD::FMAXNUM : ISD::FMINNUM;
- if (TLI.isOperationLegal(Opcode, TransformVT))
+ if (TLI.isOperationLegalOrCustom(Opcode, TransformVT))
return DAG.getNode(Opcode, DL, VT, LHS, RHS);
return SDValue();
}
>From 7be85ab275ff6bf1baca68dcb79d826d94f0c5c6 Mon Sep 17 00:00:00 2001
From: YunQiang Su <yunqiang at isrc.iscas.ac.cn>
Date: Thu, 11 Dec 2025 11:55:21 +0800
Subject: [PATCH 3/6] Fix Opc legal and custom
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 73 ++--
.../AMDGPU/select-flags-to-fmin-fmax.ll | 364 +++++-------------
2 files changed, 139 insertions(+), 298 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 26c6c5e5d0302..7c020b8e14642 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -11907,7 +11907,16 @@ static bool isLegalToCombineMinNumMaxNum(SelectionDAG &DAG, SDValue LHS,
if (!VT.isFloatingPoint())
return false;
- return Flags.hasNoSignedZeros() &&
+ bool hasMinMaxOpc = (TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT) &&
+ TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT)) ||
+ (TLI.isOperationLegalOrCustom(ISD::FMINNUM_IEEE, VT) &&
+ TLI.isOperationLegalOrCustom(ISD::FMAXNUM_IEEE, VT)) ||
+ (TLI.isOperationLegalOrCustom(ISD::FMINIMUM, VT) &&
+ TLI.isOperationLegalOrCustom(ISD::FMAXIMUM, VT)) ||
+ (TLI.isOperationLegalOrCustom(ISD::FMINIMUMNUM, VT) &&
+ TLI.isOperationLegalOrCustom(ISD::FMAXIMUMNUM, VT));
+
+ return (Flags.hasNoSignedZeros() || hasMinMaxOpc) &&
TLI.isProfitableToCombineMinNumMaxNum(VT) &&
(Flags.hasNoNaNs() ||
(DAG.isKnownNeverNaN(RHS) && DAG.isKnownNeverNaN(LHS)));
@@ -11919,6 +11928,10 @@ static SDValue combineMinNumMaxNumImpl(const SDLoc &DL, EVT VT, SDValue LHS,
const TargetLowering &TLI,
SelectionDAG &DAG) {
EVT TransformVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
+ unsigned IEEE2019NumOpcode = 0;
+ unsigned IEEE2019Opcode = 0;
+ unsigned IEEEOpcode = 0;
+ unsigned Opcode = 0;
switch (CC) {
case ISD::SETOLT:
case ISD::SETOLE:
@@ -11927,49 +11940,53 @@ static SDValue combineMinNumMaxNumImpl(const SDLoc &DL, EVT VT, SDValue LHS,
case ISD::SETULT:
case ISD::SETULE: {
// Since it's known never nan to get here already, either fminimumnum,
- // fminimum, fminnum, or fminnum_ieee are OK. Try the ieee version first,
- // since it's fminnum is expanded in terms of it.
- unsigned IEEE2019NumOpcode =
- (LHS == True) ? ISD::FMINIMUMNUM : ISD::FMAXIMUMNUM;
- if (TLI.isOperationLegal(IEEE2019NumOpcode, VT))
- return DAG.getNode(IEEE2019NumOpcode, DL, VT, LHS, RHS);
-
- unsigned IEEE2019Opcode = (LHS == True) ? ISD::FMINIMUM : ISD::FMAXIMUM;
- if (TLI.isOperationLegal(IEEE2019Opcode, VT))
- return DAG.getNode(IEEE2019Opcode, DL, VT, LHS, RHS);
-
- unsigned IEEEOpcode = (LHS == True) ? ISD::FMINNUM_IEEE : ISD::FMAXNUM_IEEE;
- if (TLI.isOperationLegalOrCustom(IEEEOpcode, VT))
- return DAG.getNode(IEEEOpcode, DL, VT, LHS, RHS);
-
- unsigned Opcode = (LHS == True) ? ISD::FMINNUM : ISD::FMAXNUM;
- if (TLI.isOperationLegalOrCustom(Opcode, TransformVT))
- return DAG.getNode(Opcode, DL, VT, LHS, RHS);
- return SDValue();
+ // fminimum, fminnum, or fminnum_ieee are OK. Try Legal first and then
+ // Custom.
+ IEEE2019NumOpcode = LHS == True ? ISD::FMINIMUMNUM : ISD::FMAXIMUMNUM;
+ IEEE2019Opcode = LHS == True ? ISD::FMINIMUM : ISD::FMAXIMUM;
+ IEEEOpcode = LHS == True ? ISD::FMINNUM_IEEE : ISD::FMAXNUM_IEEE;
+ Opcode = LHS == True ? ISD::FMINNUM : ISD::FMAXNUM;
}
+ [[fallthrough]];
case ISD::SETOGT:
case ISD::SETOGE:
case ISD::SETGT:
case ISD::SETGE:
case ISD::SETUGT:
case ISD::SETUGE: {
- unsigned IEEE2019NumOpcode =
- (LHS == True) ? ISD::FMAXIMUMNUM : ISD::FMINIMUMNUM;
+ if (Opcode == 0) {
+ // Since it's known never nan to get here already, either fminimumnum,
+ // fminimum, fminnum, or fminnum_ieee are OK. Try Legal first and then
+ // Custom.
+ IEEE2019NumOpcode = (LHS == True) ? ISD::FMAXIMUMNUM : ISD::FMINIMUMNUM;
+ IEEE2019Opcode = (LHS == True) ? ISD::FMAXIMUM : ISD::FMINIMUM;
+ IEEEOpcode = (LHS == True) ? ISD::FMAXNUM_IEEE : ISD::FMINNUM_IEEE;
+ Opcode = (LHS == True) ? ISD::FMAXNUM : ISD::FMINNUM;
+ }
+ // Try FMINIMUM/FMAXIMUM first as it has smaller codesize on AMDGPU GFX12.
+ if (TLI.isOperationLegal(IEEE2019Opcode, VT))
+ return DAG.getNode(IEEE2019Opcode, DL, VT, LHS, RHS);
if (TLI.isOperationLegal(IEEE2019NumOpcode, VT))
return DAG.getNode(IEEE2019NumOpcode, DL, VT, LHS, RHS);
+ if (TLI.isOperationLegal(IEEEOpcode, VT))
+ return DAG.getNode(IEEEOpcode, DL, VT, LHS, RHS);
+ if (TLI.isOperationLegal(Opcode, VT))
+ return DAG.getNode(Opcode, DL, VT, LHS, RHS);
- unsigned IEEE2019Opcode = (LHS == True) ? ISD::FMAXIMUM : ISD::FMINIMUM;
- if (TLI.isOperationLegal(IEEE2019Opcode, VT))
+ if (TLI.isOperationCustom(IEEE2019Opcode, VT))
return DAG.getNode(IEEE2019Opcode, DL, VT, LHS, RHS);
-
- unsigned IEEEOpcode = (LHS == True) ? ISD::FMAXNUM_IEEE : ISD::FMINNUM_IEEE;
- if (TLI.isOperationLegalOrCustom(IEEEOpcode, VT))
+ if (TLI.isOperationCustom(IEEE2019NumOpcode, VT))
+ return DAG.getNode(IEEE2019NumOpcode, DL, VT, LHS, RHS);
+ if (TLI.isOperationCustom(IEEEOpcode, VT))
return DAG.getNode(IEEEOpcode, DL, VT, LHS, RHS);
+ if (TLI.isOperationCustom(Opcode, VT))
+ return DAG.getNode(Opcode, DL, VT, LHS, RHS);
- unsigned Opcode = (LHS == True) ? ISD::FMAXNUM : ISD::FMINNUM;
if (TLI.isOperationLegalOrCustom(Opcode, TransformVT))
return DAG.getNode(Opcode, DL, VT, LHS, RHS);
return SDValue();
+
+ return SDValue();
}
default:
return SDValue();
diff --git a/llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll b/llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
index 67b8b3734b321..1ed844a766a55 100644
--- a/llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
@@ -43,14 +43,13 @@ define float @v_test_fmin_legacy_ule_f32_nnan_flag(float %a, float %b) {
; GFX7-LABEL: v_test_fmin_legacy_ule_f32_nnan_flag:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_min_legacy_f32_e32 v0, v1, v0
+; GFX7-NEXT: v_min_f32_e32 v0, v0, v1
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_test_fmin_legacy_ule_f32_nnan_flag:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ngt_f32_e32 vcc, v0, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; GFX9-NEXT: v_min_f32_e32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_test_fmin_legacy_ule_f32_nnan_flag:
@@ -60,9 +59,7 @@ define float @v_test_fmin_legacy_ule_f32_nnan_flag(float %a, float %b) {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v0, v1
-; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX12-NEXT: v_minimum_f32 v0, v0, v1
; GFX12-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp ule float %a, %b
%val = select nnan i1 %cmp, float %a, float %b
@@ -119,7 +116,7 @@ define float @v_test_fmin_legacy_ule_f32_nnan_nsz_flag(float %a, float %b) {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_minimum_f32 v0, v0, v1
+; GFX12-NEXT: v_min_num_f32_e32 v0, v0, v1
; GFX12-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp ule float %a, %b
%val = select nnan nsz i1 %cmp, float %a, float %b
@@ -160,14 +157,13 @@ define float @v_test_fmax_legacy_uge_f32_nnan_flag(float %a, float %b) {
; GFX7-LABEL: v_test_fmax_legacy_uge_f32_nnan_flag:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_max_legacy_f32_e32 v0, v1, v0
+; GFX7-NEXT: v_max_f32_e32 v0, v0, v1
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_test_fmax_legacy_uge_f32_nnan_flag:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_nlt_f32_e32 vcc, v0, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; GFX9-NEXT: v_max_f32_e32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_test_fmax_legacy_uge_f32_nnan_flag:
@@ -177,9 +173,7 @@ define float @v_test_fmax_legacy_uge_f32_nnan_flag(float %a, float %b) {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_cmp_nlt_f32_e32 vcc_lo, v0, v1
-; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX12-NEXT: v_maximum_f32 v0, v0, v1
; GFX12-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp uge float %a, %b
%val = select nnan i1 %cmp, float %a, float %b
@@ -236,7 +230,7 @@ define float @v_test_fmax_legacy_uge_f32_nnan_nsz_flag(float %a, float %b) {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_maximum_f32 v0, v0, v1
+; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v1
; GFX12-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp uge float %a, %b
%val = select nnan nsz i1 %cmp, float %a, float %b
@@ -567,18 +561,17 @@ define half @v_test_fmin_legacy_ule_f16_nnan_flag(half %a, half %b) {
; GFX7-LABEL: v_test_fmin_legacy_ule_f16_nnan_flag:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX7-NEXT: v_min_legacy_f32_e32 v0, v1, v0
+; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX7-NEXT: v_min_f32_e32 v0, v0, v1
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_test_fmin_legacy_ule_f16_nnan_flag:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v0, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; GFX9-NEXT: v_min_f16_e32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: v_test_fmin_legacy_ule_f16_nnan_flag:
@@ -588,9 +581,7 @@ define half @v_test_fmin_legacy_ule_f16_nnan_flag(half %a, half %b) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.l, v1.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_minimum_f16 v0.l, v0.l, v1.l
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_test_fmin_legacy_ule_f16_nnan_flag:
@@ -600,9 +591,7 @@ define half @v_test_fmin_legacy_ule_f16_nnan_flag(half %a, half %b) {
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0, v1
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX12-FAKE16-NEXT: v_minimum_f16 v0, v0, v1
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp ule half %a, %b
%val = select nnan i1 %cmp, half %a, half %b
@@ -679,7 +668,7 @@ define half @v_test_fmin_legacy_ule_f16_nnan_nsz_flag(half %a, half %b) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_minimum_f16 v0.l, v0.l, v1.l
+; GFX12-TRUE16-NEXT: v_min_num_f16_e32 v0.l, v0.l, v1.l
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_test_fmin_legacy_ule_f16_nnan_nsz_flag:
@@ -689,7 +678,7 @@ define half @v_test_fmin_legacy_ule_f16_nnan_nsz_flag(half %a, half %b) {
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_minimum_f16 v0, v0, v1
+; GFX12-FAKE16-NEXT: v_min_num_f16_e32 v0, v0, v1
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp ule half %a, %b
%val = select nnan nsz i1 %cmp, half %a, half %b
@@ -746,18 +735,17 @@ define half @v_test_fmax_legacy_uge_f16_nnan_flag(half %a, half %b) {
; GFX7-LABEL: v_test_fmax_legacy_uge_f16_nnan_flag:
; GFX7: ; %bb.0:
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-NEXT: v_cvt_f32_f16_e32 v1, v1
-; GFX7-NEXT: v_max_legacy_f32_e32 v0, v1, v0
+; GFX7-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX7-NEXT: v_max_f32_e32 v0, v0, v1
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_test_fmax_legacy_uge_f16_nnan_flag:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_nlt_f16_e32 vcc, v0, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
+; GFX9-NEXT: v_max_f16_e32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: v_test_fmax_legacy_uge_f16_nnan_flag:
@@ -767,9 +755,7 @@ define half @v_test_fmax_legacy_uge_f16_nnan_flag(half %a, half %b) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0.l, v1.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_maximum_f16 v0.l, v0.l, v1.l
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_test_fmax_legacy_uge_f16_nnan_flag:
@@ -779,9 +765,7 @@ define half @v_test_fmax_legacy_uge_f16_nnan_flag(half %a, half %b) {
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0, v1
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
+; GFX12-FAKE16-NEXT: v_maximum_f16 v0, v0, v1
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp uge half %a, %b
%val = select nnan i1 %cmp, half %a, half %b
@@ -858,7 +842,7 @@ define half @v_test_fmax_legacy_uge_f16_nnan_nsz_flag(half %a, half %b) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_maximum_f16 v0.l, v0.l, v1.l
+; GFX12-TRUE16-NEXT: v_max_num_f16_e32 v0.l, v0.l, v1.l
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_test_fmax_legacy_uge_f16_nnan_nsz_flag:
@@ -868,7 +852,7 @@ define half @v_test_fmax_legacy_uge_f16_nnan_nsz_flag(half %a, half %b) {
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_maximum_f16 v0, v0, v1
+; GFX12-FAKE16-NEXT: v_max_num_f16_e32 v0, v0, v1
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp uge half %a, %b
%val = select nnan nsz i1 %cmp, half %a, half %b
@@ -963,51 +947,18 @@ define <2 x half> @v_test_fmin_legacy_ule_v2f16_nnan_flag(<2 x half> %a, <2 x ha
; GFX9-LABEL: v_test_fmin_legacy_ule_v2f16_nnan_flag:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v3, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
-; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v0, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
-; GFX9-NEXT: s_mov_b32 s4, 0x5040100
-; GFX9-NEXT: v_perm_b32 v0, v2, v0, s4
+; GFX9-NEXT: v_pk_min_f16 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-TRUE16-LABEL: v_test_fmin_legacy_ule_v2f16_nnan_flag:
-; GFX12-TRUE16: ; %bb.0:
-; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
-; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0.h, v1.h
-; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v0.l, v1.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
-; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-FAKE16-LABEL: v_test_fmin_legacy_ule_v2f16_nnan_flag:
-; GFX12-FAKE16: ; %bb.0:
-; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
-; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
-; GFX12-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0, v1
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
-; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX12-LABEL: v_test_fmin_legacy_ule_v2f16_nnan_flag:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_pk_minimum_f16 v0, v0, v1
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp ule <2 x half> %a, %b
%val = select nnan <2 x i1> %cmp, <2 x half> %a, <2 x half> %b
ret <2 x half> %val
@@ -1111,7 +1062,7 @@ define <2 x half> @v_test_fmin_legacy_ule_v2f16_nnan_nsz_flag(<2 x half> %a, <2
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_pk_minimum_f16 v0, v0, v1
+; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v1
; GFX12-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp ule <2 x half> %a, %b
%val = select nnan nsz <2 x i1> %cmp, <2 x half> %a, <2 x half> %b
@@ -1206,51 +1157,18 @@ define <2 x half> @v_test_fmax_legacy_uge_v2f16_nnan_flag(<2 x half> %a, <2 x ha
; GFX9-LABEL: v_test_fmax_legacy_uge_v2f16_nnan_flag:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX9-NEXT: v_cmp_nlt_f16_e32 vcc, v3, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
-; GFX9-NEXT: v_cmp_nlt_f16_e32 vcc, v0, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
-; GFX9-NEXT: s_mov_b32 s4, 0x5040100
-; GFX9-NEXT: v_perm_b32 v0, v2, v0, s4
+; GFX9-NEXT: v_pk_max_f16 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-TRUE16-LABEL: v_test_fmax_legacy_uge_v2f16_nnan_flag:
-; GFX12-TRUE16: ; %bb.0:
-; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
-; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0.h, v1.h
-; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e64 s0, v0.l, v1.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
-; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-FAKE16-LABEL: v_test_fmax_legacy_uge_v2f16_nnan_flag:
-; GFX12-FAKE16: ; %bb.0:
-; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
-; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v3, v2
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
-; GFX12-FAKE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0, v1
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
-; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX12-LABEL: v_test_fmax_legacy_uge_v2f16_nnan_flag:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_pk_maximum_f16 v0, v0, v1
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp uge <2 x half> %a, %b
%val = select nnan <2 x i1> %cmp, <2 x half> %a, <2 x half> %b
ret <2 x half> %val
@@ -1354,7 +1272,7 @@ define <2 x half> @v_test_fmax_legacy_uge_v2f16_nnan_nsz_flag(<2 x half> %a, <2
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_pk_maximum_f16 v0, v0, v1
+; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v1
; GFX12-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp uge <2 x half> %a, %b
%val = select nnan nsz <2 x i1> %cmp, <2 x half> %a, <2 x half> %b
@@ -1488,70 +1406,32 @@ define <4 x half> @v_test_fmin_legacy_ule_v4f16_nnan_flag(<4 x half> %a, <4 x ha
; GFX9-LABEL: v_test_fmin_legacy_ule_v4f16_nnan_flag:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v3
-; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v7, v6
-; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
-; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v5, v4
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
-; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v1, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; GFX9-NEXT: v_cmp_ngt_f16_e32 vcc, v0, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX9-NEXT: v_pk_min_f16 v4, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v5, 0x7e00
+; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v1, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v6, v5, v4, vcc
+; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v1, v3 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX9-NEXT: v_cndmask_b32_sdwa v1, v5, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX9-NEXT: v_pk_min_f16 v3, v0, v2
+; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v3, vcc
+; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v0, v2 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX9-NEXT: v_cndmask_b32_sdwa v0, v5, v3, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX9-NEXT: s_mov_b32 s4, 0x5040100
-; GFX9-NEXT: v_perm_b32 v0, v4, v0, s4
-; GFX9-NEXT: v_perm_b32 v1, v6, v1, s4
+; GFX9-NEXT: v_perm_b32 v0, v0, v4, s4
+; GFX9-NEXT: v_perm_b32 v1, v1, v6, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-TRUE16-LABEL: v_test_fmin_legacy_ule_v4f16_nnan_flag:
-; GFX12-TRUE16: ; %bb.0:
-; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
-; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v1.h, v3.h
-; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e64 s0, v0.h, v2.h
-; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e64 s1, v0.l, v2.l
-; GFX12-TRUE16-NEXT: v_cmp_ngt_f16_e64 s2, v1.l, v3.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2
-; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-FAKE16-LABEL: v_test_fmin_legacy_ule_v4f16_nnan_flag:
-; GFX12-FAKE16: ; %bb.0:
-; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
-; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v5, v4
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc_lo
-; GFX12-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v7, v6
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc_lo
-; GFX12-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v0, v2
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
-; GFX12-FAKE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, v1, v3
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_perm_b32 v0, v5, v0, 0x5040100
-; GFX12-FAKE16-NEXT: v_perm_b32 v1, v4, v1, 0x5040100
-; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX12-LABEL: v_test_fmin_legacy_ule_v4f16_nnan_flag:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_pk_minimum_f16 v0, v0, v2
+; GFX12-NEXT: v_pk_minimum_f16 v1, v1, v3
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp ule <4 x half> %a, %b
%val = select nnan <4 x i1> %cmp, <4 x half> %a, <4 x half> %b
ret <4 x half> %val
@@ -1684,12 +1564,8 @@ define <4 x half> @v_test_fmin_legacy_ule_v4f16_nnan_nsz_flag(<4 x half> %a, <4
; GFX9-LABEL: v_test_fmin_legacy_ule_v4f16_nnan_nsz_flag:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_pk_max_f16 v2, v2, v2
-; GFX9-NEXT: v_pk_max_f16 v0, v0, v0
; GFX9-NEXT: v_pk_min_f16 v0, v0, v2
-; GFX9-NEXT: v_pk_max_f16 v2, v3, v3
-; GFX9-NEXT: v_pk_max_f16 v1, v1, v1
-; GFX9-NEXT: v_pk_min_f16 v1, v1, v2
+; GFX9-NEXT: v_pk_min_f16 v1, v1, v3
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_test_fmin_legacy_ule_v4f16_nnan_nsz_flag:
@@ -1699,11 +1575,6 @@ define <4 x half> @v_test_fmin_legacy_ule_v4f16_nnan_nsz_flag(<4 x half> %a, <4
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_pk_min_num_f16 v0, v0, v2
; GFX12-NEXT: v_pk_min_num_f16 v1, v1, v3
; GFX12-NEXT: s_setpc_b64 s[30:31]
@@ -1839,70 +1710,32 @@ define <4 x half> @v_test_fmax_legacy_uge_v4f16_nnan_flag(<4 x half> %a, <4 x ha
; GFX9-LABEL: v_test_fmax_legacy_uge_v4f16_nnan_flag:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v3
-; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX9-NEXT: v_cmp_nlt_f16_e32 vcc, v7, v6
-; GFX9-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
-; GFX9-NEXT: v_cmp_nlt_f16_e32 vcc, v5, v4
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
-; GFX9-NEXT: v_cmp_nlt_f16_e32 vcc, v1, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; GFX9-NEXT: v_cmp_nlt_f16_e32 vcc, v0, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX9-NEXT: v_pk_max_f16 v4, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v5, 0x7e00
+; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v1, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v6, v5, v4, vcc
+; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v1, v3 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX9-NEXT: v_cndmask_b32_sdwa v1, v5, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX9-NEXT: v_pk_max_f16 v3, v0, v2
+; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v3, vcc
+; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v0, v2 src0_sel:WORD_1 src1_sel:WORD_1
+; GFX9-NEXT: v_cndmask_b32_sdwa v0, v5, v3, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX9-NEXT: s_mov_b32 s4, 0x5040100
-; GFX9-NEXT: v_perm_b32 v0, v4, v0, s4
-; GFX9-NEXT: v_perm_b32 v1, v6, v1, s4
+; GFX9-NEXT: v_perm_b32 v0, v0, v4, s4
+; GFX9-NEXT: v_perm_b32 v1, v1, v6, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-TRUE16-LABEL: v_test_fmax_legacy_uge_v4f16_nnan_flag:
-; GFX12-TRUE16: ; %bb.0:
-; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
-; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
-; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v1.h, v3.h
-; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e64 s0, v0.h, v2.h
-; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e64 s1, v0.l, v2.l
-; GFX12-TRUE16-NEXT: v_cmp_nlt_f16_e64 s2, v1.l, v3.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v2.h, v0.h, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2
-; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX12-FAKE16-LABEL: v_test_fmax_legacy_uge_v4f16_nnan_flag:
-; GFX12-FAKE16: ; %bb.0:
-; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
-; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
-; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
-; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v5, v4
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc_lo
-; GFX12-FAKE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v7, v6
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc_lo
-; GFX12-FAKE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0, v2
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
-; GFX12-FAKE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v1, v3
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
-; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-FAKE16-NEXT: v_perm_b32 v0, v5, v0, 0x5040100
-; GFX12-FAKE16-NEXT: v_perm_b32 v1, v4, v1, 0x5040100
-; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX12-LABEL: v_test_fmax_legacy_uge_v4f16_nnan_flag:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_pk_maximum_f16 v0, v0, v2
+; GFX12-NEXT: v_pk_maximum_f16 v1, v1, v3
+; GFX12-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp uge <4 x half> %a, %b
%val = select nnan <4 x i1> %cmp, <4 x half> %a, <4 x half> %b
ret <4 x half> %val
@@ -2035,12 +1868,8 @@ define <4 x half> @v_test_fmax_legacy_uge_v4f16_nnan_nsz_flag(<4 x half> %a, <4
; GFX9-LABEL: v_test_fmax_legacy_uge_v4f16_nnan_nsz_flag:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_pk_max_f16 v2, v2, v2
-; GFX9-NEXT: v_pk_max_f16 v0, v0, v0
; GFX9-NEXT: v_pk_max_f16 v0, v0, v2
-; GFX9-NEXT: v_pk_max_f16 v2, v3, v3
-; GFX9-NEXT: v_pk_max_f16 v1, v1, v1
-; GFX9-NEXT: v_pk_max_f16 v1, v1, v2
+; GFX9-NEXT: v_pk_max_f16 v1, v1, v3
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_test_fmax_legacy_uge_v4f16_nnan_nsz_flag:
@@ -2050,11 +1879,6 @@ define <4 x half> @v_test_fmax_legacy_uge_v4f16_nnan_nsz_flag(<4 x half> %a, <4
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_pk_max_num_f16 v2, v2, v2
-; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v0
-; GFX12-NEXT: v_pk_max_num_f16 v3, v3, v3
-; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_pk_max_num_f16 v0, v0, v2
; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v3
; GFX12-NEXT: s_setpc_b64 s[30:31]
>From f2dc53f5e7fc37a9068fd1bcc1ab39dcefbb7e74 Mon Sep 17 00:00:00 2001
From: YunQiang Su <yunqiang at isrc.iscas.ac.cn>
Date: Thu, 11 Dec 2025 12:01:08 +0800
Subject: [PATCH 4/6] Remove duplicated return SDValue();
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 7c020b8e14642..433c157fae85b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -11984,7 +11984,6 @@ static SDValue combineMinNumMaxNumImpl(const SDLoc &DL, EVT VT, SDValue LHS,
if (TLI.isOperationLegalOrCustom(Opcode, TransformVT))
return DAG.getNode(Opcode, DL, VT, LHS, RHS);
- return SDValue();
return SDValue();
}
>From 0fcfa21d6e1155661b1883c7e991c5c2aee98af4 Mon Sep 17 00:00:00 2001
From: YunQiang Su <yunqiang at isrc.iscas.ac.cn>
Date: Thu, 11 Dec 2025 13:56:45 +0800
Subject: [PATCH 5/6] Skip Custom if target has itself combine
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 7 ++
llvm/test/CodeGen/AMDGPU/known-never-nan.ll | 5 +-
llvm/test/CodeGen/ARM/fp16-vminmaxnm-safe.ll | 90 ++++++++-----------
llvm/test/CodeGen/ARM/vminmaxnm-safe.ll | 2 +-
llvm/test/CodeGen/PowerPC/fsel.ll | 6 +-
5 files changed, 48 insertions(+), 62 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 433c157fae85b..1a45548867c6f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -11973,6 +11973,13 @@ static SDValue combineMinNumMaxNumImpl(const SDLoc &DL, EVT VT, SDValue LHS,
if (TLI.isOperationLegal(Opcode, VT))
return DAG.getNode(Opcode, DL, VT, LHS, RHS);
+ // X86 has combineFMinFMax
+ if (TLI.hasTargetDAGCombine((ISD::NodeType)IEEE2019Opcode) ||
+ TLI.hasTargetDAGCombine((ISD::NodeType)IEEE2019NumOpcode) ||
+ TLI.hasTargetDAGCombine((ISD::NodeType)IEEEOpcode) ||
+ TLI.hasTargetDAGCombine((ISD::NodeType)Opcode))
+ return SDValue();
+
if (TLI.isOperationCustom(IEEE2019Opcode, VT))
return DAG.getNode(IEEE2019Opcode, DL, VT, LHS, RHS);
if (TLI.isOperationCustom(IEEE2019NumOpcode, VT))
diff --git a/llvm/test/CodeGen/AMDGPU/known-never-nan.ll b/llvm/test/CodeGen/AMDGPU/known-never-nan.ll
index dc19c48807843..e3e88604603de 100644
--- a/llvm/test/CodeGen/AMDGPU/known-never-nan.ll
+++ b/llvm/test/CodeGen/AMDGPU/known-never-nan.ll
@@ -7,10 +7,9 @@ define half @known_nnan_extract_vector_elt(float %a, float %b, i32 %idx, half %c
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_cvt_pkrtz_f16_f32_e32 v0, v0, v1
; CHECK-NEXT: v_lshlrev_b32_e32 v1, 4, v2
-; CHECK-NEXT: v_add_f16_e32 v2, 1.0, v3
; CHECK-NEXT: v_lshrrev_b32_e32 v0, v1, v0
-; CHECK-NEXT: v_cmp_lt_f16_e32 vcc_lo, v0, v2
-; CHECK-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
+; CHECK-NEXT: v_add_f16_e32 v1, 1.0, v3
+; CHECK-NEXT: v_min_f16_e32 v0, v0, v1
; CHECK-NEXT: s_setpc_b64 s[30:31]
%cvt = call nnan <2 x half> @llvm.amdgcn.cvt.pkrtz(float %a, float %b)
%extract = extractelement <2 x half> %cvt, i32 %idx
diff --git a/llvm/test/CodeGen/ARM/fp16-vminmaxnm-safe.ll b/llvm/test/CodeGen/ARM/fp16-vminmaxnm-safe.ll
index 52fe5ce1a8a5f..7b7a70a2ca5d4 100644
--- a/llvm/test/CodeGen/ARM/fp16-vminmaxnm-safe.ll
+++ b/llvm/test/CodeGen/ARM/fp16-vminmaxnm-safe.ll
@@ -199,13 +199,11 @@ entry:
define half @fp16_vminnm_NNNo(half %a) {
; CHECK-LABEL: fp16_vminnm_NNNo:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov.f16 s0, r0
+; CHECK-NEXT: vldr.16 s0, .LCPI12_0
; CHECK-NEXT: vmov.f16 s2, #1.200000e+01
-; CHECK-NEXT: vminnm.f16 s0, s0, s2
-; CHECK-NEXT: vldr.16 s2, .LCPI12_0
-; CHECK-NEXT: vcmp.f16 s0, s2
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vselgt.f16 s0, s2, s0
+; CHECK-NEXT: vmov.f16 s4, r0
+; CHECK-NEXT: vminnm.f16 s2, s4, s2
+; CHECK-NEXT: vmin.f16 d0, d1, d0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bx lr
; CHECK-NEXT: .p2align 1
@@ -249,13 +247,11 @@ entry:
define half @fp16_vminnm_NNNu(half %b) {
; CHECK-LABEL: fp16_vminnm_NNNu:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov.f16 s0, r0
+; CHECK-NEXT: vldr.16 s0, .LCPI14_0
; CHECK-NEXT: vmov.f16 s2, #1.200000e+01
-; CHECK-NEXT: vminnm.f16 s0, s0, s2
-; CHECK-NEXT: vldr.16 s2, .LCPI14_0
-; CHECK-NEXT: vcmp.f16 s0, s2
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vselge.f16 s0, s2, s0
+; CHECK-NEXT: vmov.f16 s4, r0
+; CHECK-NEXT: vminnm.f16 s2, s4, s2
+; CHECK-NEXT: vmin.f16 d0, d1, d0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bx lr
; CHECK-NEXT: .p2align 1
@@ -273,21 +269,19 @@ entry:
define half @fp16_vminnm_NNNule(half %b) {
; CHECK-LABEL: fp16_vminnm_NNNule:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vldr.16 s2, .LCPI15_0
-; CHECK-NEXT: vmov.f16 s0, r0
-; CHECK-NEXT: vminnm.f16 s0, s0, s2
; CHECK-NEXT: vldr.16 s2, .LCPI15_1
-; CHECK-NEXT: vcmp.f16 s0, s2
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vselgt.f16 s0, s2, s0
+; CHECK-NEXT: vmov.f16 s4, r0
+; CHECK-NEXT: vldr.16 s0, .LCPI15_0
+; CHECK-NEXT: vminnm.f16 s2, s4, s2
+; CHECK-NEXT: vmin.f16 d0, d1, d0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bx lr
; CHECK-NEXT: .p2align 1
; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI15_0:
-; CHECK-NEXT: .short 0x5040 @ half 34
-; CHECK-NEXT: .LCPI15_1:
; CHECK-NEXT: .short 0x5300 @ half 56
+; CHECK-NEXT: .LCPI15_1:
+; CHECK-NEXT: .short 0x5040 @ half 34
entry:
%cmp1 = fcmp ule half 34., %b
@@ -328,13 +322,11 @@ entry:
define half @fp16_vmaxnm_NNNo(half %a) {
; CHECK-LABEL: fp16_vmaxnm_NNNo:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov.f16 s0, r0
+; CHECK-NEXT: vldr.16 s0, .LCPI17_0
; CHECK-NEXT: vmov.f16 s2, #1.200000e+01
-; CHECK-NEXT: vmaxnm.f16 s0, s0, s2
-; CHECK-NEXT: vldr.16 s2, .LCPI17_0
-; CHECK-NEXT: vcmp.f16 s2, s0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vselgt.f16 s0, s2, s0
+; CHECK-NEXT: vmov.f16 s4, r0
+; CHECK-NEXT: vmaxnm.f16 s2, s4, s2
+; CHECK-NEXT: vmax.f16 d0, d1, d0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bx lr
; CHECK-NEXT: .p2align 1
@@ -352,21 +344,19 @@ entry:
define half @fp16_vmaxnm_NNNoge(half %a) {
; CHECK-LABEL: fp16_vmaxnm_NNNoge:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vldr.16 s2, .LCPI18_0
-; CHECK-NEXT: vmov.f16 s0, r0
-; CHECK-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-NEXT: vldr.16 s2, .LCPI18_1
-; CHECK-NEXT: vcmp.f16 s2, s0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vselge.f16 s0, s2, s0
+; CHECK-NEXT: vmov.f16 s4, r0
+; CHECK-NEXT: vldr.16 s0, .LCPI18_0
+; CHECK-NEXT: vmaxnm.f16 s2, s4, s2
+; CHECK-NEXT: vmax.f16 d0, d1, d0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bx lr
; CHECK-NEXT: .p2align 1
; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI18_0:
-; CHECK-NEXT: .short 0x5040 @ half 34
-; CHECK-NEXT: .LCPI18_1:
; CHECK-NEXT: .short 0x5300 @ half 56
+; CHECK-NEXT: .LCPI18_1:
+; CHECK-NEXT: .short 0x5040 @ half 34
entry:
%cmp1 = fcmp oge half %a, 34.
%cond1 = select i1 %cmp1, half %a, half 34.
@@ -430,13 +420,11 @@ entry:
define half @fp16_vmaxnm_NNNu(half %b) {
; CHECK-LABEL: fp16_vmaxnm_NNNu:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov.f16 s0, r0
+; CHECK-NEXT: vldr.16 s0, .LCPI21_0
; CHECK-NEXT: vmov.f16 s2, #1.200000e+01
-; CHECK-NEXT: vmaxnm.f16 s0, s0, s2
-; CHECK-NEXT: vldr.16 s2, .LCPI21_0
-; CHECK-NEXT: vcmp.f16 s2, s0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vselge.f16 s0, s2, s0
+; CHECK-NEXT: vmov.f16 s4, r0
+; CHECK-NEXT: vmaxnm.f16 s2, s4, s2
+; CHECK-NEXT: vmax.f16 d0, d1, d0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bx lr
; CHECK-NEXT: .p2align 1
@@ -454,21 +442,19 @@ entry:
define half @fp16_vmaxnm_NNNuge(half %b) {
; CHECK-LABEL: fp16_vmaxnm_NNNuge:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vldr.16 s2, .LCPI22_0
-; CHECK-NEXT: vmov.f16 s0, r0
-; CHECK-NEXT: vmaxnm.f16 s0, s0, s2
; CHECK-NEXT: vldr.16 s2, .LCPI22_1
-; CHECK-NEXT: vcmp.f16 s2, s0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vselgt.f16 s0, s2, s0
+; CHECK-NEXT: vmov.f16 s4, r0
+; CHECK-NEXT: vldr.16 s0, .LCPI22_0
+; CHECK-NEXT: vmaxnm.f16 s2, s4, s2
+; CHECK-NEXT: vmax.f16 d0, d1, d0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bx lr
; CHECK-NEXT: .p2align 1
; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI22_0:
-; CHECK-NEXT: .short 0x5040 @ half 34
-; CHECK-NEXT: .LCPI22_1:
; CHECK-NEXT: .short 0x5300 @ half 56
+; CHECK-NEXT: .LCPI22_1:
+; CHECK-NEXT: .short 0x5040 @ half 34
entry:
%cmp1 = fcmp uge half 34., %b
%cond1 = select i1 %cmp1, half 34., half %b
@@ -483,9 +469,7 @@ define half @fp16_vminmaxnm_neg0(half %a) {
; CHECK-NEXT: vldr.16 s0, .LCPI23_0
; CHECK-NEXT: vmov.f16 s2, r0
; CHECK-NEXT: vminnm.f16 s2, s2, s0
-; CHECK-NEXT: vcmp.f16 s0, s2
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vselge.f16 s0, s0, s2
+; CHECK-NEXT: vmax.f16 d0, d1, d0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bx lr
; CHECK-NEXT: .p2align 1
@@ -529,9 +513,7 @@ define half @fp16_vminmaxnm_e_neg0(half %a) {
; CHECK-NEXT: vldr.16 s0, .LCPI25_0
; CHECK-NEXT: vmov.f16 s2, r0
; CHECK-NEXT: vminnm.f16 s2, s2, s0
-; CHECK-NEXT: vcmp.f16 s0, s2
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vselge.f16 s0, s0, s2
+; CHECK-NEXT: vmax.f16 d0, d1, d0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bx lr
; CHECK-NEXT: .p2align 1
diff --git a/llvm/test/CodeGen/ARM/vminmaxnm-safe.ll b/llvm/test/CodeGen/ARM/vminmaxnm-safe.ll
index 5577ab49bb830..0df98f35c06e2 100644
--- a/llvm/test/CodeGen/ARM/vminmaxnm-safe.ll
+++ b/llvm/test/CodeGen/ARM/vminmaxnm-safe.ll
@@ -184,7 +184,7 @@ define float @fp-armv8_vminnm_NNNo(float %a) {
define double @fp-armv8_vminnm_NNNole(double %a) {
; CHECK-LABEL: "fp-armv8_vminnm_NNNole":
; CHECK: vminnm.f64
-; CHECK-NOT: vminnm.f64
+; CHECK: vminnm.f64
%cmp1 = fcmp ole double %a, 34.
%cond1 = select nsz i1 %cmp1, double %a, double 34.
%cmp2 = fcmp ole double 56., %cond1
diff --git a/llvm/test/CodeGen/PowerPC/fsel.ll b/llvm/test/CodeGen/PowerPC/fsel.ll
index dea442d8404e1..9425f2f528204 100644
--- a/llvm/test/CodeGen/PowerPC/fsel.ll
+++ b/llvm/test/CodeGen/PowerPC/fsel.ll
@@ -83,8 +83,7 @@ entry:
; CHECK-FM: blr
; CHECK-FM-VSX: @min1
-; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 2, 1
-; CHECK-FM-VSX: fsel 1, [[REG]], 1, 2
+; CHECK-FM-VSX: xsmindp [[REG:[0-9]+]], 1, 2
; CHECK-FM-VSX: blr
}
@@ -104,8 +103,7 @@ entry:
; CHECK-FM: blr
; CHECK-FM-VSX: @max1
-; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 1, 2
-; CHECK-FM-VSX: fsel 1, [[REG]], 1, 2
+; CHECK-FM-VSX: xsmaxdp [[REG:[0-9]+]], 1, 2
; CHECK-FM-VSX: blr
}
>From 89dfc1ad6c5b763d6e4abd9eb41ed6d2a302a221 Mon Sep 17 00:00:00 2001
From: YunQiang Su <yunqiang at isrc.iscas.ac.cn>
Date: Thu, 11 Dec 2025 15:47:50 +0800
Subject: [PATCH 6/6] Update amdgpu tests
---
llvm/test/CodeGen/AMDGPU/fmax_legacy.ll | 5 +-
llvm/test/CodeGen/AMDGPU/fmin_legacy.ll | 5 +-
.../AMDGPU/select-flags-to-fmin-fmax.ll | 132 +++++++++++-------
3 files changed, 88 insertions(+), 54 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/fmax_legacy.ll b/llvm/test/CodeGen/AMDGPU/fmax_legacy.ll
index f3a84e6e45260..f48ce60c4f673 100644
--- a/llvm/test/CodeGen/AMDGPU/fmax_legacy.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmax_legacy.ll
@@ -57,10 +57,9 @@ define amdgpu_kernel void @test_fmax_legacy_uge_f32_fast(ptr addrspace(1) %out,
; GCN-DAG: v_add_f32_e32 [[ADD_A:v[0-9]+]], 1.0, [[A]]
; GCN-DAG: v_add_f32_e32 [[ADD_B:v[0-9]+]], 2.0, [[B]]
-; SI: v_max_legacy_f32_e32 {{v[0-9]+}}, [[ADD_B]], [[ADD_A]]
+; SI: v_max_f32_e32 {{v[0-9]+}}, [[ADD_A]], [[ADD_B]]
-; VI: v_cmp_nlt_f32_e32 vcc, [[ADD_A]], [[ADD_B]]
-; VI: v_cndmask_b32_e32 v{{[0-9]+}}, [[ADD_B]], [[ADD_A]]
+; VI: v_max_f32_e32 v{{[0-9]+}}, [[ADD_A]], [[ADD_B]]
; EG: MAX
diff --git a/llvm/test/CodeGen/AMDGPU/fmin_legacy.ll b/llvm/test/CodeGen/AMDGPU/fmin_legacy.ll
index 39eefa1879870..eb8f8e1d0309e 100644
--- a/llvm/test/CodeGen/AMDGPU/fmin_legacy.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmin_legacy.ll
@@ -81,10 +81,9 @@ define amdgpu_kernel void @s_test_fmin_legacy_ule_f32_fast(ptr addrspace(1) %out
; VI-DAG: v_add_f32_e64 [[ADD_A:v[0-9]+]], s[[#LOAD + 2]], 1.0
; VI-DAG: v_add_f32_e64 [[ADD_B:v[0-9]+]], s[[#LOAD + 3]], 2.0
-; SI: v_min_legacy_f32_e32 {{v[0-9]+}}, [[ADD_B]], [[ADD_A]]
+; SI: v_min_f32_e32 {{v[0-9]+}}, [[ADD_A]], [[ADD_B]]
-; VI: v_cmp_ngt_f32_e32 vcc, [[ADD_A]], [[ADD_B]]
-; VI: v_cndmask_b32_e32 {{v[0-9]+}}, [[ADD_B]], [[ADD_A]], vcc
+; VI: v_min_f32_e32 {{v[0-9]+}}, [[ADD_A]], [[ADD_B]]
define amdgpu_kernel void @s_test_fmin_legacy_ule_f32_nnan_src(ptr addrspace(1) %out, float %a, float %b) #0 {
%a.nnan = fadd nnan float %a, 1.0
%b.nnan = fadd nnan float %b, 2.0
diff --git a/llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll b/llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
index 1ed844a766a55..66f8175041403 100644
--- a/llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
@@ -1406,32 +1406,50 @@ define <4 x half> @v_test_fmin_legacy_ule_v4f16_nnan_flag(<4 x half> %a, <4 x ha
; GFX9-LABEL: v_test_fmin_legacy_ule_v4f16_nnan_flag:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_pk_min_f16 v4, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v5, 0x7e00
-; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v1, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v6, v5, v4, vcc
-; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v1, v3 src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-NEXT: v_cndmask_b32_sdwa v1, v5, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-NEXT: v_pk_min_f16 v3, v0, v2
-; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v3, vcc
-; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v0, v2 src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-NEXT: v_cndmask_b32_sdwa v0, v5, v3, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-NEXT: s_mov_b32 s4, 0x5040100
-; GFX9-NEXT: v_perm_b32 v0, v0, v4, s4
-; GFX9-NEXT: v_perm_b32 v1, v1, v6, s4
+; GFX9-NEXT: v_min_f16_sdwa v4, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX9-NEXT: v_min_f16_sdwa v5, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX9-NEXT: v_min_f16_e32 v1, v1, v3
+; GFX9-NEXT: v_min_f16_e32 v0, v0, v2
+; GFX9-NEXT: v_pack_b32_f16 v0, v0, v5
+; GFX9-NEXT: v_pack_b32_f16 v1, v1, v4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-LABEL: v_test_fmin_legacy_ule_v4f16_nnan_flag:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: s_wait_expcnt 0x0
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: s_wait_bvhcnt 0x0
-; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_pk_minimum_f16 v0, v0, v2
-; GFX12-NEXT: v_pk_minimum_f16 v1, v1, v3
-; GFX12-NEXT: s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_test_fmin_legacy_ule_v4f16_nnan_flag:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_minimum_f16 v1.h, v1.h, v3.h
+; GFX12-TRUE16-NEXT: v_minimum_f16 v0.h, v0.h, v2.h
+; GFX12-TRUE16-NEXT: v_minimum_f16 v0.l, v0.l, v2.l
+; GFX12-TRUE16-NEXT: v_minimum_f16 v1.l, v1.l, v3.l
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
+; GFX12-TRUE16-NEXT: v_pack_b32_f16 v1, v1.l, v1.h
+; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_test_fmin_legacy_ule_v4f16_nnan_flag:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
+; GFX12-FAKE16-NEXT: v_minimum_f16 v1, v1, v3
+; GFX12-FAKE16-NEXT: v_minimum_f16 v0, v0, v2
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-FAKE16-NEXT: v_minimum_f16 v2, v6, v5
+; GFX12-FAKE16-NEXT: v_minimum_f16 v3, v7, v4
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v2
+; GFX12-FAKE16-NEXT: v_pack_b32_f16 v1, v1, v3
+; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp ule <4 x half> %a, %b
%val = select nnan <4 x i1> %cmp, <4 x half> %a, <4 x half> %b
ret <4 x half> %val
@@ -1710,32 +1728,50 @@ define <4 x half> @v_test_fmax_legacy_uge_v4f16_nnan_flag(<4 x half> %a, <4 x ha
; GFX9-LABEL: v_test_fmax_legacy_uge_v4f16_nnan_flag:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_pk_max_f16 v4, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v5, 0x7e00
-; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v1, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v6, v5, v4, vcc
-; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v1, v3 src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-NEXT: v_cndmask_b32_sdwa v1, v5, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-NEXT: v_pk_max_f16 v3, v0, v2
-; GFX9-NEXT: v_cmp_o_f16_e32 vcc, v0, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v3, vcc
-; GFX9-NEXT: v_cmp_o_f16_sdwa vcc, v0, v2 src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-NEXT: v_cndmask_b32_sdwa v0, v5, v3, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-NEXT: s_mov_b32 s4, 0x5040100
-; GFX9-NEXT: v_perm_b32 v0, v0, v4, s4
-; GFX9-NEXT: v_perm_b32 v1, v1, v6, s4
+; GFX9-NEXT: v_max_f16_sdwa v4, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX9-NEXT: v_max_f16_sdwa v5, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX9-NEXT: v_max_f16_e32 v1, v1, v3
+; GFX9-NEXT: v_max_f16_e32 v0, v0, v2
+; GFX9-NEXT: v_pack_b32_f16 v0, v0, v5
+; GFX9-NEXT: v_pack_b32_f16 v1, v1, v4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX12-LABEL: v_test_fmax_legacy_uge_v4f16_nnan_flag:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX12-NEXT: s_wait_expcnt 0x0
-; GFX12-NEXT: s_wait_samplecnt 0x0
-; GFX12-NEXT: s_wait_bvhcnt 0x0
-; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_pk_maximum_f16 v0, v0, v2
-; GFX12-NEXT: v_pk_maximum_f16 v1, v1, v3
-; GFX12-NEXT: s_setpc_b64 s[30:31]
+; GFX12-TRUE16-LABEL: v_test_fmax_legacy_uge_v4f16_nnan_flag:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_maximum_f16 v1.h, v1.h, v3.h
+; GFX12-TRUE16-NEXT: v_maximum_f16 v0.h, v0.h, v2.h
+; GFX12-TRUE16-NEXT: v_maximum_f16 v0.l, v0.l, v2.l
+; GFX12-TRUE16-NEXT: v_maximum_f16 v1.l, v1.l, v3.l
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
+; GFX12-TRUE16-NEXT: v_pack_b32_f16 v1, v1.l, v1.h
+; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-FAKE16-LABEL: v_test_fmax_legacy_uge_v4f16_nnan_flag:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
+; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v1
+; GFX12-FAKE16-NEXT: v_maximum_f16 v1, v1, v3
+; GFX12-FAKE16-NEXT: v_maximum_f16 v0, v0, v2
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-FAKE16-NEXT: v_maximum_f16 v2, v6, v5
+; GFX12-FAKE16-NEXT: v_maximum_f16 v3, v7, v4
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v2
+; GFX12-FAKE16-NEXT: v_pack_b32_f16 v1, v1, v3
+; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = fcmp uge <4 x half> %a, %b
%val = select nnan <4 x i1> %cmp, <4 x half> %a, <4 x half> %b
ret <4 x half> %val
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