[llvm] [LV] Add extra check for signed oveflow for SDiv/SRem (PR #170818)

[Luke Lau via llvm-commits]

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@@ -2878,11 +2878,40 @@ bool LoopVectorizationCostModel::isPredicatedInst(Instruction *I) const {
              TheLoop->isLoopInvariant(cast<StoreInst>(I)->getValueOperand()));
   }
   case Instruction::UDiv:
-  case Instruction::SDiv:
-  case Instruction::SRem:
   case Instruction::URem:
     // If the divisor is loop-invariant no predication is needed.
     return !Legal->isInvariant(I->getOperand(1));
+  case Instruction::SDiv:
+  case Instruction::SRem: {
+    auto *LHS = I->getOperand(0);
+    auto *RHS = I->getOperand(1);
+    ScalarEvolution &SE = *PSE.getSE();
+    auto *LHSSC = SE.getSCEV(LHS);
+    auto *RHSSC = SE.getSCEV(RHS);
+    unsigned Bits = SE.getTypeSizeInBits(LHSSC->getType());
+    APInt MinusOne = APInt::getAllOnes(Bits);
+    bool MayBeNegOne = SE.getSignedRange(RHSSC).contains(MinusOne);
+
+    // No predicate if RHS have no poison in masked-off lanes and not -1.
+    if (isa<SCEVAddRecExpr>(RHSSC) && !MayBeNegOne)
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lukel97 wrote:

Why do we check need to check for `SCEVAddRecExpr`? Does the `Legal->isInvariant` check below not already check if the RHS may have poison in masked-off lanes?

https://github.com/llvm/llvm-project/pull/170818