[llvm] [X86] Attempt to use VPMADD52L/VPMULUDQ instead of VPMULLQ on slow VPMULLQ targets (or when VPMULLQ is unavailable) (PR #171760)

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``````````diff
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 346af7d60..2ad5ee6f6 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -49938,15 +49938,15 @@ static SDValue combineMul(SDNode *N, SelectionDAG &DAG,
     unsigned Count1 = Known1.countMinLeadingZeros();
 
     // Optimization 1: Use VPMULUDQ (32-bit multiply).
-    // If the upper 32 bits are zero, we can use the standard PMULUDQ instruction.
-    // This is generally the fastest option and widely supported.
+    // If the upper 32 bits are zero, we can use the standard PMULUDQ
+    // instruction. This is generally the fastest option and widely supported.
     if (Count0 >= 32 && Count1 >= 32) {
       return DAG.getNode(X86ISD::PMULUDQ, DL, VT, Op0, Op1);
     }
 
     // Optimization 2: Use VPMADD52L (52-bit multiply-add).
-    // On targets with slow VPMULLQ (e.g., Ice Lake), 
-    //VPMADD52L is significantly faster (lower latency/better throughput).
+    // On targets with slow VPMULLQ (e.g., Ice Lake),
+    // VPMADD52L is significantly faster (lower latency/better throughput).
     if (Subtarget.hasAVX512() && Subtarget.hasIFMA()) {
       if (Count0 >= 12 && Count1 >= 12) {
         SDValue Zero = getZeroVector(VT.getSimpleVT(), Subtarget, DAG, DL);

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https://github.com/llvm/llvm-project/pull/171760