[llvm] [AMDGPU][True16] remove pack32 pattern for true16 mode (PR #171756)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 10 19:04:46 PST 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Brox Chen (broxigarchen)
<details>
<summary>Changes</summary>
Remove pack32 so that isel use reg_sequence in true16 mode for build_vector. This generates better code
---
Patch is 157.13 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/171756.diff
41 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/SIInstructions.td (-3)
- (modified) llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll (+6-8)
- (modified) llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll (+28-40)
- (modified) llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll (+8-12)
- (modified) llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll (+34-50)
- (modified) llvm/test/CodeGen/AMDGPU/fdiv.f16.ll (+2-3)
- (modified) llvm/test/CodeGen/AMDGPU/fmaximum3.ll (+1-2)
- (modified) llvm/test/CodeGen/AMDGPU/fminimum3.ll (+1-2)
- (modified) llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll (+28-42)
- (modified) llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll (+11-24)
- (modified) llvm/test/CodeGen/AMDGPU/fpow.ll (+8-16)
- (modified) llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll (+9-21)
- (modified) llvm/test/CodeGen/AMDGPU/fract-match.ll (+8-18)
- (modified) llvm/test/CodeGen/AMDGPU/half.ll (+46-67)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.ceil.f16.ll (+1-2)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll (+1-4)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.floor.f16.ll (+1-2)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.frexp.ll (+28-44)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll (+6-19)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.log.ll (+8-42)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.log10.ll (+8-42)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.log2.ll (-42)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.rint.f16.ll (+5-4)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.round.ll (-2)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll (+1-4)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.trunc.f16.ll (+5-4)
- (modified) llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll (+2-3)
- (modified) llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll (+28-36)
- (modified) llvm/test/CodeGen/AMDGPU/repeated-divisor.ll (+5-14)
- (modified) llvm/test/CodeGen/AMDGPU/roundeven.ll (-8)
- (modified) llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.v2f16.ll (+15-20)
- (modified) llvm/test/CodeGen/AMDGPU/sext-in-reg-vector-shuffle.ll (+16-20)
- (modified) llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll (+11-18)
- (modified) llvm/test/CodeGen/AMDGPU/sitofp.f16.ll (+5-8)
- (modified) llvm/test/CodeGen/AMDGPU/true16-imm-folded-to-0-regression.ll (+3-4)
- (modified) llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll (+11-18)
- (modified) llvm/test/CodeGen/AMDGPU/uitofp.f16.ll (+5-8)
- (modified) llvm/test/CodeGen/AMDGPU/v_pack.ll (+16-24)
- (modified) llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll (+4-6)
- (modified) llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll (+4-6)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 984d1a4db4cd6..4cc66b3a5adee 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -3860,9 +3860,6 @@ let SubtargetPredicate = isGFX9Plus in {
let True16Predicate = NotHasTrue16BitInsts in
def : PackB32Pat<V_PACK_B32_F16_e64>;
-let True16Predicate = UseRealTrue16Insts in
- def : PackB32Pat<V_PACK_B32_F16_t16_e64>;
-
let True16Predicate = UseFakeTrue16Insts in
def : PackB32Pat<V_PACK_B32_F16_fake16_e64>;
} // End SubtargetPredicate = isGFX9Plus
diff --git a/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll b/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
index 0c7dc74d95e49..d1b8a17915adc 100644
--- a/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
+++ b/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
@@ -1848,10 +1848,9 @@ define <2 x half> @fmul_select_v2f16_test3(<2 x half> %x, <2 x i32> %bool.arg1,
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, 0x3c00
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, v1, v3
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v2.l, 0x4000, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.h, v2.l, 0x4000, s0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_pack_b32_f16 v1, v1.h, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.h, v2.l, 0x4000, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v2.l, 0x4000, s0
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_pk_mul_f16 v0, v0, v1
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -2005,10 +2004,9 @@ define <2 x half> @fmul_select_v2f16_test4(<2 x half> %x, <2 x i32> %bool.arg1,
; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, 0x3c00
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, v1, v3
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v2.l, 0x3800, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.h, v2.l, 0x3800, s0
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_pack_b32_f16 v1, v1.h, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.h, v2.l, 0x3800, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v2.l, 0x3800, s0
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_pk_mul_f16 v0, v0, v1
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll b/llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
index 555adecf9c79c..d370ea86e3dc8 100644
--- a/llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
@@ -524,19 +524,16 @@ define <4 x half> @vec_8xf16_extract_4xf16(ptr addrspace(1) %p0, ptr addrspace(1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: .LBB2_3: ; %exit
; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e32 vcc_lo, 0.5, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x3900
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, 0x3900
; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e64 s0, 0.5, v2.h
; GFX11-TRUE16-NEXT: v_cmp_nge_f16_e64 s1, 0.5, v3.l
; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e64 s2, 0.5, v3.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, 0x3d00, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.l, 0x3d00, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, 0x3d00, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.l, 0x3d00, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x3d00, v0.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.l, 0x3d00, s2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_pack_b32_f16 v0, v0.h, v1.l
-; GFX11-TRUE16-NEXT: v_pack_b32_f16 v1, v2.l, v1.h
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x3d00, v1.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, 0x3d00, s2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB2_4:
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5
@@ -1251,19 +1248,16 @@ define <4 x half> @vec_16xf16_extract_4xf16(ptr addrspace(1) %p0, ptr addrspace(
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: .LBB5_3: ; %exit
; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e32 vcc_lo, 0.5, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x3900
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, 0x3900
; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e64 s0, 0.5, v2.h
; GFX11-TRUE16-NEXT: v_cmp_nge_f16_e64 s1, 0.5, v3.l
; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e64 s2, 0.5, v3.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, 0x3d00, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.l, 0x3d00, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, 0x3d00, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v1.l, 0x3d00, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x3d00, v0.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.l, 0x3d00, s2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_pack_b32_f16 v0, v0.h, v1.l
-; GFX11-TRUE16-NEXT: v_pack_b32_f16 v1, v2.l, v1.h
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, 0x3d00, v1.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, 0x3d00, s2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB5_4:
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
@@ -1965,42 +1959,36 @@ define amdgpu_gfx <8 x half> @vec_16xf16_extract_8xf16_0(i1 inreg %cond, ptr add
; GFX11-TRUE16-NEXT: ; %bb.1: ; %F
; GFX11-TRUE16-NEXT: global_load_b128 v[4:7], v[2:3], off offset:16 glc dlc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: global_load_b128 v[2:5], v[2:3], off glc dlc
+; GFX11-TRUE16-NEXT: global_load_b128 v[4:7], v[2:3], off glc dlc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB8_3
; GFX11-TRUE16-NEXT: s_branch .LBB8_4
; GFX11-TRUE16-NEXT: .LBB8_2:
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11
; GFX11-TRUE16-NEXT: .LBB8_3: ; %T
; GFX11-TRUE16-NEXT: global_load_b128 v[2:5], v[0:1], off offset:16 glc dlc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: global_load_b128 v[2:5], v[0:1], off glc dlc
+; GFX11-TRUE16-NEXT: global_load_b128 v[4:7], v[0:1], off glc dlc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: .LBB8_4: ; %exit
+; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e32 vcc_lo, 0.5, v7.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0x3900
+; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e64 s0, 0.5, v6.l
+; GFX11-TRUE16-NEXT: v_cmp_nge_f16_e64 s1, 0.5, v7.h
+; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e64 s2, 0.5, v4.h
+; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e64 s3, 0.5, v5.h
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.h, 0x3d00, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v3.h, 0x3d00, s0
; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e32 vcc_lo, 0.5, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x3900
; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e64 s0, 0.5, v4.l
-; GFX11-TRUE16-NEXT: v_cmp_nge_f16_e64 s1, 0.5, v5.h
-; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e64 s2, 0.5, v2.h
-; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e64 s3, 0.5, v3.h
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v0.l, 0x3d00, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v0.l, 0x3d00, s0
-; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e32 vcc_lo, 0.5, v3.l
-; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e64 s0, 0.5, v2.l
-; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e64 s34, 0.5, v4.h
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v0.l, 0x3d00, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.l, 0x3d00, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.l, 0x3d00, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v0.l, 0x3d00, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v0.l, 0x3d00, s34
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, 0x3d00, v0.l, s1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_pack_b32_f16 v0, v0.h, v1.h
-; GFX11-TRUE16-NEXT: v_pack_b32_f16 v1, v1.l, v2.l
-; GFX11-TRUE16-NEXT: v_pack_b32_f16 v2, v5.l, v2.h
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_pack_b32_f16 v3, v4.l, v3.l
+; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e64 s34, 0.5, v6.h
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.h, 0x3d00, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v3.h, 0x3d00, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.h, 0x3d00, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.h, 0x3d00, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v3.h, 0x3d00, s34
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, 0x3d00, v3.h, s1
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: vec_16xf16_extract_8xf16_0:
diff --git a/llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll b/llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
index da08f4fcf8f3d..2335da7f0abde 100644
--- a/llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
@@ -2568,8 +2568,7 @@ define <2 x half> @v_test_canonicalize_reg_undef_v2f16(half %val) #1 {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, 0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, 0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_test_canonicalize_reg_undef_v2f16:
@@ -2770,8 +2769,7 @@ define <2 x half> @v_test_canonicalize_reg_k_v2f16(half %val) #1 {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, 2.0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, 0x4000
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_test_canonicalize_reg_k_v2f16:
@@ -2813,9 +2811,8 @@ define <2 x half> @v_test_canonicalize_k_reg_v2f16(half %val) #1 {
; GFX11-TRUE16-LABEL: v_test_canonicalize_k_reg_v2f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_pack_b32_f16 v0, 2.0, v0.l
+; GFX11-TRUE16-NEXT: v_max_f16_e32 v0.h, v0.l, v0.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x4000
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_test_canonicalize_k_reg_v2f16:
@@ -2907,10 +2904,9 @@ define <4 x half> @v_test_canonicalize_reg_undef_undef_undef_v4f16(half %val) #1
; GFX11-TRUE16-LABEL: v_test_canonicalize_reg_undef_undef_undef_v4f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, 0
; GFX11-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0x7e007e00
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, 0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_test_canonicalize_reg_undef_undef_undef_v4f16:
@@ -3015,10 +3011,10 @@ define <4 x half> @v_test_canonicalize_reg_undef_reg_reg_v4f16(half %val0, half
; GFX11-TRUE16-LABEL: v_test_canonicalize_reg_undef_reg_reg_v4f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, 0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, 0
+; GFX11-TRUE16-NEXT: v_max_f16_e32 v0.l, v0.l, v0.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_pk_max_f16 v1, v1, v1
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll b/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
index 9a17538ea9b1b..a773bf256bd0a 100644
--- a/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
@@ -3146,11 +3146,10 @@ define <2 x half> @v_copysign_out_v2f16_mag_v2f32_sign_v2f16(<2 x float> %mag, <
; GFX11-TRUE16-LABEL: v_copysign_out_v2f16_mag_v2f32_sign_v2f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v1
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v1.l
-; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v2
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.h, v1
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v1, v2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_copysign_out_v2f16_mag_v2f32_sign_v2f16:
@@ -3653,11 +3652,10 @@ define <2 x half> @v_copysign_out_v2f16_mag_v2f16_sign_v2f32(<2 x half> %mag, <2
; GFX11-TRUE16-LABEL: v_copysign_out_v2f16_mag_v2f16_sign_v2f32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.l, v2
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_pack_b32_f16 v1, v1.l, v2.l
-; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v1
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.h, v2
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.l, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_copysign_out_v2f16_mag_v2f16_sign_v2f32:
@@ -3983,12 +3981,10 @@ define amdgpu_ps i32 @s_copysign_out_v2f16_mag_v2f32_sign_v2f16(<2 x float> inre
;
; GFX11-TRUE16-LABEL: s_copysign_out_v2f16_mag_v2f32_sign_v2f16:
; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, s1
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, s0
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, s1
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_pack_b32_f16 v0, v0.h, v0.l
; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, s2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
@@ -4443,12 +4439,10 @@ define amdgpu_ps i32 @s_copysign_out_v2f16_mag_v2f16_sign_v2f32(<2 x half> inreg
;
; GFX11-TRUE16-LABEL: s_copysign_out_v2f16_mag_v2f16_sign_v2f32:
; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, s2
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, s1
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, s2
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, s1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_pack_b32_f16 v0, v0.h, v0.l
; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, s0, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
@@ -4780,14 +4774,12 @@ define <3 x half> @v_copysign_out_v3f16_mag_v3f32_sign_v3f16(<3 x float> %mag, <
; GFX11-TRUE16-LABEL: v_copysign_out_v3f16_mag_v3f32_sign_v3f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v1
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v1.l
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v2
-; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v1, v4
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.h, v1
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v0
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.l, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v1, v3
+; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v2, v4
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_copysign_out_v3f16_mag_v3f32_sign_v3f16:
@@ -5483,14 +5475,12 @@ define <3 x half> @v_copysign_out_v3f16_mag_v3f16_sign_v3f32(<3 x half> %mag, <3
; GFX11-TRUE16-LABEL: v_copysign_out_v3f16_mag_v3f16_sign_v3f32:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v3.l, v3
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.l, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_pack_b32_f16 v2, v2.l, v3.l
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v3.l, v4
-; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v1, v3
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v3.h, v3
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v3.l, v2
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.l, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v0, v3
+; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v1, v2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_copysign_out_v3f16_mag_v3f16_sign_v3f32:
@@ -5894,16 +5884,13 @@ define <4 x half> @v_copysign_out_v4f16_mag_v4f32_sign_v4f16(<4 x float> %mag, <
; GFX11-TRUE16-LABEL: v_copysign_out_v4f16_mag_v4f32_sign_v4f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v3.l, v3
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v1
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_pack_b32_f16 v1, v0.l, v1.l
-; GFX11-TRUE16-NEXT: v_pack_b32_f16 v2, v0.h, v3.l
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v3.h, v3
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.h, v1
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v0
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v3.l, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff7fff, v1, v4
-; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v2, v5
+; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fff7fff, v3, v5
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_copysign_out_v4f16_mag_v4f32_sign_v4f16:
@@ -...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/171756
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