[llvm] [AMDGPU] Add register pressure guard on LLVM-IR level to prevent harmful optimizations (PR #171267)

[via llvm-commits]

tianhbai wrote:

> I'd rather have the effort put into improving codegen sinking. I do think many of our late sinking problems can be solved by running machine optimizations on gMIR in global isel

Can codegen sinking recognize when IR-level sinking has increased register pressure and counteract the negative effects of IR sinking?


https://github.com/llvm/llvm-project/pull/171267