[llvm] SelectionDAG: Support FMINIMUMNUM and FMINIMUM in combineMinNumMaxNumImpl (PR #137449)

[YunQiang Su via llvm-commits]

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@@ -119,7 +119,7 @@ define float @v_test_fmin_legacy_ule_f32_nnan_nsz_flag(float %a, float %b) {
 ; GFX12-NEXT:    s_wait_samplecnt 0x0
 ; GFX12-NEXT:    s_wait_bvhcnt 0x0
 ; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    v_min_num_f32_e32 v0, v0, v1
+; GFX12-NEXT:    v_minimum_f32 v0, v0, v1
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wzssyqa wrote:

OK. While it is not so simple. RISC-V RV64GC which has no `zfa` extension do support `IEEE2019NumOpcode`, while not `IEEE2019Opcode`.
So we should try all of them with `Legal` and then `Custom`.

In fact I don't think that use `Custom` is a good idea, since the `Custom` operation may work with +0 vs -0, which is not needed here at all.

https://github.com/llvm/llvm-project/pull/137449