[llvm] ba73d60 - [RISCV] Use sew and vec_policy for Rivos vector instruction operands. (#171721)

[via llvm-commits]

Author: Craig Topper
Date: 2025-12-10T17:46:10-08:00
New Revision: ba73d60c43c1c2af5111669f5ec938f1c501fd4a

URL: https://github.com/llvm/llvm-project/commit/ba73d60c43c1c2af5111669f5ec938f1c501fd4a
DIFF: https://github.com/llvm/llvm-project/commit/ba73d60c43c1c2af5111669f5ec938f1c501fd4a.diff

LOG: [RISCV] Use sew and vec_policy for Rivos vector instruction operands. (#171721)

This enables MachineVerifier and MachineIR printing support for these
operands.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
index 3a6ce3ce1d469..39a7aeda94707 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
@@ -156,7 +156,7 @@ foreach m = MxList in {
     let BaseInstr = RI_VEXTRACT in
     def PseudoRI_VEXTRACT_  # mx :
       RISCVVPseudo<(outs GPR:$rd),
-                   (ins m.vrclass:$rs2, uimm5:$idx, ixlenimm:$sew),
+                   (ins m.vrclass:$rs2, uimm5:$idx, sew:$sew),
                    []>;
 
     let HasVLOp = 1, BaseInstr = RI_VINSERT, HasVecPolicyOp = 1,
@@ -164,7 +164,7 @@ foreach m = MxList in {
     def PseudoRI_VINSERT_ # mx :
       RISCVVPseudo<(outs m.vrclass:$rd),
                    (ins m.vrclass:$rs1, GPR:$rs2, uimm5:$idx, AVL:$vl,
-                        ixlenimm:$sew, ixlenimm:$policy),
+                        sew:$sew, vec_policy:$policy),
                    []>;
   }
 }