[llvm] [AMDGPU][GlobalISel] Add RegBankLegalize support for G_FPTRUNC (PR #171723)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 10 14:55:22 PST 2025
https://github.com/vangthao95 created https://github.com/llvm/llvm-project/pull/171723
None
>From 04bfa13437e7e65fd692daff29d4836473fe30ba Mon Sep 17 00:00:00 2001
From: Vang Thao <vthao at amd.com>
Date: Wed, 10 Dec 2025 14:52:28 -0800
Subject: [PATCH] [AMDGPU][GlobalISel] Add RegBankLegalize support for
G_FPTRUNC
---
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 9 +
.../test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll | 585 ++++++++++++++++++
.../GlobalISel/regbankselect-fptrunc.mir | 4 +-
llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll | 353 ++++++++---
llvm/test/CodeGen/AMDGPU/fptrunc.ll | 263 +++++++-
.../AMDGPU/fptrunc.v2f16.no.fast.math.ll | 24 +-
.../test/CodeGen/AMDGPU/vector-reduce-fadd.ll | 16 +-
.../test/CodeGen/AMDGPU/vector-reduce-fmul.ll | 16 +-
8 files changed, 1130 insertions(+), 140 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index abe01e752960f..c5ed63f9fba92 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -983,6 +983,15 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Any({{UniS32, S16}, {{Sgpr32}, {Sgpr16}}}, hasSALUFloat)
.Any({{UniS32, S16}, {{UniInVgprS32}, {Vgpr16}}}, !hasSALUFloat);
+ addRulesForGOpcs({G_FPTRUNC})
+ .Any({{DivS16, S32}, {{Vgpr16}, {Vgpr32}}})
+ .Any({{UniS32, S64}, {{UniInVgprS32}, {Vgpr64}}})
+ .Any({{DivS32, S64}, {{Vgpr32}, {Vgpr64}}})
+ .Any({{UniV2S16, V2S32}, {{UniInVgprV2S16}, {VgprV2S32}}})
+ .Any({{DivV2S16, V2S32}, {{VgprV2S16}, {VgprV2S32}}})
+ .Any({{UniS16, S32}, {{Sgpr16}, {Sgpr32}}}, hasSALUFloat)
+ .Any({{UniS16, S32}, {{UniInVgprS16}, {Vgpr32}}}, !hasSALUFloat);
+
addRulesForGOpcs({G_IS_FPCLASS})
.Any({{DivS1, S16}, {{Vcc}, {Vgpr16}}})
.Any({{UniS1, S16}, {{UniInVcc}, {Vgpr16}}})
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll
new file mode 100644
index 0000000000000..92d54e04599fe
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll
@@ -0,0 +1,585 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mattr=-real-true16 -mcpu=gfx1100 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mattr=+real-true16 -mcpu=gfx1100 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mattr=-real-true16 -mcpu=gfx1200 -o - %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mattr=+real-true16 -mcpu=gfx1200 -o - %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mattr=-real-true16 -mcpu=gfx1250 -o - %s | FileCheck -check-prefixes=GFX1250,GFX1250-FAKE16 %s
+; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mattr=+real-true16 -mcpu=gfx1250 -o - %s | FileCheck -check-prefixes=GFX1250,GFX1250-TRUE16 %s
+
+define amdgpu_ps half @fptrunc_f32_to_f16_uniform(float inreg %a) {
+; GFX11-FAKE16-LABEL: fptrunc_f32_to_f16_uniform:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, s0
+; GFX11-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX11-TRUE16-LABEL: fptrunc_f32_to_f16_uniform:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, s0
+; GFX11-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fptrunc_f32_to_f16_uniform:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_cvt_f16_f32 s0, s0
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: fptrunc_f32_to_f16_uniform:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
+; GFX1250-NEXT: s_cvt_f16_f32 s0, s0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX1250-NEXT: v_mov_b32_e32 v0, s0
+; GFX1250-NEXT: ; return to shader part epilog
+ %result = fptrunc float %a to half
+ ret half %result
+}
+
+define amdgpu_ps half @fptrunc_f32_to_f16_div(float %a) {
+; GFX11-FAKE16-LABEL: fptrunc_f32_to_f16_div:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX11-TRUE16-LABEL: fptrunc_f32_to_f16_div:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: fptrunc_f32_to_f16_div:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX12-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: fptrunc_f32_to_f16_div:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX12-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX1250-FAKE16-LABEL: fptrunc_f32_to_f16_div:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
+; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
+; GFX1250-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX1250-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX1250-TRUE16-LABEL: fptrunc_f32_to_f16_div:
+; GFX1250-TRUE16: ; %bb.0:
+; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
+; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
+; GFX1250-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX1250-TRUE16-NEXT: ; return to shader part epilog
+ %result = fptrunc float %a to half
+ ret half %result
+}
+
+define amdgpu_ps float @fptrunc_f64_to_f32_uniform(double inreg %a) {
+; GFX11-LABEL: fptrunc_f64_to_f32_uniform:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_cvt_f32_f64_e32 v0, s[0:1]
+; GFX11-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fptrunc_f64_to_f32_uniform:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_cvt_f32_f64_e32 v0, s[0:1]
+; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: fptrunc_f64_to_f32_uniform:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
+; GFX1250-NEXT: v_cvt_f32_f64_e32 v0, s[0:1]
+; GFX1250-NEXT: ; return to shader part epilog
+ %result = fptrunc double %a to float
+ ret float %result
+}
+
+define amdgpu_ps float @fptrunc_f64_to_f32_div(double %a) {
+; GFX11-LABEL: fptrunc_f64_to_f32_div:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
+; GFX11-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fptrunc_f64_to_f32_div:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
+; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: fptrunc_f64_to_f32_div:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
+; GFX1250-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
+; GFX1250-NEXT: ; return to shader part epilog
+ %result = fptrunc double %a to float
+ ret float %result
+}
+
+define amdgpu_ps half @fptrunc_f64_to_f16_uniform(double inreg %a) {
+; GFX11-LABEL: fptrunc_f64_to_f16_uniform:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_bfe_u32 s2, s1, 0xb0014
+; GFX11-NEXT: s_lshr_b32 s3, s1, 8
+; GFX11-NEXT: s_and_b32 s4, s1, 0x1ff
+; GFX11-NEXT: s_addk_i32 s2, 0xfc10
+; GFX11-NEXT: s_and_b32 s3, s3, 0xffe
+; GFX11-NEXT: s_or_b32 s0, s4, s0
+; GFX11-NEXT: s_cselect_b32 s0, 1, 0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s0, s3, s0
+; GFX11-NEXT: s_cselect_b32 s3, 1, 0
+; GFX11-NEXT: s_sub_i32 s4, 1, s2
+; GFX11-NEXT: s_or_b32 s5, s0, 0x1000
+; GFX11-NEXT: s_max_i32 s4, s4, 0
+; GFX11-NEXT: s_lshl_b32 s3, s3, 9
+; GFX11-NEXT: s_min_i32 s4, s4, 13
+; GFX11-NEXT: s_lshl_b32 s7, s2, 12
+; GFX11-NEXT: s_lshr_b32 s6, s5, s4
+; GFX11-NEXT: s_or_b32 s3, s3, 0x7c00
+; GFX11-NEXT: s_lshl_b32 s4, s6, s4
+; GFX11-NEXT: s_or_b32 s0, s0, s7
+; GFX11-NEXT: s_cmp_lg_u32 s4, s5
+; GFX11-NEXT: s_cselect_b32 s4, 1, 0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s4, s6, s4
+; GFX11-NEXT: s_cmp_lt_i32 s2, 1
+; GFX11-NEXT: s_cselect_b32 s0, s4, s0
+; GFX11-NEXT: s_and_b32 s4, s0, 7
+; GFX11-NEXT: s_lshr_b32 s0, s0, 2
+; GFX11-NEXT: s_cmp_eq_u32 s4, 3
+; GFX11-NEXT: s_cselect_b32 s5, 1, 0
+; GFX11-NEXT: s_cmp_gt_i32 s4, 5
+; GFX11-NEXT: s_cselect_b32 s4, 1, 0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s4, s5, s4
+; GFX11-NEXT: s_cmp_lg_u32 s4, 0
+; GFX11-NEXT: s_cselect_b32 s4, 1, 0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_add_i32 s0, s0, s4
+; GFX11-NEXT: s_cmp_gt_i32 s2, 30
+; GFX11-NEXT: s_cselect_b32 s0, 0x7c00, s0
+; GFX11-NEXT: s_cmpk_eq_i32 s2, 0x40f
+; GFX11-NEXT: s_cselect_b32 s0, s3, s0
+; GFX11-NEXT: s_lshr_b32 s1, s1, 16
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_and_b32 s1, s1, 0x8000
+; GFX11-NEXT: s_or_b32 s0, s1, s0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fptrunc_f64_to_f16_uniform:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_bfe_u32 s2, s1, 0xb0014
+; GFX12-NEXT: s_lshr_b32 s3, s1, 8
+; GFX12-NEXT: s_and_b32 s4, s1, 0x1ff
+; GFX12-NEXT: s_addk_co_i32 s2, 0xfc10
+; GFX12-NEXT: s_and_b32 s3, s3, 0xffe
+; GFX12-NEXT: s_or_b32 s0, s4, s0
+; GFX12-NEXT: s_cselect_b32 s0, 1, 0
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: s_or_b32 s0, s3, s0
+; GFX12-NEXT: s_cselect_b32 s3, 1, 0
+; GFX12-NEXT: s_sub_co_i32 s4, 1, s2
+; GFX12-NEXT: s_or_b32 s5, s0, 0x1000
+; GFX12-NEXT: s_max_i32 s4, s4, 0
+; GFX12-NEXT: s_lshl_b32 s3, s3, 9
+; GFX12-NEXT: s_min_i32 s4, s4, 13
+; GFX12-NEXT: s_lshl_b32 s7, s2, 12
+; GFX12-NEXT: s_lshr_b32 s6, s5, s4
+; GFX12-NEXT: s_or_b32 s3, s3, 0x7c00
+; GFX12-NEXT: s_lshl_b32 s4, s6, s4
+; GFX12-NEXT: s_or_b32 s0, s0, s7
+; GFX12-NEXT: s_cmp_lg_u32 s4, s5
+; GFX12-NEXT: s_cselect_b32 s4, 1, 0
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX12-NEXT: s_or_b32 s4, s6, s4
+; GFX12-NEXT: s_cmp_lt_i32 s2, 1
+; GFX12-NEXT: s_cselect_b32 s0, s4, s0
+; GFX12-NEXT: s_and_b32 s4, s0, 7
+; GFX12-NEXT: s_lshr_b32 s0, s0, 2
+; GFX12-NEXT: s_cmp_eq_u32 s4, 3
+; GFX12-NEXT: s_cselect_b32 s5, 1, 0
+; GFX12-NEXT: s_cmp_gt_i32 s4, 5
+; GFX12-NEXT: s_cselect_b32 s4, 1, 0
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX12-NEXT: s_or_b32 s4, s5, s4
+; GFX12-NEXT: s_cmp_lg_u32 s4, 0
+; GFX12-NEXT: s_cselect_b32 s4, 1, 0
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: s_add_co_i32 s0, s0, s4
+; GFX12-NEXT: s_cmp_gt_i32 s2, 30
+; GFX12-NEXT: s_cselect_b32 s0, 0x7c00, s0
+; GFX12-NEXT: s_cmp_eq_u32 s2, 0x40f
+; GFX12-NEXT: s_cselect_b32 s0, s3, s0
+; GFX12-NEXT: s_lshr_b32 s1, s1, 16
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX12-NEXT: s_and_b32 s1, s1, 0x8000
+; GFX12-NEXT: s_or_b32 s0, s1, s0
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: fptrunc_f64_to_f16_uniform:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
+; GFX1250-NEXT: s_bfe_u32 s2, s1, 0xb0014
+; GFX1250-NEXT: s_lshr_b32 s3, s1, 8
+; GFX1250-NEXT: s_and_b32 s4, s1, 0x1ff
+; GFX1250-NEXT: s_addk_co_i32 s2, 0xfc10
+; GFX1250-NEXT: s_and_b32 s3, s3, 0xffe
+; GFX1250-NEXT: s_or_b32 s0, s4, s0
+; GFX1250-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT: s_or_b32 s0, s3, s0
+; GFX1250-NEXT: s_cselect_b32 s3, 1, 0
+; GFX1250-NEXT: s_sub_co_i32 s4, 1, s2
+; GFX1250-NEXT: s_or_b32 s5, s0, 0x1000
+; GFX1250-NEXT: s_max_i32 s4, s4, 0
+; GFX1250-NEXT: s_lshl_b32 s3, s3, 9
+; GFX1250-NEXT: s_min_i32 s4, s4, 13
+; GFX1250-NEXT: s_lshl_b32 s7, s2, 12
+; GFX1250-NEXT: s_lshr_b32 s6, s5, s4
+; GFX1250-NEXT: s_or_b32 s3, s3, 0x7c00
+; GFX1250-NEXT: s_lshl_b32 s4, s6, s4
+; GFX1250-NEXT: s_or_b32 s0, s0, s7
+; GFX1250-NEXT: s_cmp_lg_u32 s4, s5
+; GFX1250-NEXT: s_cselect_b32 s4, 1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_or_b32 s4, s6, s4
+; GFX1250-NEXT: s_cmp_lt_i32 s2, 1
+; GFX1250-NEXT: s_cselect_b32 s0, s4, s0
+; GFX1250-NEXT: s_and_b32 s4, s0, 7
+; GFX1250-NEXT: s_lshr_b32 s0, s0, 2
+; GFX1250-NEXT: s_cmp_eq_u32 s4, 3
+; GFX1250-NEXT: s_cselect_b32 s5, 1, 0
+; GFX1250-NEXT: s_cmp_gt_i32 s4, 5
+; GFX1250-NEXT: s_cselect_b32 s4, 1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_or_b32 s4, s5, s4
+; GFX1250-NEXT: s_cmp_lg_u32 s4, 0
+; GFX1250-NEXT: s_cselect_b32 s4, 1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT: s_add_co_i32 s0, s0, s4
+; GFX1250-NEXT: s_cmp_gt_i32 s2, 30
+; GFX1250-NEXT: s_cselect_b32 s0, 0x7c00, s0
+; GFX1250-NEXT: s_cmp_eq_u32 s2, 0x40f
+; GFX1250-NEXT: s_cselect_b32 s0, s3, s0
+; GFX1250-NEXT: s_lshr_b32 s1, s1, 16
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_and_b32 s1, s1, 0x8000
+; GFX1250-NEXT: s_or_b32 s0, s1, s0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT: v_mov_b32_e32 v0, s0
+; GFX1250-NEXT: ; return to shader part epilog
+ %result = fptrunc double %a to half
+ ret half %result
+}
+
+define amdgpu_ps half @fptrunc_f64_to_f16_div(double %a) {
+; GFX11-LABEL: fptrunc_f64_to_f16_div:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_and_or_b32 v0, 0x1ff, v1, v0
+; GFX11-NEXT: v_bfe_u32 v2, v1, 20, 11
+; GFX11-NEXT: v_lshrrev_b32_e32 v3, 8, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX11-NEXT: v_add_nc_u32_e32 v2, 0xfffffc10, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_sub_nc_u32_e32 v4, 1, v2
+; GFX11-NEXT: v_and_or_b32 v0, 0xffe, v3, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_med3_i32 v3, v4, 0, 13
+; GFX11-NEXT: v_or_b32_e32 v4, 0x1000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshrrev_b32_e32 v5, v3, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v3, v3, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, v3, v4
+; GFX11-NEXT: v_lshl_or_b32 v4, v2, 12, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v2
+; GFX11-NEXT: v_or_b32_e32 v3, v5, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
+; GFX11-NEXT: v_and_b32_e32 v4, 7, v3
+; GFX11-NEXT: v_lshrrev_b32_e32 v3, 2, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v4
+; GFX11-NEXT: v_cmp_lt_i32_e64 s0, 5, v4
+; GFX11-NEXT: s_or_b32 s0, vcc_lo, s0
+; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_add_nc_u32_e32 v3, v3, v4
+; GFX11-NEXT: v_cmp_lt_i32_e32 vcc_lo, 30, v2
+; GFX11-NEXT: v_lshl_or_b32 v0, v0, 9, 0x7c00
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, 0x7c00, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v2
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_and_or_b32 v0, 0x8000, v1, v0
+; GFX11-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fptrunc_f64_to_f16_div:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_and_or_b32 v0, 0x1ff, v1, v0
+; GFX12-NEXT: v_bfe_u32 v2, v1, 20, 11
+; GFX12-NEXT: v_lshrrev_b32_e32 v3, 8, v1
+; GFX12-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX12-NEXT: v_add_nc_u32_e32 v2, 0xfffffc10, v2
+; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-NEXT: v_sub_nc_u32_e32 v4, 1, v2
+; GFX12-NEXT: v_and_or_b32 v0, 0xffe, v3, v0
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-NEXT: v_med3_i32 v3, v4, 0, 13
+; GFX12-NEXT: v_or_b32_e32 v4, 0x1000, v0
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-NEXT: v_lshrrev_b32_e32 v5, v3, v4
+; GFX12-NEXT: v_lshlrev_b32_e32 v3, v3, v5
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX12-NEXT: v_cmp_ne_u32_e32 vcc_lo, v3, v4
+; GFX12-NEXT: v_lshl_or_b32 v4, v2, 12, v0
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; GFX12-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v2
+; GFX12-NEXT: v_or_b32_e32 v3, v5, v3
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
+; GFX12-NEXT: v_and_b32_e32 v4, 7, v3
+; GFX12-NEXT: v_lshrrev_b32_e32 v3, 2, v3
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v4
+; GFX12-NEXT: v_cmp_lt_i32_e64 s0, 5, v4
+; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
+; GFX12-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX12-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX12-NEXT: v_add_nc_u32_e32 v3, v3, v4
+; GFX12-NEXT: v_cmp_lt_i32_e32 vcc_lo, 30, v2
+; GFX12-NEXT: v_lshl_or_b32 v0, v0, 9, 0x7c00
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX12-NEXT: v_cndmask_b32_e64 v3, v3, 0x7c00, vcc_lo
+; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v2
+; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_and_or_b32 v0, 0x8000, v1, v0
+; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: fptrunc_f64_to_f16_div:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
+; GFX1250-NEXT: v_and_or_b32 v0, 0x1ff, v1, v0
+; GFX1250-NEXT: v_bfe_u32 v2, v1, 20, 11
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX1250-NEXT: v_add_nc_u32_e32 v2, 0xfffffc10, v2
+; GFX1250-NEXT: v_dual_lshrrev_b32 v3, 8, v1 :: v_dual_lshrrev_b32 v1, 16, v1
+; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_sub_nc_u32_e32 v4, 1, v2
+; GFX1250-NEXT: v_and_or_b32 v0, 0xffe, v3, v0
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_med3_i32 v3, v4, 0, 13
+; GFX1250-NEXT: v_or_b32_e32 v4, 0x1000, v0
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-NEXT: v_lshrrev_b32_e32 v5, v3, v4
+; GFX1250-NEXT: v_lshlrev_b32_e32 v3, v3, v5
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_cmp_ne_u32_e32 vcc_lo, v3, v4
+; GFX1250-NEXT: v_lshl_or_b32 v4, v2, 12, v0
+; GFX1250-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; GFX1250-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v2
+; GFX1250-NEXT: v_or_b32_e32 v3, v5, v3
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
+; GFX1250-NEXT: v_dual_lshrrev_b32 v3, 2, v3 :: v_dual_bitop2_b32 v4, 7, v3 bitop3:0x40
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v4
+; GFX1250-NEXT: v_cmp_lt_i32_e64 s0, 5, v4
+; GFX1250-NEXT: s_or_b32 s0, vcc_lo, s0
+; GFX1250-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX1250-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
+; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1250-NEXT: v_add_nc_u32_e32 v3, v3, v4
+; GFX1250-NEXT: v_cmp_lt_i32_e32 vcc_lo, 30, v2
+; GFX1250-NEXT: v_lshl_or_b32 v0, v0, 9, 0x7c00
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_cndmask_b32_e64 v3, v3, 0x7c00, vcc_lo
+; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v2
+; GFX1250-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_and_or_b32 v0, 0x8000, v1, v0
+; GFX1250-NEXT: ; return to shader part epilog
+ %result = fptrunc double %a to half
+ ret half %result
+}
+
+define amdgpu_ps <2 x half> @fptrunc_v2f32_to_v2f16_uniform(<2 x float> inreg %a) {
+; GFX11-FAKE16-LABEL: fptrunc_v2f32_to_v2f16_uniform:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, s0
+; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, s1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s1, v1
+; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s0, s0, s1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX11-TRUE16-LABEL: fptrunc_v2f32_to_v2f16_uniform:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, s0
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, s1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s1, v1
+; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12-LABEL: fptrunc_v2f32_to_v2f16_uniform:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_cvt_f16_f32 s0, s0
+; GFX12-NEXT: s_cvt_f16_f32 s1, s1
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX12-NEXT: s_pack_ll_b32_b16 s0, s0, s1
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: fptrunc_v2f32_to_v2f16_uniform:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
+; GFX1250-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_cvt_pk_f16_f32 v0, v0, v1
+; GFX1250-NEXT: ; return to shader part epilog
+ %result = fptrunc <2 x float> %a to <2 x half>
+ ret <2 x half> %result
+}
+
+define amdgpu_ps <2 x half> @fptrunc_v2f32_to_v2f16_div(<2 x float> %a) {
+; GFX11-FAKE16-LABEL: fptrunc_v2f32_to_v2f16_div:
+; GFX11-FAKE16: ; %bb.0:
+; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX11-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX11-TRUE16-LABEL: fptrunc_v2f32_to_v2f16_div:
+; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: fptrunc_v2f32_to_v2f16_div:
+; GFX12-FAKE16: ; %bb.0:
+; GFX12-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX12-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX12-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: fptrunc_v2f32_to_v2f16_div:
+; GFX12-TRUE16: ; %bb.0:
+; GFX12-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX12-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
+; GFX12-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX1250-LABEL: fptrunc_v2f32_to_v2f16_div:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
+; GFX1250-NEXT: v_cvt_pk_f16_f32 v0, v0, v1
+; GFX1250-NEXT: ; return to shader part epilog
+ %result = fptrunc <2 x float> %a to <2 x half>
+ ret <2 x half> %result
+}
+
+define amdgpu_ps void @fptrunc_v2f64_to_v2f32_uniform(<2 x double> inreg %a, ptr addrspace(1) %ptr) {
+; GFX11-LABEL: fptrunc_v2f64_to_v2f32_uniform:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_cvt_f32_f64_e32 v2, s[0:1]
+; GFX11-NEXT: v_cvt_f32_f64_e32 v3, s[2:3]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_readfirstlane_b32 s0, v2
+; GFX11-NEXT: v_readfirstlane_b32 s1, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX11-NEXT: global_store_b64 v[0:1], v[2:3], off
+; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fptrunc_v2f64_to_v2f32_uniform:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_cvt_f32_f64_e32 v2, s[0:1]
+; GFX12-NEXT: v_cvt_f32_f64_e32 v3, s[2:3]
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-NEXT: v_readfirstlane_b32 s0, v2
+; GFX12-NEXT: v_readfirstlane_b32 s1, v3
+; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX12-NEXT: global_store_b64 v[0:1], v[2:3], off
+; GFX12-NEXT: s_endpgm
+;
+; GFX1250-LABEL: fptrunc_v2f64_to_v2f32_uniform:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
+; GFX1250-NEXT: v_cvt_f32_f64_e32 v2, s[0:1]
+; GFX1250-NEXT: v_cvt_f32_f64_e32 v3, s[2:3]
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_readfirstlane_b32 s0, v2
+; GFX1250-NEXT: v_readfirstlane_b32 s1, v3
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1250-NEXT: global_store_b64 v[0:1], v[2:3], off
+; GFX1250-NEXT: s_endpgm
+ %result = fptrunc <2 x double> %a to <2 x float>
+ store <2 x float> %result, ptr addrspace(1) %ptr
+ ret void
+}
+
+define amdgpu_ps void @fptrunc_v2f64_to_v2f32_div(<2 x double> %a, ptr addrspace(1) %ptr) {
+; GFX11-LABEL: fptrunc_v2f64_to_v2f32_div:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
+; GFX11-NEXT: v_cvt_f32_f64_e32 v1, v[2:3]
+; GFX11-NEXT: global_store_b64 v[4:5], v[0:1], off
+; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: fptrunc_v2f64_to_v2f32_div:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
+; GFX12-NEXT: v_cvt_f32_f64_e32 v1, v[2:3]
+; GFX12-NEXT: global_store_b64 v[4:5], v[0:1], off
+; GFX12-NEXT: s_endpgm
+;
+; GFX1250-LABEL: fptrunc_v2f64_to_v2f32_div:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1
+; GFX1250-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
+; GFX1250-NEXT: v_cvt_f32_f64_e32 v1, v[2:3]
+; GFX1250-NEXT: global_store_b64 v[4:5], v[0:1], off
+; GFX1250-NEXT: s_endpgm
+ %result = fptrunc <2 x double> %a to <2 x float>
+ store <2 x float> %result, ptr addrspace(1) %ptr
+ ret void
+}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir
index 53147d8435ea7..5fcda87db6abe 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
-# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: fptrunc_s
diff --git a/llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll b/llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
index 657e35a90a9a5..3fdf41ba93751 100644
--- a/llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
@@ -1,20 +1,20 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -global-isel=0 < %s | FileCheck -enable-var-scope -check-prefixes=SI-SDAG %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -global-isel=1 < %s | FileCheck -check-prefixes=SI-GISEL %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=SI-GISEL %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=fiji -global-isel=0 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=VI-SDAG %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=fiji -global-isel=1 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=VI-GISEL %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=fiji -global-isel=1 -new-reg-bank-select -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=VI-GISEL %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx900 -global-isel=0 -mattr=-flat-for-global -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX9-SDAG %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx900 -global-isel=1 -mattr=-flat-for-global -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX9-GISEL %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx900 -global-isel=1 -new-reg-bank-select -mattr=-flat-for-global -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX9-GISEL %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx950 -global-isel=0 -mattr=-flat-for-global -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX950-SDAG %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx950 -global-isel=1 -mattr=-flat-for-global -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX950-GISEL %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx950 -global-isel=1 -new-reg-bank-select -mattr=-flat-for-global -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX950-GISEL %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=-flat-for-global,+real-true16 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX11-SDAG-TRUE16 %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=-flat-for-global,-real-true16 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX11-SDAG-FAKE16 %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -mattr=-flat-for-global,+real-true16 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX11-GISEL-TRUE16 %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -mattr=-flat-for-global,-real-true16 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX11-GISEL-FAKE16 %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=-flat-for-global,+real-true16 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX11-GISEL-TRUE16 %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=-flat-for-global,-real-true16 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX11-GISEL-FAKE16 %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1250 -global-isel=0 -mattr=-flat-for-global,+real-true16 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX1250-SDAG-TRUE16 %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1250 -global-isel=0 -mattr=-flat-for-global,-real-true16 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX1250-SDAG-FAKE16 %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1250 -global-isel=1 -mattr=-flat-for-global,+real-true16 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX1250-GISEL-TRUE16 %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1250 -global-isel=1 -mattr=-flat-for-global,-real-true16 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX1250-GISEL-FAKE16 %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1250 -global-isel=1 -new-reg-bank-select -mattr=-flat-for-global,+real-true16 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX1250-GISEL-TRUE16 %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1250 -global-isel=1 -new-reg-bank-select -mattr=-flat-for-global,-real-true16 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX1250-GISEL-FAKE16 %s
define amdgpu_kernel void @fptrunc_f32_to_f16(
; SI-SDAG-LABEL: fptrunc_f32_to_f16:
@@ -618,13 +618,13 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(
; SI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
; SI-GISEL-NEXT: s_or_b32 s4, s6, s4
; SI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
-; SI-GISEL-NEXT: s_lshl_b32 s6, s6, 9
; SI-GISEL-NEXT: s_lshl_b32 s7, s3, 12
; SI-GISEL-NEXT: s_sub_i32 s8, 1, s3
; SI-GISEL-NEXT: s_or_b32 s9, s4, 0x1000
-; SI-GISEL-NEXT: s_or_b32 s6, s6, 0x7c00
+; SI-GISEL-NEXT: s_lshl_b32 s6, s6, 9
; SI-GISEL-NEXT: s_or_b32 s4, s4, s7
; SI-GISEL-NEXT: s_max_i32 s7, s8, 0
+; SI-GISEL-NEXT: s_or_b32 s6, s6, 0x7c00
; SI-GISEL-NEXT: s_min_i32 s7, s7, 13
; SI-GISEL-NEXT: s_lshr_b32 s8, s9, s7
; SI-GISEL-NEXT: s_lshl_b32 s7, s8, s7
@@ -640,6 +640,8 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(
; SI-GISEL-NEXT: s_cmp_gt_i32 s7, 5
; SI-GISEL-NEXT: s_cselect_b32 s7, 1, 0
; SI-GISEL-NEXT: s_or_b32 s7, s8, s7
+; SI-GISEL-NEXT: s_cmp_lg_u32 s7, 0
+; SI-GISEL-NEXT: s_cselect_b32 s7, 1, 0
; SI-GISEL-NEXT: s_add_i32 s4, s4, s7
; SI-GISEL-NEXT: s_cmp_gt_i32 s3, 30
; SI-GISEL-NEXT: s_cselect_b32 s4, 0x7c00, s4
@@ -750,6 +752,8 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(
; VI-GISEL-NEXT: s_cmp_gt_i32 s6, 5
; VI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
; VI-GISEL-NEXT: s_or_b32 s6, s7, s6
+; VI-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
; VI-GISEL-NEXT: s_add_i32 s2, s2, s6
; VI-GISEL-NEXT: s_cmp_gt_i32 s4, 30
; VI-GISEL-NEXT: s_cselect_b32 s2, 0x7c00, s2
@@ -861,6 +865,8 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(
; GFX9-GISEL-NEXT: s_cmp_gt_i32 s6, 5
; GFX9-GISEL-NEXT: s_cselect_b32 s6, 1, 0
; GFX9-GISEL-NEXT: s_or_b32 s6, s7, s6
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s6, 1, 0
; GFX9-GISEL-NEXT: s_add_i32 s2, s2, s6
; GFX9-GISEL-NEXT: s_cmp_gt_i32 s4, 30
; GFX9-GISEL-NEXT: s_cselect_b32 s2, 0x7c00, s2
@@ -972,6 +978,8 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(
; GFX950-GISEL-NEXT: s_cmp_gt_i32 s6, 5
; GFX950-GISEL-NEXT: s_cselect_b32 s6, 1, 0
; GFX950-GISEL-NEXT: s_or_b32 s6, s7, s6
+; GFX950-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; GFX950-GISEL-NEXT: s_cselect_b32 s6, 1, 0
; GFX950-GISEL-NEXT: s_add_i32 s2, s2, s6
; GFX950-GISEL-NEXT: s_cmp_gt_i32 s4, 30
; GFX950-GISEL-NEXT: s_cselect_b32 s2, 0x7c00, s2
@@ -1160,6 +1168,9 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(
; GFX11-GISEL-TRUE16-NEXT: s_cselect_b32 s6, 1, 0
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-GISEL-TRUE16-NEXT: s_or_b32 s6, s7, s6
+; GFX11-GISEL-TRUE16-NEXT: s_cmp_lg_u32 s6, 0
+; GFX11-GISEL-TRUE16-NEXT: s_cselect_b32 s6, 1, 0
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-GISEL-TRUE16-NEXT: s_add_i32 s2, s2, s6
; GFX11-GISEL-TRUE16-NEXT: s_cmp_gt_i32 s4, 30
; GFX11-GISEL-TRUE16-NEXT: s_cselect_b32 s2, 0x7c00, s2
@@ -1215,6 +1226,9 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(
; GFX11-GISEL-FAKE16-NEXT: s_cselect_b32 s6, 1, 0
; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-GISEL-FAKE16-NEXT: s_or_b32 s6, s7, s6
+; GFX11-GISEL-FAKE16-NEXT: s_cmp_lg_u32 s6, 0
+; GFX11-GISEL-FAKE16-NEXT: s_cselect_b32 s6, 1, 0
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-GISEL-FAKE16-NEXT: s_add_i32 s2, s2, s6
; GFX11-GISEL-FAKE16-NEXT: s_cmp_gt_i32 s4, 30
; GFX11-GISEL-FAKE16-NEXT: s_cselect_b32 s2, 0x7c00, s2
@@ -1407,6 +1421,9 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(
; GFX1250-GISEL-TRUE16-NEXT: s_cselect_b32 s6, 1, 0
; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1250-GISEL-TRUE16-NEXT: s_or_b32 s6, s7, s6
+; GFX1250-GISEL-TRUE16-NEXT: s_cmp_lg_u32 s6, 0
+; GFX1250-GISEL-TRUE16-NEXT: s_cselect_b32 s6, 1, 0
+; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-GISEL-TRUE16-NEXT: s_add_co_i32 s2, s2, s6
; GFX1250-GISEL-TRUE16-NEXT: s_cmp_gt_i32 s4, 30
; GFX1250-GISEL-TRUE16-NEXT: s_cselect_b32 s2, 0x7c00, s2
@@ -1463,6 +1480,9 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(
; GFX1250-GISEL-FAKE16-NEXT: s_cselect_b32 s6, 1, 0
; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1250-GISEL-FAKE16-NEXT: s_or_b32 s6, s7, s6
+; GFX1250-GISEL-FAKE16-NEXT: s_cmp_lg_u32 s6, 0
+; GFX1250-GISEL-FAKE16-NEXT: s_cselect_b32 s6, 1, 0
+; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-GISEL-FAKE16-NEXT: s_add_co_i32 s2, s2, s6
; GFX1250-GISEL-FAKE16-NEXT: s_cmp_gt_i32 s4, 30
; GFX1250-GISEL-FAKE16-NEXT: s_cselect_b32 s2, 0x7c00, s2
@@ -1735,11 +1755,13 @@ define amdgpu_kernel void @fptrunc_f64_to_f16_afn(
; GFX1250-GISEL-TRUE16-NEXT: s_load_b64 s[2:3], s[2:3], 0x0
; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT: v_cvt_f32_f64_e32 v0, s[2:3]
-; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_3)
+; GFX1250-GISEL-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
-; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-GISEL-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX1250-GISEL-TRUE16-NEXT: s_cvt_f16_f32 s2, s2
+; GFX1250-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2
+; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX1250-GISEL-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX1250-GISEL-TRUE16-NEXT: s_endpgm
;
@@ -1751,11 +1773,13 @@ define amdgpu_kernel void @fptrunc_f64_to_f16_afn(
; GFX1250-GISEL-FAKE16-NEXT: s_load_b64 s[2:3], s[2:3], 0x0
; GFX1250-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f32_f64_e32 v0, s[2:3]
-; GFX1250-GISEL-FAKE16-NEXT: s_mov_b32 s2, -1
; GFX1250-GISEL-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_3)
+; GFX1250-GISEL-FAKE16-NEXT: v_readfirstlane_b32 s2, v0
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
-; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX1250-GISEL-FAKE16-NEXT: s_cvt_f16_f32 s2, s2
+; GFX1250-GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2
+; GFX1250-GISEL-FAKE16-NEXT: s_mov_b32 s2, -1
; GFX1250-GISEL-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX1250-GISEL-FAKE16-NEXT: s_endpgm
ptr addrspace(1) %r,
@@ -1798,9 +1822,14 @@ define amdgpu_kernel void @fptrunc_v2f32_to_v2f16(
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, s4
; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, s5
-; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_readfirstlane_b32 s3, v0
+; SI-GISEL-NEXT: v_readfirstlane_b32 s4, v1
+; SI-GISEL-NEXT: s_and_b32 s3, 0xffff, s3
+; SI-GISEL-NEXT: s_and_b32 s4, 0xffff, s4
+; SI-GISEL-NEXT: s_lshl_b32 s4, s4, 16
+; SI-GISEL-NEXT: s_or_b32 s4, s3, s4
; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s4
; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-GISEL-NEXT: s_endpgm
;
@@ -1830,12 +1859,17 @@ define amdgpu_kernel void @fptrunc_v2f32_to_v2f16(
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, s3
; VI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, s2
-; VI-GISEL-NEXT: v_cvt_f16_f32_sdwa v1, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
; VI-GISEL-NEXT: s_mov_b32 s2, -1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s3, v0
+; VI-GISEL-NEXT: s_and_b32 s4, 0xffff, s4
+; VI-GISEL-NEXT: s_and_b32 s3, 0xffff, s3
+; VI-GISEL-NEXT: s_lshl_b32 s4, s4, 16
+; VI-GISEL-NEXT: s_or_b32 s3, s3, s4
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s3
; VI-GISEL-NEXT: s_mov_b32 s3, 0xf000
-; VI-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; VI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-GISEL-NEXT: s_endpgm
;
@@ -1868,8 +1902,12 @@ define amdgpu_kernel void @fptrunc_v2f32_to_v2f16(
; GFX9-GISEL-NEXT: v_cvt_f16_f32_e32 v0, s2
; GFX9-GISEL-NEXT: v_cvt_f16_f32_e32 v1, s3
; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s3, v0
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s4, v1
+; GFX9-GISEL-NEXT: s_pack_ll_b32_b16 s3, s3, s4
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s3
; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
-; GFX9-GISEL-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX9-GISEL-NEXT: s_nop 0
; GFX9-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX9-GISEL-NEXT: s_endpgm
;
@@ -1953,11 +1991,14 @@ define amdgpu_kernel void @fptrunc_v2f32_to_v2f16(
; GFX11-GISEL-TRUE16-NEXT: s_load_b64 s[2:3], s[2:3], 0x0
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, s2
-; GFX11-GISEL-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, s3
-; GFX11-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1
+; GFX11-GISEL-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, s3
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
+; GFX11-GISEL-TRUE16-NEXT: v_readfirstlane_b32 s3, v1
+; GFX11-GISEL-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s2, s3
; GFX11-GISEL-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX11-GISEL-TRUE16-NEXT: buffer_store_b32 v0, off, s[0:3], 0
; GFX11-GISEL-TRUE16-NEXT: s_endpgm
;
@@ -1969,10 +2010,13 @@ define amdgpu_kernel void @fptrunc_v2f32_to_v2f16(
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, s2
; GFX11-GISEL-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, s3
-; GFX11-GISEL-FAKE16-NEXT: s_mov_b32 s2, -1
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT: v_readfirstlane_b32 s2, v0
+; GFX11-GISEL-FAKE16-NEXT: v_readfirstlane_b32 s3, v1
+; GFX11-GISEL-FAKE16-NEXT: s_pack_ll_b32_b16 s2, s2, s3
; GFX11-GISEL-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-GISEL-FAKE16-NEXT: s_mov_b32 s2, -1
; GFX11-GISEL-FAKE16-NEXT: buffer_store_b32 v0, off, s[0:3], 0
; GFX11-GISEL-FAKE16-NEXT: s_endpgm
;
@@ -2173,13 +2217,13 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; SI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
; SI-GISEL-NEXT: s_or_b32 s4, s8, s4
; SI-GISEL-NEXT: s_cselect_b32 s8, 1, 0
-; SI-GISEL-NEXT: s_lshl_b32 s8, s8, 9
; SI-GISEL-NEXT: s_lshl_b32 s9, s3, 12
; SI-GISEL-NEXT: s_sub_i32 s10, 1, s3
; SI-GISEL-NEXT: s_or_b32 s11, s4, 0x1000
-; SI-GISEL-NEXT: s_or_b32 s8, s8, 0x7c00
+; SI-GISEL-NEXT: s_lshl_b32 s8, s8, 9
; SI-GISEL-NEXT: s_or_b32 s4, s4, s9
; SI-GISEL-NEXT: s_max_i32 s9, s10, 0
+; SI-GISEL-NEXT: s_or_b32 s8, s8, 0x7c00
; SI-GISEL-NEXT: s_min_i32 s9, s9, 13
; SI-GISEL-NEXT: s_lshr_b32 s10, s11, s9
; SI-GISEL-NEXT: s_lshl_b32 s9, s10, s9
@@ -2195,6 +2239,8 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; SI-GISEL-NEXT: s_cmp_gt_i32 s9, 5
; SI-GISEL-NEXT: s_cselect_b32 s9, 1, 0
; SI-GISEL-NEXT: s_or_b32 s9, s10, s9
+; SI-GISEL-NEXT: s_cmp_lg_u32 s9, 0
+; SI-GISEL-NEXT: s_cselect_b32 s9, 1, 0
; SI-GISEL-NEXT: s_add_i32 s4, s4, s9
; SI-GISEL-NEXT: s_cmp_gt_i32 s3, 30
; SI-GISEL-NEXT: s_cselect_b32 s4, 0x7c00, s4
@@ -2212,13 +2258,13 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; SI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
; SI-GISEL-NEXT: s_or_b32 s4, s8, s4
; SI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
-; SI-GISEL-NEXT: s_lshl_b32 s6, s6, 9
; SI-GISEL-NEXT: s_lshl_b32 s8, s5, 12
; SI-GISEL-NEXT: s_sub_i32 s9, 1, s5
; SI-GISEL-NEXT: s_or_b32 s10, s4, 0x1000
-; SI-GISEL-NEXT: s_or_b32 s6, s6, 0x7c00
+; SI-GISEL-NEXT: s_lshl_b32 s6, s6, 9
; SI-GISEL-NEXT: s_or_b32 s4, s4, s8
; SI-GISEL-NEXT: s_max_i32 s8, s9, 0
+; SI-GISEL-NEXT: s_or_b32 s6, s6, 0x7c00
; SI-GISEL-NEXT: s_min_i32 s8, s8, 13
; SI-GISEL-NEXT: s_lshr_b32 s9, s10, s8
; SI-GISEL-NEXT: s_lshl_b32 s8, s9, s8
@@ -2234,6 +2280,8 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; SI-GISEL-NEXT: s_cmp_gt_i32 s8, 5
; SI-GISEL-NEXT: s_cselect_b32 s8, 1, 0
; SI-GISEL-NEXT: s_or_b32 s8, s9, s8
+; SI-GISEL-NEXT: s_cmp_lg_u32 s8, 0
+; SI-GISEL-NEXT: s_cselect_b32 s8, 1, 0
; SI-GISEL-NEXT: s_add_i32 s4, s4, s8
; SI-GISEL-NEXT: s_cmp_gt_i32 s5, 30
; SI-GISEL-NEXT: s_cselect_b32 s4, 0x7c00, s4
@@ -2392,6 +2440,8 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; VI-GISEL-NEXT: s_cmp_gt_i32 s8, 5
; VI-GISEL-NEXT: s_cselect_b32 s8, 1, 0
; VI-GISEL-NEXT: s_or_b32 s8, s9, s8
+; VI-GISEL-NEXT: s_cmp_lg_u32 s8, 0
+; VI-GISEL-NEXT: s_cselect_b32 s8, 1, 0
; VI-GISEL-NEXT: s_add_i32 s3, s3, s8
; VI-GISEL-NEXT: s_cmp_gt_i32 s2, 30
; VI-GISEL-NEXT: s_cselect_b32 s3, 0x7c00, s3
@@ -2431,6 +2481,8 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; VI-GISEL-NEXT: s_cmp_gt_i32 s6, 5
; VI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
; VI-GISEL-NEXT: s_or_b32 s6, s8, s6
+; VI-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
; VI-GISEL-NEXT: s_add_i32 s4, s4, s6
; VI-GISEL-NEXT: s_cmp_gt_i32 s3, 30
; VI-GISEL-NEXT: s_cselect_b32 s4, 0x7c00, s4
@@ -2588,6 +2640,8 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; GFX9-GISEL-NEXT: s_cmp_gt_i32 s8, 5
; GFX9-GISEL-NEXT: s_cselect_b32 s8, 1, 0
; GFX9-GISEL-NEXT: s_or_b32 s8, s9, s8
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s8, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s8, 1, 0
; GFX9-GISEL-NEXT: s_add_i32 s3, s3, s8
; GFX9-GISEL-NEXT: s_cmp_gt_i32 s2, 30
; GFX9-GISEL-NEXT: s_cselect_b32 s3, 0x7c00, s3
@@ -2627,6 +2681,8 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; GFX9-GISEL-NEXT: s_cmp_gt_i32 s6, 5
; GFX9-GISEL-NEXT: s_cselect_b32 s6, 1, 0
; GFX9-GISEL-NEXT: s_or_b32 s6, s8, s6
+; GFX9-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; GFX9-GISEL-NEXT: s_cselect_b32 s6, 1, 0
; GFX9-GISEL-NEXT: s_add_i32 s4, s4, s6
; GFX9-GISEL-NEXT: s_cmp_gt_i32 s3, 30
; GFX9-GISEL-NEXT: s_cselect_b32 s4, 0x7c00, s4
@@ -2781,6 +2837,8 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; GFX950-GISEL-NEXT: s_cmp_gt_i32 s8, 5
; GFX950-GISEL-NEXT: s_cselect_b32 s8, 1, 0
; GFX950-GISEL-NEXT: s_or_b32 s8, s9, s8
+; GFX950-GISEL-NEXT: s_cmp_lg_u32 s8, 0
+; GFX950-GISEL-NEXT: s_cselect_b32 s8, 1, 0
; GFX950-GISEL-NEXT: s_add_i32 s3, s3, s8
; GFX950-GISEL-NEXT: s_cmp_gt_i32 s2, 30
; GFX950-GISEL-NEXT: s_cselect_b32 s3, 0x7c00, s3
@@ -2820,6 +2878,8 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; GFX950-GISEL-NEXT: s_cmp_gt_i32 s6, 5
; GFX950-GISEL-NEXT: s_cselect_b32 s6, 1, 0
; GFX950-GISEL-NEXT: s_or_b32 s6, s8, s6
+; GFX950-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; GFX950-GISEL-NEXT: s_cselect_b32 s6, 1, 0
; GFX950-GISEL-NEXT: s_add_i32 s4, s4, s6
; GFX950-GISEL-NEXT: s_cmp_gt_i32 s3, 30
; GFX950-GISEL-NEXT: s_cselect_b32 s4, 0x7c00, s4
@@ -3107,6 +3167,9 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; GFX11-GISEL-TRUE16-NEXT: s_cselect_b32 s8, 1, 0
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-GISEL-TRUE16-NEXT: s_or_b32 s8, s9, s8
+; GFX11-GISEL-TRUE16-NEXT: s_cmp_lg_u32 s8, 0
+; GFX11-GISEL-TRUE16-NEXT: s_cselect_b32 s8, 1, 0
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-GISEL-TRUE16-NEXT: s_add_i32 s3, s3, s8
; GFX11-GISEL-TRUE16-NEXT: s_cmp_gt_i32 s2, 30
; GFX11-GISEL-TRUE16-NEXT: s_cselect_b32 s3, 0x7c00, s3
@@ -3149,6 +3212,9 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; GFX11-GISEL-TRUE16-NEXT: s_cselect_b32 s6, 1, 0
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-GISEL-TRUE16-NEXT: s_or_b32 s6, s8, s6
+; GFX11-GISEL-TRUE16-NEXT: s_cmp_lg_u32 s6, 0
+; GFX11-GISEL-TRUE16-NEXT: s_cselect_b32 s6, 1, 0
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-GISEL-TRUE16-NEXT: s_add_i32 s3, s3, s6
; GFX11-GISEL-TRUE16-NEXT: s_cmp_gt_i32 s4, 30
; GFX11-GISEL-TRUE16-NEXT: s_cselect_b32 s3, 0x7c00, s3
@@ -3206,6 +3272,9 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; GFX11-GISEL-FAKE16-NEXT: s_cselect_b32 s8, 1, 0
; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-GISEL-FAKE16-NEXT: s_or_b32 s8, s9, s8
+; GFX11-GISEL-FAKE16-NEXT: s_cmp_lg_u32 s8, 0
+; GFX11-GISEL-FAKE16-NEXT: s_cselect_b32 s8, 1, 0
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-GISEL-FAKE16-NEXT: s_add_i32 s3, s3, s8
; GFX11-GISEL-FAKE16-NEXT: s_cmp_gt_i32 s2, 30
; GFX11-GISEL-FAKE16-NEXT: s_cselect_b32 s3, 0x7c00, s3
@@ -3248,6 +3317,9 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; GFX11-GISEL-FAKE16-NEXT: s_cselect_b32 s6, 1, 0
; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-GISEL-FAKE16-NEXT: s_or_b32 s6, s8, s6
+; GFX11-GISEL-FAKE16-NEXT: s_cmp_lg_u32 s6, 0
+; GFX11-GISEL-FAKE16-NEXT: s_cselect_b32 s6, 1, 0
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-GISEL-FAKE16-NEXT: s_add_i32 s3, s3, s6
; GFX11-GISEL-FAKE16-NEXT: s_cmp_gt_i32 s4, 30
; GFX11-GISEL-FAKE16-NEXT: s_cselect_b32 s3, 0x7c00, s3
@@ -3540,6 +3612,9 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; GFX1250-GISEL-TRUE16-NEXT: s_cselect_b32 s8, 1, 0
; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1250-GISEL-TRUE16-NEXT: s_or_b32 s8, s9, s8
+; GFX1250-GISEL-TRUE16-NEXT: s_cmp_lg_u32 s8, 0
+; GFX1250-GISEL-TRUE16-NEXT: s_cselect_b32 s8, 1, 0
+; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-GISEL-TRUE16-NEXT: s_add_co_i32 s3, s3, s8
; GFX1250-GISEL-TRUE16-NEXT: s_cmp_gt_i32 s2, 30
; GFX1250-GISEL-TRUE16-NEXT: s_cselect_b32 s3, 0x7c00, s3
@@ -3582,6 +3657,9 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; GFX1250-GISEL-TRUE16-NEXT: s_cselect_b32 s6, 1, 0
; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1250-GISEL-TRUE16-NEXT: s_or_b32 s6, s8, s6
+; GFX1250-GISEL-TRUE16-NEXT: s_cmp_lg_u32 s6, 0
+; GFX1250-GISEL-TRUE16-NEXT: s_cselect_b32 s6, 1, 0
+; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-GISEL-TRUE16-NEXT: s_add_co_i32 s3, s3, s6
; GFX1250-GISEL-TRUE16-NEXT: s_cmp_gt_i32 s4, 30
; GFX1250-GISEL-TRUE16-NEXT: s_cselect_b32 s3, 0x7c00, s3
@@ -3640,6 +3718,9 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; GFX1250-GISEL-FAKE16-NEXT: s_cselect_b32 s8, 1, 0
; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1250-GISEL-FAKE16-NEXT: s_or_b32 s8, s9, s8
+; GFX1250-GISEL-FAKE16-NEXT: s_cmp_lg_u32 s8, 0
+; GFX1250-GISEL-FAKE16-NEXT: s_cselect_b32 s8, 1, 0
+; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-GISEL-FAKE16-NEXT: s_add_co_i32 s3, s3, s8
; GFX1250-GISEL-FAKE16-NEXT: s_cmp_gt_i32 s2, 30
; GFX1250-GISEL-FAKE16-NEXT: s_cselect_b32 s3, 0x7c00, s3
@@ -3682,6 +3763,9 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; GFX1250-GISEL-FAKE16-NEXT: s_cselect_b32 s6, 1, 0
; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1250-GISEL-FAKE16-NEXT: s_or_b32 s6, s8, s6
+; GFX1250-GISEL-FAKE16-NEXT: s_cmp_lg_u32 s6, 0
+; GFX1250-GISEL-FAKE16-NEXT: s_cselect_b32 s6, 1, 0
+; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-GISEL-FAKE16-NEXT: s_add_co_i32 s3, s3, s6
; GFX1250-GISEL-FAKE16-NEXT: s_cmp_gt_i32 s4, 30
; GFX1250-GISEL-FAKE16-NEXT: s_cselect_b32 s3, 0x7c00, s3
@@ -3742,9 +3826,14 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16_afn(
; SI-GISEL-NEXT: v_cvt_f32_f64_e32 v1, s[6:7]
; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_readfirstlane_b32 s3, v0
+; SI-GISEL-NEXT: v_readfirstlane_b32 s4, v1
+; SI-GISEL-NEXT: s_and_b32 s3, 0xffff, s3
+; SI-GISEL-NEXT: s_and_b32 s4, 0xffff, s4
+; SI-GISEL-NEXT: s_lshl_b32 s4, s4, 16
+; SI-GISEL-NEXT: s_or_b32 s4, s3, s4
; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s4
; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-GISEL-NEXT: s_endpgm
;
@@ -3776,13 +3865,19 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16_afn(
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
; VI-GISEL-NEXT: s_mov_b32 s2, -1
-; VI-GISEL-NEXT: s_mov_b32 s3, 0xf000
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v0, s[4:5]
; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v1, s[6:7]
+; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v0, s[4:5]
+; VI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1
; VI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
-; VI-GISEL-NEXT: v_cvt_f16_f32_sdwa v1, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-; VI-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s3, v0
+; VI-GISEL-NEXT: s_and_b32 s4, 0xffff, s4
+; VI-GISEL-NEXT: s_and_b32 s3, 0xffff, s3
+; VI-GISEL-NEXT: s_lshl_b32 s4, s4, 16
+; VI-GISEL-NEXT: s_or_b32 s3, s3, s4
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; VI-GISEL-NEXT: s_mov_b32 s3, 0xf000
; VI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-GISEL-NEXT: s_endpgm
;
@@ -3814,13 +3909,17 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16_afn(
; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-GISEL-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
-; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-GISEL-NEXT: v_cvt_f32_f64_e32 v0, s[4:5]
; GFX9-GISEL-NEXT: v_cvt_f32_f64_e32 v1, s[6:7]
; GFX9-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX9-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GFX9-GISEL-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s3, v0
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s4, v1
+; GFX9-GISEL-NEXT: s_pack_ll_b32_b16 s3, s3, s4
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT: s_nop 0
; GFX9-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX9-GISEL-NEXT: s_endpgm
;
@@ -3850,13 +3949,17 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16_afn(
; GFX950-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX950-GISEL-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
; GFX950-GISEL-NEXT: s_mov_b32 s2, -1
-; GFX950-GISEL-NEXT: s_mov_b32 s3, 0xf000
; GFX950-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX950-GISEL-NEXT: v_cvt_f32_f64_e32 v0, s[4:5]
; GFX950-GISEL-NEXT: v_cvt_f32_f64_e32 v1, s[6:7]
; GFX950-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX950-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GFX950-GISEL-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s3, v0
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s4, v1
+; GFX950-GISEL-NEXT: s_pack_ll_b32_b16 s3, s3, s4
+; GFX950-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GFX950-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX950-GISEL-NEXT: s_nop 0
; GFX950-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX950-GISEL-NEXT: s_endpgm
;
@@ -3913,16 +4016,19 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16_afn(
; GFX11-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: s_load_b128 s[4:7], s[2:3], 0x0
-; GFX11-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1
-; GFX11-GISEL-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_cvt_f32_f64_e32 v0, s[4:5]
; GFX11-GISEL-TRUE16-NEXT: v_cvt_f32_f64_e32 v1, s[6:7]
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
-; GFX11-GISEL-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v1
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
+; GFX11-GISEL-TRUE16-NEXT: v_readfirstlane_b32 s3, v1
+; GFX11-GISEL-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s2, s3
+; GFX11-GISEL-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX11-GISEL-TRUE16-NEXT: buffer_store_b32 v0, off, s[0:3], 0
; GFX11-GISEL-TRUE16-NEXT: s_endpgm
;
@@ -3931,16 +4037,19 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16_afn(
; GFX11-GISEL-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT: s_load_b128 s[4:7], s[2:3], 0x0
-; GFX11-GISEL-FAKE16-NEXT: s_mov_b32 s2, -1
-; GFX11-GISEL-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT: v_cvt_f32_f64_e32 v0, s[4:5]
; GFX11-GISEL-FAKE16-NEXT: v_cvt_f32_f64_e32 v1, s[6:7]
; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX11-GISEL-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT: v_readfirstlane_b32 s2, v0
+; GFX11-GISEL-FAKE16-NEXT: v_readfirstlane_b32 s3, v1
+; GFX11-GISEL-FAKE16-NEXT: s_pack_ll_b32_b16 s2, s2, s3
+; GFX11-GISEL-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
+; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-GISEL-FAKE16-NEXT: s_mov_b32 s2, -1
; GFX11-GISEL-FAKE16-NEXT: buffer_store_b32 v0, off, s[0:3], 0
; GFX11-GISEL-FAKE16-NEXT: s_endpgm
;
@@ -3994,18 +4103,20 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16_afn(
; GFX1250-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT: s_load_b128 s[4:7], s[2:3], 0x0
-; GFX1250-GISEL-TRUE16-NEXT: s_wait_xcnt 0x0
-; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1
-; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX1250-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-TRUE16-NEXT: v_cvt_f32_f64_e32 v0, s[4:5]
; GFX1250-GISEL-TRUE16-NEXT: v_cvt_f32_f64_e32 v1, s[6:7]
-; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1250-GISEL-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
-; GFX1250-GISEL-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1
-; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-GISEL-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h
+; GFX1250-GISEL-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1250-GISEL-TRUE16-NEXT: v_readfirstlane_b32 s3, v1
+; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
+; GFX1250-GISEL-TRUE16-NEXT: s_cvt_f16_f32 s2, s2
+; GFX1250-GISEL-TRUE16-NEXT: s_cvt_f16_f32 s3, s3
+; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX1250-GISEL-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s2, s3
+; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1250-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2
+; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX1250-GISEL-TRUE16-NEXT: buffer_store_b32 v0, off, s[0:3], null
; GFX1250-GISEL-TRUE16-NEXT: s_endpgm
;
@@ -4015,18 +4126,20 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16_afn(
; GFX1250-GISEL-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX1250-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT: s_load_b128 s[4:7], s[2:3], 0x0
-; GFX1250-GISEL-FAKE16-NEXT: s_wait_xcnt 0x0
-; GFX1250-GISEL-FAKE16-NEXT: s_mov_b32 s2, -1
-; GFX1250-GISEL-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX1250-GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f32_f64_e32 v0, s[4:5]
; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f32_f64_e32 v1, s[6:7]
-; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
-; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-GISEL-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX1250-GISEL-FAKE16-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1250-GISEL-FAKE16-NEXT: v_readfirstlane_b32 s3, v1
+; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0
+; GFX1250-GISEL-FAKE16-NEXT: s_cvt_f16_f32 s2, s2
+; GFX1250-GISEL-FAKE16-NEXT: s_cvt_f16_f32 s3, s3
+; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX1250-GISEL-FAKE16-NEXT: s_pack_ll_b32_b16 s2, s2, s3
+; GFX1250-GISEL-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1250-GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2
+; GFX1250-GISEL-FAKE16-NEXT: s_mov_b32 s2, -1
; GFX1250-GISEL-FAKE16-NEXT: buffer_store_b32 v0, off, s[0:3], null
; GFX1250-GISEL-FAKE16-NEXT: s_endpgm
ptr addrspace(1) %r,
@@ -4876,7 +4989,10 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_zext_i32(
; SI-GISEL-NEXT: s_mov_b32 s2, -1
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, s3
+; SI-GISEL-NEXT: v_readfirstlane_b32 s3, v0
+; SI-GISEL-NEXT: s_and_b32 s4, 0xffff, s3
; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s4
; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-GISEL-NEXT: s_endpgm
;
@@ -4903,10 +5019,14 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_zext_i32(
; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: s_load_dword s2, s[2:3], 0x0
-; VI-GISEL-NEXT: s_mov_b32 s3, 0xf000
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, s2
; VI-GISEL-NEXT: s_mov_b32 s2, -1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s3, v0
+; VI-GISEL-NEXT: s_and_b32 s3, 0xffff, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; VI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; VI-GISEL-NEXT: s_nop 1
; VI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-GISEL-NEXT: s_endpgm
;
@@ -4933,10 +5053,14 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_zext_i32(
; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-GISEL-NEXT: s_load_dword s2, s[2:3], 0x0
-; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-GISEL-NEXT: v_cvt_f16_f32_e32 v0, s2
; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s3, v0
+; GFX9-GISEL-NEXT: s_and_b32 s3, 0xffff, s3
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT: s_nop 1
; GFX9-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX9-GISEL-NEXT: s_endpgm
;
@@ -4963,10 +5087,15 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_zext_i32(
; GFX950-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX950-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX950-GISEL-NEXT: s_load_dword s2, s[2:3], 0x0
-; GFX950-GISEL-NEXT: s_mov_b32 s3, 0xf000
; GFX950-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX950-GISEL-NEXT: v_cvt_f16_f32_e32 v0, s2
; GFX950-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s3, v0
+; GFX950-GISEL-NEXT: s_and_b32 s3, 0xffff, s3
+; GFX950-GISEL-NEXT: s_nop 0
+; GFX950-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GFX950-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX950-GISEL-NEXT: s_nop 0
; GFX950-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX950-GISEL-NEXT: s_endpgm
;
@@ -5013,12 +5142,15 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_zext_i32(
; GFX11-GISEL-TRUE16-LABEL: fptrunc_f32_to_f16_zext_i32:
; GFX11-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX11-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.h, 0
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: s_load_b32 s2, s[2:3], 0x0
; GFX11-GISEL-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, s2
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-GISEL-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
+; GFX11-GISEL-TRUE16-NEXT: s_and_b32 s2, 0xffff, s2
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2
; GFX11-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX11-GISEL-TRUE16-NEXT: buffer_store_b32 v0, off, s[0:3], 0
; GFX11-GISEL-TRUE16-NEXT: s_endpgm
@@ -5031,9 +5163,11 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_zext_i32(
; GFX11-GISEL-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, s2
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-GISEL-FAKE16-NEXT: v_readfirstlane_b32 s2, v0
+; GFX11-GISEL-FAKE16-NEXT: s_and_b32 s2, 0xffff, s2
+; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2
; GFX11-GISEL-FAKE16-NEXT: s_mov_b32 s2, -1
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-GISEL-FAKE16-NEXT: buffer_store_b32 v0, off, s[0:3], 0
; GFX11-GISEL-FAKE16-NEXT: s_endpgm
;
@@ -5154,7 +5288,10 @@ define amdgpu_kernel void @fptrunc_fabs_f32_to_f16_zext_i32(
; SI-GISEL-NEXT: s_mov_b32 s2, -1
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; SI-GISEL-NEXT: v_cvt_f16_f32_e64 v0, |s3|
+; SI-GISEL-NEXT: v_readfirstlane_b32 s3, v0
+; SI-GISEL-NEXT: s_and_b32 s4, 0xffff, s3
; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s4
; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-GISEL-NEXT: s_endpgm
;
@@ -5181,10 +5318,14 @@ define amdgpu_kernel void @fptrunc_fabs_f32_to_f16_zext_i32(
; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: s_load_dword s2, s[2:3], 0x0
-; VI-GISEL-NEXT: s_mov_b32 s3, 0xf000
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cvt_f16_f32_e64 v0, |s2|
; VI-GISEL-NEXT: s_mov_b32 s2, -1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s3, v0
+; VI-GISEL-NEXT: s_and_b32 s3, 0xffff, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; VI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; VI-GISEL-NEXT: s_nop 1
; VI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-GISEL-NEXT: s_endpgm
;
@@ -5211,10 +5352,14 @@ define amdgpu_kernel void @fptrunc_fabs_f32_to_f16_zext_i32(
; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-GISEL-NEXT: s_load_dword s2, s[2:3], 0x0
-; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-GISEL-NEXT: v_cvt_f16_f32_e64 v0, |s2|
; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s3, v0
+; GFX9-GISEL-NEXT: s_and_b32 s3, 0xffff, s3
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT: s_nop 1
; GFX9-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX9-GISEL-NEXT: s_endpgm
;
@@ -5241,10 +5386,15 @@ define amdgpu_kernel void @fptrunc_fabs_f32_to_f16_zext_i32(
; GFX950-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX950-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX950-GISEL-NEXT: s_load_dword s2, s[2:3], 0x0
-; GFX950-GISEL-NEXT: s_mov_b32 s3, 0xf000
; GFX950-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX950-GISEL-NEXT: v_cvt_f16_f32_e64 v0, |s2|
; GFX950-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s3, v0
+; GFX950-GISEL-NEXT: s_and_b32 s3, 0xffff, s3
+; GFX950-GISEL-NEXT: s_nop 0
+; GFX950-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GFX950-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX950-GISEL-NEXT: s_nop 0
; GFX950-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX950-GISEL-NEXT: s_endpgm
;
@@ -5291,12 +5441,15 @@ define amdgpu_kernel void @fptrunc_fabs_f32_to_f16_zext_i32(
; GFX11-GISEL-TRUE16-LABEL: fptrunc_fabs_f32_to_f16_zext_i32:
; GFX11-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX11-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.h, 0
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: s_load_b32 s2, s[2:3], 0x0
; GFX11-GISEL-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_cvt_f16_f32_e64 v0.l, |s2|
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-GISEL-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
+; GFX11-GISEL-TRUE16-NEXT: s_and_b32 s2, 0xffff, s2
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2
; GFX11-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX11-GISEL-TRUE16-NEXT: buffer_store_b32 v0, off, s[0:3], 0
; GFX11-GISEL-TRUE16-NEXT: s_endpgm
@@ -5309,9 +5462,11 @@ define amdgpu_kernel void @fptrunc_fabs_f32_to_f16_zext_i32(
; GFX11-GISEL-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT: v_cvt_f16_f32_e64 v0, |s2|
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-GISEL-FAKE16-NEXT: v_readfirstlane_b32 s2, v0
+; GFX11-GISEL-FAKE16-NEXT: s_and_b32 s2, 0xffff, s2
+; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2
; GFX11-GISEL-FAKE16-NEXT: s_mov_b32 s2, -1
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-GISEL-FAKE16-NEXT: buffer_store_b32 v0, off, s[0:3], 0
; GFX11-GISEL-FAKE16-NEXT: s_endpgm
;
@@ -5438,8 +5593,10 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_sext_i32(
; SI-GISEL-NEXT: s_mov_b32 s2, -1
; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, s3
-; SI-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 16
+; SI-GISEL-NEXT: v_readfirstlane_b32 s3, v0
+; SI-GISEL-NEXT: s_sext_i32_i16 s4, s3
; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s4
; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-GISEL-NEXT: s_endpgm
;
@@ -5467,11 +5624,14 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_sext_i32(
; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: s_load_dword s2, s[2:3], 0x0
-; VI-GISEL-NEXT: s_mov_b32 s3, 0xf000
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, s2
; VI-GISEL-NEXT: s_mov_b32 s2, -1
-; VI-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 16
+; VI-GISEL-NEXT: v_readfirstlane_b32 s3, v0
+; VI-GISEL-NEXT: s_sext_i32_i16 s3, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; VI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; VI-GISEL-NEXT: s_nop 1
; VI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-GISEL-NEXT: s_endpgm
;
@@ -5499,11 +5659,14 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_sext_i32(
; GFX9-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-GISEL-NEXT: s_load_dword s2, s[2:3], 0x0
-; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-GISEL-NEXT: v_cvt_f16_f32_e32 v0, s2
; GFX9-GISEL-NEXT: s_mov_b32 s2, -1
-; GFX9-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s3, v0
+; GFX9-GISEL-NEXT: s_sext_i32_i16 s3, s3
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GFX9-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT: s_nop 1
; GFX9-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX9-GISEL-NEXT: s_endpgm
;
@@ -5531,11 +5694,15 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_sext_i32(
; GFX950-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX950-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX950-GISEL-NEXT: s_load_dword s2, s[2:3], 0x0
-; GFX950-GISEL-NEXT: s_mov_b32 s3, 0xf000
; GFX950-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX950-GISEL-NEXT: v_cvt_f16_f32_e32 v0, s2
; GFX950-GISEL-NEXT: s_mov_b32 s2, -1
-; GFX950-GISEL-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s3, v0
+; GFX950-GISEL-NEXT: s_sext_i32_i16 s3, s3
+; GFX950-GISEL-NEXT: s_nop 0
+; GFX950-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GFX950-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; GFX950-GISEL-NEXT: s_nop 0
; GFX950-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX950-GISEL-NEXT: s_endpgm
;
@@ -5587,9 +5754,11 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_sext_i32(
; GFX11-GISEL-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, s2
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-GISEL-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
+; GFX11-GISEL-TRUE16-NEXT: s_sext_i32_i16 s2, s2
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2
; GFX11-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX11-GISEL-TRUE16-NEXT: buffer_store_b32 v0, off, s[0:3], 0
; GFX11-GISEL-TRUE16-NEXT: s_endpgm
;
@@ -5601,9 +5770,11 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_sext_i32(
; GFX11-GISEL-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, s2
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-GISEL-FAKE16-NEXT: v_readfirstlane_b32 s2, v0
+; GFX11-GISEL-FAKE16-NEXT: s_sext_i32_i16 s2, s2
+; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2
; GFX11-GISEL-FAKE16-NEXT: s_mov_b32 s2, -1
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX11-GISEL-FAKE16-NEXT: buffer_store_b32 v0, off, s[0:3], 0
; GFX11-GISEL-FAKE16-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/fptrunc.ll b/llvm/test/CodeGen/AMDGPU/fptrunc.ll
index b6b26a47970b0..e008a6e1338af 100644
--- a/llvm/test/CodeGen/AMDGPU/fptrunc.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptrunc.ll
@@ -1,17 +1,17 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefixes=SI %s
; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=0 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=VI-SDAG,VI-SAFE-SDAG %s
-; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=1 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=VI-GISEL,VI-SAFE-GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=1 -new-reg-bank-select -mattr=-flat-for-global < %s | FileCheck -check-prefixes=VI-GISEL,VI-SAFE-GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=tonga -global-isel=0 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=VI-SDAG,VI-UNSAFE-SDAG %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -global-isel=0 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX10-SDAG,GFX10-SAFE-SDAG %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -global-isel=1 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX10-GISEL,GFX10-SAFE-GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -global-isel=1 -new-reg-bank-select -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX10-GISEL,GFX10-SAFE-GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -global-isel=0 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX10-SDAG,GFX10-UNSAFE-SDAG %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX11-SDAG,GFX11-SAFE-SDAG %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX11-GISEL,GFX11-SAFE-GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX11-GISEL,GFX11-SAFE-GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=-flat-for-global,+real-true16 < %s | FileCheck -check-prefixes=GFX11-SDAG,GFX11-UNSAFE-DAG-TRUE16 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 -mattr=-flat-for-global,-real-true16 < %s | FileCheck -check-prefixes=GFX11-SDAG,GFX11-UNSAFE-DAG-FAKE16 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -mattr=-flat-for-global,+real-true16 < %s | FileCheck -check-prefixes=GFX11-GISEL,GFX11-UNSAFE-GISEL-TRUE16 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -mattr=-flat-for-global,-real-true16 < %s | FileCheck -check-prefixes=GFX11-GISEL,GFX11-UNSAFE-GISEL-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=-flat-for-global,+real-true16 < %s | FileCheck -check-prefixes=GFX11-GISEL,GFX11-UNSAFE-GISEL-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -new-reg-bank-select -mattr=-flat-for-global,-real-true16 < %s | FileCheck -check-prefixes=GFX11-GISEL,GFX11-UNSAFE-GISEL-FAKE16 %s
define amdgpu_kernel void @fptrunc_f64_to_f32(ptr addrspace(1) %out, double %in) {
; SI-LABEL: fptrunc_f64_to_f32:
@@ -313,6 +313,8 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(ptr addrspace(1) %out, double %in)
; VI-GISEL-NEXT: s_cmp_gt_i32 s6, 5
; VI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
; VI-GISEL-NEXT: s_or_b32 s6, s7, s6
+; VI-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
; VI-GISEL-NEXT: s_add_i32 s2, s2, s6
; VI-GISEL-NEXT: s_cmp_gt_i32 s4, 30
; VI-GISEL-NEXT: s_cselect_b32 s2, 0x7c00, s2
@@ -413,6 +415,8 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(ptr addrspace(1) %out, double %in)
; GFX10-GISEL-NEXT: s_cmp_gt_i32 s6, 5
; GFX10-GISEL-NEXT: s_cselect_b32 s6, 1, 0
; GFX10-GISEL-NEXT: s_or_b32 s6, s7, s6
+; GFX10-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; GFX10-GISEL-NEXT: s_cselect_b32 s6, 1, 0
; GFX10-GISEL-NEXT: s_add_i32 s2, s2, s6
; GFX10-GISEL-NEXT: s_cmp_gt_i32 s4, 30
; GFX10-GISEL-NEXT: s_cselect_b32 s2, 0x7c00, s2
@@ -524,6 +528,9 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(ptr addrspace(1) %out, double %in)
; GFX11-GISEL-NEXT: s_cselect_b32 s6, 1, 0
; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-GISEL-NEXT: s_or_b32 s6, s7, s6
+; GFX11-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; GFX11-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-GISEL-NEXT: s_add_i32 s2, s2, s6
; GFX11-GISEL-NEXT: s_cmp_gt_i32 s4, 30
; GFX11-GISEL-NEXT: s_cselect_b32 s2, 0x7c00, s2
@@ -707,13 +714,18 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f32(ptr addrspace(1) %out, <2 x do
; VI-GISEL-LABEL: fptrunc_v2f64_to_v2f32:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
-; VI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
-; VI-GISEL-NEXT: s_mov_b32 s6, -1
-; VI-GISEL-NEXT: s_mov_b32 s7, 0xf000
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v0, s[0:1]
; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v1, s[2:3]
-; VI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-GISEL-NEXT: s_mov_b32 s2, -1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s5
+; VI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; VI-GISEL-NEXT: s_endpgm
;
; GFX10-SDAG-LABEL: fptrunc_v2f64_to_v2f32:
@@ -736,6 +748,10 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f32(ptr addrspace(1) %out, <2 x do
; GFX10-GISEL-NEXT: v_cvt_f32_f64_e32 v0, s[0:1]
; GFX10-GISEL-NEXT: v_cvt_f32_f64_e32 v1, s[2:3]
; GFX10-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX10-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX10-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s3
; GFX10-GISEL-NEXT: s_mov_b32 s2, -1
; GFX10-GISEL-NEXT: s_mov_b32 s3, 0x31016000
; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)
@@ -762,6 +778,11 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f32(ptr addrspace(1) %out, <2 x do
; GFX11-GISEL-NEXT: v_cvt_f32_f64_e32 v0, s[0:1]
; GFX11-GISEL-NEXT: v_cvt_f32_f64_e32 v1, s[2:3]
; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; GFX11-GISEL-NEXT: s_mov_b32 s2, -1
; GFX11-GISEL-NEXT: s_mov_b32 s3, 0x31016000
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
@@ -800,13 +821,18 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f32_afn(ptr addrspace(1) %out, <2
; VI-GISEL-LABEL: fptrunc_v2f64_to_v2f32_afn:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
-; VI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
-; VI-GISEL-NEXT: s_mov_b32 s6, -1
-; VI-GISEL-NEXT: s_mov_b32 s7, 0xf000
; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v0, s[0:1]
; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v1, s[2:3]
-; VI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-GISEL-NEXT: s_mov_b32 s2, -1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s5
+; VI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; VI-GISEL-NEXT: s_endpgm
;
; GFX10-SDAG-LABEL: fptrunc_v2f64_to_v2f32_afn:
@@ -829,6 +855,10 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f32_afn(ptr addrspace(1) %out, <2
; GFX10-GISEL-NEXT: v_cvt_f32_f64_e32 v0, s[0:1]
; GFX10-GISEL-NEXT: v_cvt_f32_f64_e32 v1, s[2:3]
; GFX10-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX10-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX10-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s3
; GFX10-GISEL-NEXT: s_mov_b32 s2, -1
; GFX10-GISEL-NEXT: s_mov_b32 s3, 0x31016000
; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0)
@@ -855,6 +885,11 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f32_afn(ptr addrspace(1) %out, <2
; GFX11-GISEL-NEXT: v_cvt_f32_f64_e32 v0, s[0:1]
; GFX11-GISEL-NEXT: v_cvt_f32_f64_e32 v1, s[2:3]
; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; GFX11-GISEL-NEXT: s_mov_b32 s2, -1
; GFX11-GISEL-NEXT: s_mov_b32 s3, 0x31016000
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
@@ -905,6 +940,12 @@ define amdgpu_kernel void @fptrunc_v3f64_to_v3f32(ptr addrspace(1) %out, <3 x do
; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v0, s[8:9]
; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v1, s[10:11]
; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v2, s[12:13]
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s5
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s6
; VI-GISEL-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0
; VI-GISEL-NEXT: s_endpgm
;
@@ -935,6 +976,12 @@ define amdgpu_kernel void @fptrunc_v3f64_to_v3f32(ptr addrspace(1) %out, <3 x do
; GFX10-GISEL-NEXT: v_cvt_f32_f64_e32 v0, s[8:9]
; GFX10-GISEL-NEXT: v_cvt_f32_f64_e32 v1, s[10:11]
; GFX10-GISEL-NEXT: v_cvt_f32_f64_e32 v2, s[12:13]
+; GFX10-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX10-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GFX10-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s5
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s6
; GFX10-GISEL-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0
; GFX10-GISEL-NEXT: s_endpgm
;
@@ -965,6 +1012,14 @@ define amdgpu_kernel void @fptrunc_v3f64_to_v3f32(ptr addrspace(1) %out, <3 x do
; GFX11-GISEL-NEXT: v_cvt_f32_f64_e32 v0, s[8:9]
; GFX11-GISEL-NEXT: v_cvt_f32_f64_e32 v1, s[10:11]
; GFX11-GISEL-NEXT: v_cvt_f32_f64_e32 v2, s[12:13]
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, s6
; GFX11-GISEL-NEXT: buffer_store_b96 v[0:2], off, s[0:3], 0
; GFX11-GISEL-NEXT: s_endpgm
%result = fptrunc <3 x double> %in to <3 x float>
@@ -1012,6 +1067,12 @@ define amdgpu_kernel void @fptrunc_v3f64_to_v3f32_afn(ptr addrspace(1) %out, <3
; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v0, s[8:9]
; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v1, s[10:11]
; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v2, s[12:13]
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s5
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s6
; VI-GISEL-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0
; VI-GISEL-NEXT: s_endpgm
;
@@ -1042,6 +1103,12 @@ define amdgpu_kernel void @fptrunc_v3f64_to_v3f32_afn(ptr addrspace(1) %out, <3
; GFX10-GISEL-NEXT: v_cvt_f32_f64_e32 v0, s[8:9]
; GFX10-GISEL-NEXT: v_cvt_f32_f64_e32 v1, s[10:11]
; GFX10-GISEL-NEXT: v_cvt_f32_f64_e32 v2, s[12:13]
+; GFX10-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX10-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GFX10-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s5
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s6
; GFX10-GISEL-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0
; GFX10-GISEL-NEXT: s_endpgm
;
@@ -1072,6 +1139,14 @@ define amdgpu_kernel void @fptrunc_v3f64_to_v3f32_afn(ptr addrspace(1) %out, <3
; GFX11-GISEL-NEXT: v_cvt_f32_f64_e32 v0, s[8:9]
; GFX11-GISEL-NEXT: v_cvt_f32_f64_e32 v1, s[10:11]
; GFX11-GISEL-NEXT: v_cvt_f32_f64_e32 v2, s[12:13]
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, s6
; GFX11-GISEL-NEXT: buffer_store_b96 v[0:2], off, s[0:3], 0
; GFX11-GISEL-NEXT: s_endpgm
%result = fptrunc afn <3 x double> %in to <3 x float>
@@ -1119,6 +1194,14 @@ define amdgpu_kernel void @fptrunc_v4f64_to_v4f32(ptr addrspace(1) %out, <4 x do
; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v1, s[10:11]
; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v2, s[12:13]
; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v3, s[14:15]
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; VI-GISEL-NEXT: v_readfirstlane_b32 s7, v3
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s5
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s6
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s7
; VI-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; VI-GISEL-NEXT: s_endpgm
;
@@ -1149,6 +1232,14 @@ define amdgpu_kernel void @fptrunc_v4f64_to_v4f32(ptr addrspace(1) %out, <4 x do
; GFX10-GISEL-NEXT: v_cvt_f32_f64_e32 v1, s[10:11]
; GFX10-GISEL-NEXT: v_cvt_f32_f64_e32 v2, s[12:13]
; GFX10-GISEL-NEXT: v_cvt_f32_f64_e32 v3, s[14:15]
+; GFX10-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX10-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GFX10-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; GFX10-GISEL-NEXT: v_readfirstlane_b32 s7, v3
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s5
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s6
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s7
; GFX10-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GFX10-GISEL-NEXT: s_endpgm
;
@@ -1179,6 +1270,15 @@ define amdgpu_kernel void @fptrunc_v4f64_to_v4f32(ptr addrspace(1) %out, <4 x do
; GFX11-GISEL-NEXT: v_cvt_f32_f64_e32 v1, s[10:11]
; GFX11-GISEL-NEXT: v_cvt_f32_f64_e32 v2, s[12:13]
; GFX11-GISEL-NEXT: v_cvt_f32_f64_e32 v3, s[14:15]
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s7, v3
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
; GFX11-GISEL-NEXT: buffer_store_b128 v[0:3], off, s[0:3], 0
; GFX11-GISEL-NEXT: s_endpgm
%result = fptrunc <4 x double> %in to <4 x float>
@@ -1226,6 +1326,14 @@ define amdgpu_kernel void @fptrunc_v4f64_to_v4f32_afn(ptr addrspace(1) %out, <4
; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v1, s[10:11]
; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v2, s[12:13]
; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v3, s[14:15]
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; VI-GISEL-NEXT: v_readfirstlane_b32 s7, v3
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s5
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s6
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s7
; VI-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; VI-GISEL-NEXT: s_endpgm
;
@@ -1256,6 +1364,14 @@ define amdgpu_kernel void @fptrunc_v4f64_to_v4f32_afn(ptr addrspace(1) %out, <4
; GFX10-GISEL-NEXT: v_cvt_f32_f64_e32 v1, s[10:11]
; GFX10-GISEL-NEXT: v_cvt_f32_f64_e32 v2, s[12:13]
; GFX10-GISEL-NEXT: v_cvt_f32_f64_e32 v3, s[14:15]
+; GFX10-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX10-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GFX10-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; GFX10-GISEL-NEXT: v_readfirstlane_b32 s7, v3
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s5
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s6
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s7
; GFX10-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GFX10-GISEL-NEXT: s_endpgm
;
@@ -1286,6 +1402,15 @@ define amdgpu_kernel void @fptrunc_v4f64_to_v4f32_afn(ptr addrspace(1) %out, <4
; GFX11-GISEL-NEXT: v_cvt_f32_f64_e32 v1, s[10:11]
; GFX11-GISEL-NEXT: v_cvt_f32_f64_e32 v2, s[12:13]
; GFX11-GISEL-NEXT: v_cvt_f32_f64_e32 v3, s[14:15]
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s7, v3
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
; GFX11-GISEL-NEXT: buffer_store_b128 v[0:3], off, s[0:3], 0
; GFX11-GISEL-NEXT: s_endpgm
%result = fptrunc afn <4 x double> %in to <4 x float>
@@ -1343,12 +1468,29 @@ define amdgpu_kernel void @fptrunc_v8f64_to_v8f32(ptr addrspace(1) %out, <8 x do
; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v1, s[10:11]
; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v2, s[12:13]
; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v3, s[14:15]
-; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v4, s[16:17]
-; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v5, s[18:19]
-; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v6, s[20:21]
-; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v7, s[22:23]
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; VI-GISEL-NEXT: v_readfirstlane_b32 s7, v3
+; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v0, s[16:17]
+; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v1, s[18:19]
+; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v2, s[20:21]
+; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v3, s[22:23]
+; VI-GISEL-NEXT: v_readfirstlane_b32 s8, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s9, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s10, v2
+; VI-GISEL-NEXT: v_readfirstlane_b32 s11, v3
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s5
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s6
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s7
; VI-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
-; VI-GISEL-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
+; VI-GISEL-NEXT: s_nop 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s8
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s9
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s10
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s11
+; VI-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
; VI-GISEL-NEXT: s_endpgm
;
; GFX10-SDAG-LABEL: fptrunc_v8f64_to_v8f32:
@@ -1387,6 +1529,22 @@ define amdgpu_kernel void @fptrunc_v8f64_to_v8f32(ptr addrspace(1) %out, <8 x do
; GFX10-GISEL-NEXT: v_cvt_f32_f64_e32 v5, s[18:19]
; GFX10-GISEL-NEXT: v_cvt_f32_f64_e32 v6, s[20:21]
; GFX10-GISEL-NEXT: v_cvt_f32_f64_e32 v7, s[22:23]
+; GFX10-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX10-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GFX10-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; GFX10-GISEL-NEXT: v_readfirstlane_b32 s7, v3
+; GFX10-GISEL-NEXT: v_readfirstlane_b32 s8, v4
+; GFX10-GISEL-NEXT: v_readfirstlane_b32 s9, v5
+; GFX10-GISEL-NEXT: v_readfirstlane_b32 s10, v6
+; GFX10-GISEL-NEXT: v_readfirstlane_b32 s11, v7
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s5
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s6
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s7
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v4, s8
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v5, s9
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v6, s10
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v7, s11
; GFX10-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GFX10-GISEL-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
; GFX10-GISEL-NEXT: s_endpgm
@@ -1428,6 +1586,19 @@ define amdgpu_kernel void @fptrunc_v8f64_to_v8f32(ptr addrspace(1) %out, <8 x do
; GFX11-GISEL-NEXT: v_cvt_f32_f64_e32 v5, s[18:19]
; GFX11-GISEL-NEXT: v_cvt_f32_f64_e32 v6, s[20:21]
; GFX11-GISEL-NEXT: v_cvt_f32_f64_e32 v7, s[22:23]
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s7, v3
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s8, v4
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s9, v5
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s10, v6
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s11, v7
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, s9
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
; GFX11-GISEL-NEXT: s_clause 0x1
; GFX11-GISEL-NEXT: buffer_store_b128 v[0:3], off, s[0:3], 0
; GFX11-GISEL-NEXT: buffer_store_b128 v[4:7], off, s[0:3], 0 offset:16
@@ -1487,12 +1658,29 @@ define amdgpu_kernel void @fptrunc_v8f64_to_v8f32_afn(ptr addrspace(1) %out, <8
; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v1, s[10:11]
; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v2, s[12:13]
; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v3, s[14:15]
-; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v4, s[16:17]
-; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v5, s[18:19]
-; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v6, s[20:21]
-; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v7, s[22:23]
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; VI-GISEL-NEXT: v_readfirstlane_b32 s7, v3
+; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v0, s[16:17]
+; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v1, s[18:19]
+; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v2, s[20:21]
+; VI-GISEL-NEXT: v_cvt_f32_f64_e32 v3, s[22:23]
+; VI-GISEL-NEXT: v_readfirstlane_b32 s8, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s9, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s10, v2
+; VI-GISEL-NEXT: v_readfirstlane_b32 s11, v3
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s5
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s6
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s7
; VI-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
-; VI-GISEL-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
+; VI-GISEL-NEXT: s_nop 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s8
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s9
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s10
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s11
+; VI-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
; VI-GISEL-NEXT: s_endpgm
;
; GFX10-SDAG-LABEL: fptrunc_v8f64_to_v8f32_afn:
@@ -1531,6 +1719,22 @@ define amdgpu_kernel void @fptrunc_v8f64_to_v8f32_afn(ptr addrspace(1) %out, <8
; GFX10-GISEL-NEXT: v_cvt_f32_f64_e32 v5, s[18:19]
; GFX10-GISEL-NEXT: v_cvt_f32_f64_e32 v6, s[20:21]
; GFX10-GISEL-NEXT: v_cvt_f32_f64_e32 v7, s[22:23]
+; GFX10-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX10-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GFX10-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; GFX10-GISEL-NEXT: v_readfirstlane_b32 s7, v3
+; GFX10-GISEL-NEXT: v_readfirstlane_b32 s8, v4
+; GFX10-GISEL-NEXT: v_readfirstlane_b32 s9, v5
+; GFX10-GISEL-NEXT: v_readfirstlane_b32 s10, v6
+; GFX10-GISEL-NEXT: v_readfirstlane_b32 s11, v7
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s5
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s6
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s7
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v4, s8
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v5, s9
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v6, s10
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v7, s11
; GFX10-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GFX10-GISEL-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
; GFX10-GISEL-NEXT: s_endpgm
@@ -1572,6 +1776,19 @@ define amdgpu_kernel void @fptrunc_v8f64_to_v8f32_afn(ptr addrspace(1) %out, <8
; GFX11-GISEL-NEXT: v_cvt_f32_f64_e32 v5, s[18:19]
; GFX11-GISEL-NEXT: v_cvt_f32_f64_e32 v6, s[20:21]
; GFX11-GISEL-NEXT: v_cvt_f32_f64_e32 v7, s[22:23]
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s7, v3
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s8, v4
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s9, v5
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s10, v6
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s11, v7
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, s9
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
; GFX11-GISEL-NEXT: s_clause 0x1
; GFX11-GISEL-NEXT: buffer_store_b128 v[0:3], off, s[0:3], 0
; GFX11-GISEL-NEXT: buffer_store_b128 v[4:7], off, s[0:3], 0 offset:16
diff --git a/llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.no.fast.math.ll b/llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.no.fast.math.ll
index d8f21d285ddff..e8025e6c45cf0 100644
--- a/llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.no.fast.math.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.no.fast.math.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn -mcpu=gfx950 -global-isel=0 < %s | FileCheck -check-prefixes=GFX950,GFX950-SDAG %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx950 -global-isel=1 < %s | FileCheck -check-prefixes=GFX950,GFX950-GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx950 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX950,GFX950-GISEL %s
define <2 x half> @v_test_cvt_v2f32_v2f16(<2 x float> %src) {
; GFX950-LABEL: v_test_cvt_v2f32_v2f16:
@@ -13,13 +13,21 @@ define <2 x half> @v_test_cvt_v2f32_v2f16(<2 x float> %src) {
}
define <3 x half> @v_test_cvt_v3f32_v3f16(<3 x float> %src) {
-; GFX950-LABEL: v_test_cvt_v3f32_v3f16:
-; GFX950: ; %bb.0:
-; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-NEXT: v_cvt_f16_f32_e32 v2, v2
-; GFX950-NEXT: v_cvt_pk_f16_f32 v0, v0, v1
-; GFX950-NEXT: v_mov_b32_e32 v1, v2
-; GFX950-NEXT: s_setpc_b64 s[30:31]
+; GFX950-SDAG-LABEL: v_test_cvt_v3f32_v3f16:
+; GFX950-SDAG: ; %bb.0:
+; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-SDAG-NEXT: v_cvt_f16_f32_e32 v2, v2
+; GFX950-SDAG-NEXT: v_cvt_pk_f16_f32 v0, v0, v1
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, v2
+; GFX950-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX950-GISEL-LABEL: v_test_cvt_v3f32_v3f16:
+; GFX950-GISEL: ; %bb.0:
+; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-GISEL-NEXT: v_cvt_f16_f32_e32 v2, v2
+; GFX950-GISEL-NEXT: v_cvt_pk_f16_f32 v0, v0, v1
+; GFX950-GISEL-NEXT: v_lshl_or_b32 v1, s0, 16, v2
+; GFX950-GISEL-NEXT: s_setpc_b64 s[30:31]
%res = fptrunc <3 x float> %src to <3 x half>
ret <3 x half> %res
}
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
index bce7c1e5e8ab7..ab66959de07d9 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
@@ -1,20 +1,20 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx700 < %s | FileCheck -check-prefixes=GFX7,GFX7-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx700 < %s | FileCheck -check-prefixes=GFX7,GFX7-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx700 < %s | FileCheck -check-prefixes=GFX7,GFX7-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx801 < %s | FileCheck -check-prefixes=GFX8,GFX8-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx801 < %s | FileCheck -check-prefixes=GFX8,GFX8-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx801 < %s | FileCheck -check-prefixes=GFX8,GFX8-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX9,GFX9-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
define half @test_vector_reduce_fadd_v2half(half %sp, <2 x half> %v) {
; GFX7-SDAG-LABEL: test_vector_reduce_fadd_v2half:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll
index 657fe0f0804f3..a6aff732830ee 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll
@@ -1,20 +1,20 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx700 < %s | FileCheck -check-prefixes=GFX7,GFX7-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx700 < %s | FileCheck -check-prefixes=GFX7,GFX7-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx700 < %s | FileCheck -check-prefixes=GFX7,GFX7-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx801 < %s | FileCheck -check-prefixes=GFX8,GFX8-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx801 < %s | FileCheck -check-prefixes=GFX8,GFX8-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx801 < %s | FileCheck -check-prefixes=GFX8,GFX8-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX9,GFX9-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
define half @test_vector_reduce_fmul_v2half(half %sp, <2 x half> %v) {
; GFX7-SDAG-LABEL: test_vector_reduce_fmul_v2half:
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