[llvm] [AArch64] Eliminate redundant setcc on vector comparison results (PR #171431)

[David Green via llvm-commits]

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@@ -4748,6 +4748,27 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
     }
   }
 
+  // setcc X, 0, setlt --> X  (when X is all sign bits)
+  // setcc 0, X, setgt --> X  (equivalent form)
+  //
+  // When we know that X has 0 or -1 in each lane, this comparison will produce
+  // X. This is only true when boolean contents are represented via 0s and -1s.
+  if (OpVT.isVector() && VT == OpVT &&
+      getBooleanContents(VT) == ZeroOrNegativeOneBooleanContent) {
+    SDValue Candidate;
+    // setcc LHS, 0, setlt
+    if (Cond == ISD::SETLT && isNullOrNullSplat(N1))
+      Candidate = N0;
+    // setcc 0, RHS, setgt (equivalent to RHS < 0)
+    else if (Cond == ISD::SETGT && isNullOrNullSplat(N0))
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davemgreen wrote:

Does the constant on the RHS come up anywhere, or is the zero usually canonicalised to the RHS?

https://github.com/llvm/llvm-project/pull/171431