[llvm] SelectionDAG: Support FMINIMUMNUM and FMINIMUM in combineMinNumMaxNumImpl (PR #137449)

[Matt Arsenault via llvm-commits]

================
@@ -11944,6 +11953,15 @@ static SDValue combineMinNumMaxNumImpl(const SDLoc &DL, EVT VT, SDValue LHS,
   case ISD::SETGE:
   case ISD::SETUGT:
   case ISD::SETUGE: {
+    unsigned IEEE2019NumOpcode =
+        (LHS == True) ? ISD::FMAXIMUMNUM : ISD::FMINIMUMNUM;
----------------
arsenm wrote:

```suggestion
        LHS == True ? ISD::FMAXIMUMNUM : ISD::FMINIMUMNUM;
```

https://github.com/llvm/llvm-project/pull/137449