[llvm] SelectionDAG: Support FMINIMUMNUM and FMINIMUM in combineMinNumMaxNumImpl (PR #137449)

[Matt Arsenault via llvm-commits]

================
@@ -11926,9 +11926,18 @@ static SDValue combineMinNumMaxNumImpl(const SDLoc &DL, EVT VT, SDValue LHS,
   case ISD::SETLE:
   case ISD::SETULT:
   case ISD::SETULE: {
-    // Since it's known never nan to get here already, either fminnum or
-    // fminnum_ieee are OK. Try the ieee version first, since it's fminnum is
-    // expanded in terms of it.
+    // Since it's known never nan to get here already, either fminimumnum,
+    // fminimum, fminnum, or fminnum_ieee are OK. Try the ieee version first,
+    // since it's fminnum is expanded in terms of it.
+    unsigned IEEE2019NumOpcode =
+        (LHS == True) ? ISD::FMINIMUMNUM : ISD::FMAXIMUMNUM;
+    if (TLI.isOperationLegal(IEEE2019NumOpcode, VT))
+      return DAG.getNode(IEEE2019NumOpcode, DL, VT, LHS, RHS);
+
+    unsigned IEEE2019Opcode = (LHS == True) ? ISD::FMINIMUM : ISD::FMAXIMUM;
----------------
arsenm wrote:

```suggestion
    unsigned IEEE2019Opcode = LHS == True ? ISD::FMINIMUM : ISD::FMAXIMUM;
```

https://github.com/llvm/llvm-project/pull/137449