[llvm] [AArch64][GlobalISel] Added support for neon right shifts (PR #170832)

[Matt Arsenault via llvm-commits]

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@@ -1857,6 +1857,98 @@ bool AArch64LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
     return LowerBinOp(TargetOpcode::G_SAVGFLOOR);
   case Intrinsic::aarch64_neon_srhadd:
     return LowerBinOp(TargetOpcode::G_SAVGCEIL);
+  case Intrinsic::aarch64_neon_sqshrn: {
+    if (MRI.getType(MI.getOperand(0).getReg()).isVector()) {
+      // Create right shift instruction. Get v. register the output is written
+      // to
+      auto Shr = MIB.buildInstr(AArch64::G_VASHR,
+                                {MRI.getType(MI.getOperand(2).getReg())},
+                                {MI.getOperand(2), MI.getOperand(3).getImm()});
+      // Build the narrow intrinsic, taking in the v. register of the shift
+      MIB.buildInstr(TargetOpcode::G_TRUNC_SSAT_S, {MI.getOperand(0)}, {Shr});
+      MI.eraseFromParent();
+    }
+    break;
+  }
+  case Intrinsic::aarch64_neon_sqshrun: {
+    if (MRI.getType(MI.getOperand(0).getReg()).isVector()) {
+      // Create right shift instruction. Get v. register the output is written
+      // to
+      auto Shr = MIB.buildInstr(AArch64::G_VASHR,
+                                {MRI.getType(MI.getOperand(2).getReg())},
+                                {MI.getOperand(2), MI.getOperand(3).getImm()});
+      // Build the narrow intrinsic, taking in the v. register of the shift
+      MIB.buildInstr(TargetOpcode::G_TRUNC_SSAT_U, {MI.getOperand(0)}, {Shr});
+      MI.eraseFromParent();
+    }
+    break;
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arsenm wrote:

Can you directly return here instead of breaking to the trivial return? 

https://github.com/llvm/llvm-project/pull/170832