[llvm] SelectionDAG: Support FMINIMUMNUM and FMINIMUM in combineMinNumMaxNumImpl (PR #137449)

[YunQiang Su via llvm-commits]

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@@ -11516,9 +11516,18 @@ static SDValue combineMinNumMaxNumImpl(const SDLoc &DL, EVT VT, SDValue LHS,
   case ISD::SETLE:
   case ISD::SETULT:
   case ISD::SETULE: {
-    // Since it's known never nan to get here already, either fminnum or
-    // fminnum_ieee are OK. Try the ieee version first, since it's fminnum is
-    // expanded in terms of it.
+    // Since it's known never nan to get here already, either fminimumnum,
+    // fminimum, fminnum, or fminnum_ieee are OK. Try the ieee version first,
+    // since it's fminnum is expanded in terms of it.
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wzssyqa wrote:

We try IEEE2019Num first due to that some architectures defines FMINIMUMNUM while not FMAXIMUM, such as RISCV64GC.

https://github.com/llvm/llvm-project/pull/137449