[llvm] [AArch64]Enable aggressive interleaving for A320 (PR #169825)

[Nashe Mncube via llvm-commits]

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@@ -175,6 +175,8 @@ void AArch64Subtarget::initializeProperties(bool HasMinSize) {
     MaxBytesForLoopAlignment = 16;
     break;
   case CortexA320:
+    AggressiveInterleaving = true;
+    [[fallthrough]];
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nasherm wrote:

Done

https://github.com/llvm/llvm-project/pull/169825