[llvm] [SDAG] Fix incorrect usage of VECREDUCE_ADD (PR #171459)

[Simon Pilgrim via llvm-commits]

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@@ -2664,7 +2664,8 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_COMPRESS(SDNode *N, SDValue &Lo,
 
   // We store LoVec and then insert HiVec starting at offset=|1s| in LoMask.
   SDValue WideMask =
-      DAG.getNode(ISD::ZERO_EXTEND, DL, LoMask.getValueType(), LoMask);
+      DAG.getNode(ISD::ZERO_EXTEND, DL,
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RKSimon wrote:

https://github.com/llvm/llvm-project/blob/578a26ada2e51e90733b50d048b0d74ac48ab21c/llvm/include/llvm/CodeGen/ValueTypes.h#L100-L109
The problem is if the original vector was simple (e.g. v512i32) - but you change it one that it isn't (e.g. v512i64) - MVT::changeVectorElementType is called and will assert internally:
https://github.com/llvm/llvm-project/blob/578a26ada2e51e90733b50d048b0d74ac48ab21c/llvm/include/llvm/CodeGenTypes/MachineValueType.h#L211-L218

https://github.com/llvm/llvm-project/pull/171459