[llvm] [LV] Add extra check for signed oveflow for SDiv/SRem (PR #170818)

[Shih-Po Hung via llvm-commits]

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@@ -2878,11 +2878,20 @@ bool LoopVectorizationCostModel::isPredicatedInst(Instruction *I) const {
              TheLoop->isLoopInvariant(cast<StoreInst>(I)->getValueOperand()));
   }
   case Instruction::UDiv:
-  case Instruction::SDiv:
-  case Instruction::SRem:
   case Instruction::URem:
     // If the divisor is loop-invariant no predication is needed.
     return !Legal->isInvariant(I->getOperand(1));
+  case Instruction::SDiv:
+  case Instruction::SRem: {
+    auto *LHS = I->getOperand(0);
+    auto *RHS = I->getOperand(1);
+    // If RHS is loop-invariant, signed-division overflow is possible
+    // when LHS can be INT_MIN.
+    ScalarEvolution &SE = *PSE.getSE();
+    return !Legal->isInvariant(RHS) ||
+           (!Legal->isInvariant(LHS) &&
+            SE.getSignedRangeMin(SE.getSCEV(LHS)).isMinSignedValue());
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arcbbb wrote:

Thanks. I missed that the issue was the masked‑off lanes, so I have updated it to run the range check only for SCEVAddRecExpr.

https://github.com/llvm/llvm-project/pull/170818