[llvm] 857b68f - [MC] Reorder TARGETInstrTable to shrink MCInstrDesc::ImplicitOffset (#171199)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 9 23:18:02 PST 2025
Author: Jay Foad
Date: 2025-12-10T07:17:58Z
New Revision: 857b68f112ecb61c43a9aa5bc50fc1e0e7dcaf57
URL: https://github.com/llvm/llvm-project/commit/857b68f112ecb61c43a9aa5bc50fc1e0e7dcaf57
DIFF: https://github.com/llvm/llvm-project/commit/857b68f112ecb61c43a9aa5bc50fc1e0e7dcaf57.diff
LOG: [MC] Reorder TARGETInstrTable to shrink MCInstrDesc::ImplicitOffset (#171199)
Put ImplicitOps[] before OperandInfo[] in the generated
TARGETInstrTable. This means that offsets to entries into the (small)
ImplicitOps table do not need to skip over the (large) OperandInfo
table.
This allows shrinking ImplicitOffset from 32 bits to 16 bits
(effectively reverting #138127) which will allow expanding Opcode
instead without increasing the size of MCInstrDesc.
Added:
Modified:
llvm/include/llvm/MC/MCInstrDesc.h
llvm/test/TableGen/RegClassByHwMode.td
llvm/test/TableGen/target-specialized-pseudos.td
llvm/utils/TableGen/InstrInfoEmitter.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/MC/MCInstrDesc.h b/llvm/include/llvm/MC/MCInstrDesc.h
index 5722213347d51..69dd3e2848832 100644
--- a/llvm/include/llvm/MC/MCInstrDesc.h
+++ b/llvm/include/llvm/MC/MCInstrDesc.h
@@ -211,7 +211,7 @@ class MCInstrDesc {
unsigned char NumImplicitUses; // Num of regs implicitly used
unsigned char NumImplicitDefs; // Num of regs implicitly defined
unsigned short OpInfoOffset; // Offset to info about operands
- unsigned int ImplicitOffset; // Offset to start of implicit op list
+ unsigned short ImplicitOffset; // Offset to start of implicit op list
uint64_t Flags; // Flags identifying machine instr class
uint64_t TSFlags; // Target Specific Flag values
diff --git a/llvm/test/TableGen/RegClassByHwMode.td b/llvm/test/TableGen/RegClassByHwMode.td
index 56a61eec3732f..a29c8747a7c20 100644
--- a/llvm/test/TableGen/RegClassByHwMode.td
+++ b/llvm/test/TableGen/RegClassByHwMode.td
@@ -24,7 +24,7 @@ include "Common/RegClassByHwModeCommon.td"
// INSTRINFO-NEXT: } // namespace llvm::MyTarget
-// INSTRINFO: { [[LOAD_STACK_GUARD_OPCODE]], 1, 1, 0, 0, 0, 0, [[LOAD_STACK_GUARD_OP_INDEX:[0-9]+]], MyTargetImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_
+// INSTRINFO: { [[LOAD_STACK_GUARD_OPCODE]], 1, 1, 0, 0, 0, 0, MyTargetOpInfoBase + [[LOAD_STACK_GUARD_OP_INDEX:[0-9]+]], 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_
// INSTRINFO: /* [[LOAD_STACK_GUARD_OP_INDEX]] */ { MyTarget::XRegs_EvenIfRequired, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 },
// INSTRINFO: { MyTarget::XRegs_EvenIfRequired, 0|(1<<MCOI::LookupRegClassByHwMode), MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
diff --git a/llvm/test/TableGen/target-specialized-pseudos.td b/llvm/test/TableGen/target-specialized-pseudos.td
index 3953a36101fe0..bf55926f21983 100644
--- a/llvm/test/TableGen/target-specialized-pseudos.td
+++ b/llvm/test/TableGen/target-specialized-pseudos.td
@@ -22,13 +22,13 @@
// CHECK: extern const MyTargetInstrTable MyTargetDescs = {
// CHECK-NEXT: {
-// CHECK-NEXT: { [[MY_MOV_OPCODE]], 2, 1, 2, 0, 0, 0, {{[0-9]+}}, MyTargetImpOpBase + 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MY_MOV
-// CHECK-NEXT: { [[G_UBFX_OPCODE]], 4, 1, 0, 0, 0, 0, {{[0-9]+}}, MyTargetImpOpBase + 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
+// CHECK-NEXT: { [[MY_MOV_OPCODE]], 2, 1, 2, 0, 0, 0, MyTargetOpInfoBase + {{[0-9]+}}, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // MY_MOV
+// CHECK-NEXT: { [[G_UBFX_OPCODE]], 4, 1, 0, 0, 0, 0, MyTargetOpInfoBase + {{[0-9]+}}, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // G_UBFX
-// ALLCASES: { [[PATCHABLE_TYPED_EVENT_CALL_OPCODE]], 3, 0, 0, 0, 0, 0, [[PATCHABLE_TYPED_EVENT_CALL_OP_ENTRY:[0-9]+]], MyTargetImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_
-// ALLCASES: { [[PATCHABLE_EVENT_CALL_OPCODE]], 2, 0, 0, 0, 0, 0, [[PATCHABLE_EVENT_CALL_OP_ENTRY:[0-9]+]], MyTargetImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_
-// ALLCASES: { [[PREALLOCATED_ARG_OPCODE]], 3, 1, 0, 0, 0, 0, [[PREALLOCATED_ARG_OP_ENTRY:[0-9]+]], MyTargetImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_
-// ALLCASES: { [[LOAD_STACK_GUARD_OPCODE]], 1, 1, 0, 0, 0, 0, [[LOAD_STACK_GUARD_OP_ENTRY:[0-9]+]], MyTargetImpOpBase + 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_
+// ALLCASES: { [[PATCHABLE_TYPED_EVENT_CALL_OPCODE]], 3, 0, 0, 0, 0, 0, MyTargetOpInfoBase + [[PATCHABLE_TYPED_EVENT_CALL_OP_ENTRY:[0-9]+]], 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_
+// ALLCASES: { [[PATCHABLE_EVENT_CALL_OPCODE]], 2, 0, 0, 0, 0, 0, MyTargetOpInfoBase + [[PATCHABLE_EVENT_CALL_OP_ENTRY:[0-9]+]], 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_
+// ALLCASES: { [[PREALLOCATED_ARG_OPCODE]], 3, 1, 0, 0, 0, 0, MyTargetOpInfoBase + [[PREALLOCATED_ARG_OP_ENTRY:[0-9]+]], 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_
+// ALLCASES: { [[LOAD_STACK_GUARD_OPCODE]], 1, 1, 0, 0, 0, 0, MyTargetOpInfoBase + [[LOAD_STACK_GUARD_OP_ENTRY:[0-9]+]], 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // anonymous_
// CHECK: /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
diff --git a/llvm/utils/TableGen/InstrInfoEmitter.cpp b/llvm/utils/TableGen/InstrInfoEmitter.cpp
index 9cd6ad28b1be4..0faef33a386e7 100644
--- a/llvm/utils/TableGen/InstrInfoEmitter.cpp
+++ b/llvm/utils/TableGen/InstrInfoEmitter.cpp
@@ -959,13 +959,19 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
OS << "struct " << TargetName << "InstrTable {\n";
OS << " MCInstrDesc Insts[" << NumberedInstructions.size() << "];\n";
+ OS << " static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "
+ "\"Unwanted padding between Insts and ImplicitOps\");\n";
+ OS << " MCPhysReg ImplicitOps[" << std::max(ImplicitListSize, 1U)
+ << "];\n";
+ // Emit enough padding to make ImplicitOps plus Padding add up to the size
+ // of a whole number of MCOperandInfo structs. This allows us to index into
+ // the OperandInfo array starting from the end of the Insts array, by
+ // biasing the indices by the OpInfoBase value calculated below.
+ OS << " char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % "
+ "sizeof(MCOperandInfo)];\n";
OS << " static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "
"\"Unwanted padding between Insts and OperandInfo\");\n";
OS << " MCOperandInfo OperandInfo[" << OperandInfoSize << "];\n";
- OS << " static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "
- "\"Unwanted padding between OperandInfo and ImplicitOps\");\n";
- OS << " MCPhysReg ImplicitOps[" << std::max(ImplicitListSize, 1U)
- << "];\n";
OS << "};";
}
@@ -991,9 +997,12 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
// Emit all of the MCInstrDesc records in reverse ENUM ordering.
Timer.startTimer("Emit InstrDesc records");
- OS << "static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);\n";
- OS << "static constexpr unsigned " << TargetName << "ImpOpBase = sizeof "
- << TargetName << "InstrTable::OperandInfo / (sizeof(MCPhysReg));\n\n";
+ OS << "static_assert((sizeof " << TargetName
+ << "InstrTable::ImplicitOps + sizeof " << TargetName
+ << "InstrTable::Padding) % sizeof(MCOperandInfo) == 0);\n";
+ OS << "static constexpr unsigned " << TargetName << "OpInfoBase = (sizeof "
+ << TargetName << "InstrTable::ImplicitOps + sizeof " << TargetName
+ << "InstrTable::Padding) / sizeof(MCOperandInfo);\n\n";
OS << "extern const " << TargetName << "InstrTable " << TargetName
<< "Descs = {\n {\n";
@@ -1013,12 +1022,6 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
OS << " }, {\n";
- // Emit all of the operand info records.
- Timer.startTimer("Emit operand info");
- EmitOperandInfo(OS, OperandInfoList);
-
- OS << " }, {\n";
-
// Emit all of the instruction's implicit uses and defs.
Timer.startTimer("Emit uses/defs");
for (auto &List : ImplicitLists) {
@@ -1028,6 +1031,17 @@ void InstrInfoEmitter::run(raw_ostream &OS) {
OS << '\n';
}
+ OS << " }, {\n";
+
+ // Emit the padding.
+ OS << " 0\n";
+
+ OS << " }, {\n";
+
+ // Emit all of the operand info records.
+ Timer.startTimer("Emit operand info");
+ EmitOperandInfo(OS, OperandInfoList);
+
OS << " }\n};\n\n";
// Emit the array of instruction names.
@@ -1291,11 +1305,11 @@ void InstrInfoEmitter::emitRecord(
// Emit the operand info offset.
OperandInfoTy OperandInfo = GetOperandInfo(Inst);
- OS << OperandInfoMap.find(OperandInfo)->second << ",\t";
+ OS << Target.getName() << "OpInfoBase + "
+ << OperandInfoMap.find(OperandInfo)->second << ",\t";
// Emit implicit operand base.
- OS << Target.getName() << "ImpOpBase + " << EmittedLists[ImplicitOps]
- << ",\t0";
+ OS << EmittedLists[ImplicitOps] << ",\t0";
// Emit all of the target independent flags...
if (Inst.isPreISelOpcode)
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