[llvm] [RISCV] Fix wrong use of SiFiveP400GetVLMAX in RISCVSchedSiFiveP600 (PR #171562)

Pengcheng Wang via llvm-commits llvm-commits at lists.llvm.org
Tue Dec 9 21:59:19 PST 2025

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https://github.com/wangpc-pp closed https://github.com/llvm/llvm-project/pull/171562

Previous message: [llvm] [RISCV] Fix wrong use of SiFiveP400GetVLMAX in RISCVSchedSiFiveP600 (PR #171562)
Next message: [llvm] 21871bb - [RISCV] Add fractional LMUL register classes for inline assembly. (#171278)
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