[llvm] 13d99e3 - [RISCV] Fix wrong use of SiFiveP400GetVLMAX in RISCVSchedSiFiveP600 (#171562)

[via llvm-commits]

Author: Pengcheng Wang
Date: 2025-12-10T13:59:13+08:00
New Revision: 13d99e3e6ea583ffc26469de041bf5b7a55ba67b

URL: https://github.com/llvm/llvm-project/commit/13d99e3e6ea583ffc26469de041bf5b7a55ba67b
DIFF: https://github.com/llvm/llvm-project/commit/13d99e3e6ea583ffc26469de041bf5b7a55ba67b.diff

LOG: [RISCV] Fix wrong use of SiFiveP400GetVLMAX in RISCVSchedSiFiveP600 (#171562)

There is no difference of functionality and I believe this is a
copy-paste mistake. :-)

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
index c989e1ceb4b0e..db9b17f193a56 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
@@ -48,7 +48,7 @@ class SiFiveP600GetVLMAX<string mx, int sew> {
 }
 
 class SiFiveP600StridedLdStLatency<string mx, int sew> {
-  defvar VL = SiFiveP400GetVLMAX<mx, sew>.val;
+  defvar VL = SiFiveP600GetVLMAX<mx, sew>.val;
   int val = !cond(
     !eq(VL, 2):  13,
     !eq(VL, 4):  18,