[llvm] [RISCV] Generate Xqcilsm LWMI/SWMI load/store multiple instructions (PR #171079)

[Sudharsan Veeravalli via llvm-commits]

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@@ -227,6 +311,25 @@ bool RISCVLoadStoreOpt::tryConvertToLdStPair(
   return true;
 }
 
+// Merge two adjacent load/store instructions into a paired instruction.
+// This function calls the vendor specific implementation that seelects the
+// appropriate paired opcode, verifies that the memory operand is properly
+// aligned, and checks that the offset is valid. If all conditions are met, it
+// builds and inserts the paired instruction.
+bool RISCVLoadStoreOpt::tryConvertToLdStPair(
+    MachineBasicBlock::iterator First, MachineBasicBlock::iterator Second) {
+  MachineFunction *MF = First->getMF();
+  const RISCVSubtarget &STI = MF->getSubtarget<RISCVSubtarget>();
+
+  // Try converting to QC_LWMI/QC_SWMI if the XQCILSM extension is enabled.
+  if (!STI.is64Bit() && STI.hasVendorXqcilsm()) {
+    return tryConvertToXqcilsmLdStPair(MF, First, Second);
+  }
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svs-quic wrote:

Done

https://github.com/llvm/llvm-project/pull/171079