[llvm] [X86] Trap instructions don't need side effects (PR #171552)
Harald van Dijk via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 9 17:46:54 PST 2025
https://github.com/hvdijk created https://github.com/llvm/llvm-project/pull/171552
TargetSelectionDAG.td defines *trap with SDNPSideEffect to indicate that the pattern has side effects that are not otherwise modelled. TableGen requires that when a pattern has side effects, the corresponding instructions do too. However, that does not take into account that instructions have more fine-grained flags, and what is a side effect on the pattern need not be a side effect on the instruction.
Specifically, this commit modifies TableGen to permit patterns with side effects to map to instructions with hasSideEffects = 0, isTrap = 1. This is never inferred: the TableGen change only permits behaviour that was previously rejected. Anything that TableGen previously permitted continues to be treated exactly the same, to ensure there are no unexpected effects on other targets.
The X86 trap instructions are modified to make use of this new option.
>From 79c662b0fe0a68b5bee04e9cb9e557aacff4ca21 Mon Sep 17 00:00:00 2001
From: Harald van Dijk <hdijk at accesssoftek.com>
Date: Wed, 10 Dec 2025 01:44:47 +0000
Subject: [PATCH] [X86] Trap instructions don't need side effects
TargetSelectionDAG.td defines *trap with SDNPSideEffect to indicate that
the pattern has side effects that are not otherwise modelled. TableGen
requires that when a pattern has side effects, the corresponding
instructions do too. However, that does not take into account that
instructions have more fine-grained flags, and what is a side effect on
the pattern need not be a side effect on the instruction.
Specifically, this commit modifies TableGen to permit patterns with side
effects to map to instructions with hasSideEffects = 0, isTrap = 1. This
is never inferred: the TableGen change only permits behaviour that was
previously rejected. Anything that TableGen previously permitted
continues to be treated exactly the same, to ensure there are no
unexpected effects on other targets.
The X86 trap instructions are modified to make use of this new option.
---
llvm/lib/Target/X86/X86InstrSystem.td | 2 +-
.../X86/AlderlakeP/resources-x86_64.s | 2 +-
.../llvm-mca/X86/Atom/resources-x86_64.s | 2 +-
.../llvm-mca/X86/Barcelona/resources-x86_64.s | 2 +-
.../llvm-mca/X86/BdVer2/resources-x86_64.s | 2 +-
.../llvm-mca/X86/Broadwell/resources-x86_64.s | 2 +-
.../llvm-mca/X86/BtVer2/resources-x86_64.s | 2 +-
.../llvm-mca/X86/Generic/resources-x86_64.s | 2 +-
.../llvm-mca/X86/Haswell/resources-x86_64.s | 2 +-
.../X86/IceLakeServer/resources-x86_64.s | 2 +-
.../X86/LunarlakeP/resources-x86_64.s | 2 +-
.../tools/llvm-mca/X86/SLM/resources-x86_64.s | 2 +-
.../X86/SandyBridge/resources-x86_64.s | 2 +-
.../X86/SapphireRapids/resources-x86_64.s | 2 +-
.../X86/SkylakeClient/resources-x86_64.s | 2 +-
.../X86/SkylakeServer/resources-x86_64.s | 2 +-
.../llvm-mca/X86/Znver1/resources-x86_64.s | 2 +-
.../llvm-mca/X86/Znver2/resources-x86_64.s | 2 +-
.../llvm-mca/X86/Znver3/resources-x86_64.s | 2 +-
.../llvm-mca/X86/Znver4/resources-x86_64.s | 2 +-
.../TableGen/Common/CodeGenDAGPatterns.cpp | 29 ++++++++++++-------
21 files changed, 38 insertions(+), 31 deletions(-)
diff --git a/llvm/lib/Target/X86/X86InstrSystem.td b/llvm/lib/Target/X86/X86InstrSystem.td
index eb0b5a43afdf9..f2257eeb58c6f 100644
--- a/llvm/lib/Target/X86/X86InstrSystem.td
+++ b/llvm/lib/Target/X86/X86InstrSystem.td
@@ -21,7 +21,7 @@ def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
// CPU flow control instructions
-let mayLoad = 1, mayStore = 0, hasSideEffects = 1, isTrap = 1 in {
+let mayLoad = 1, mayStore = 0, hasSideEffects = 0, isTrap = 1 in {
def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
def UD1Wm : I<0xB9, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-x86_64.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-x86_64.s
index 5cad9072f37c6..516b1ad00864e 100644
--- a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-x86_64.s
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-x86_64.s
@@ -1876,7 +1876,7 @@ xorq (%rax), %rdi
# CHECK-NEXT: 2 7 0.33 * testq $7, (%rax)
# CHECK-NEXT: 1 2 0.20 testq %rsi, %rdi
# CHECK-NEXT: 2 7 0.33 * testq %rsi, (%rax)
-# CHECK-NEXT: 1 100 0.25 * U ud2
+# CHECK-NEXT: 1 100 0.25 * ud2
# CHECK-NEXT: 144 100 35.50 U wrmsr
# CHECK-NEXT: 3 2 0.60 xaddb %bl, %cl
# CHECK-NEXT: 5 13 0.50 * * xaddb %bl, (%rcx)
diff --git a/llvm/test/tools/llvm-mca/X86/Atom/resources-x86_64.s b/llvm/test/tools/llvm-mca/X86/Atom/resources-x86_64.s
index 2d7764627ef1b..4fdaf1e2ced0a 100644
--- a/llvm/test/tools/llvm-mca/X86/Atom/resources-x86_64.s
+++ b/llvm/test/tools/llvm-mca/X86/Atom/resources-x86_64.s
@@ -1876,7 +1876,7 @@ xorq (%rax), %rdi
# CHECK-NEXT: 1 1 1.00 * testq $7, (%rax)
# CHECK-NEXT: 1 1 0.50 testq %rsi, %rdi
# CHECK-NEXT: 1 1 1.00 * testq %rsi, (%rax)
-# CHECK-NEXT: 1 100 0.50 * U ud2
+# CHECK-NEXT: 1 100 0.50 * ud2
# CHECK-NEXT: 1 202 101.00 U wrmsr
# CHECK-NEXT: 1 2 1.00 xaddb %bl, %cl
# CHECK-NEXT: 1 3 1.50 * * xaddb %bl, (%rcx)
diff --git a/llvm/test/tools/llvm-mca/X86/Barcelona/resources-x86_64.s b/llvm/test/tools/llvm-mca/X86/Barcelona/resources-x86_64.s
index 90cbb4891e75d..b47386732b16c 100644
--- a/llvm/test/tools/llvm-mca/X86/Barcelona/resources-x86_64.s
+++ b/llvm/test/tools/llvm-mca/X86/Barcelona/resources-x86_64.s
@@ -1876,7 +1876,7 @@ xorq (%rax), %rdi
# CHECK-NEXT: 2 6 0.50 * testq $7, (%rax)
# CHECK-NEXT: 1 1 0.33 testq %rsi, %rdi
# CHECK-NEXT: 2 6 0.50 * testq %rsi, (%rax)
-# CHECK-NEXT: 1 100 0.33 * U ud2
+# CHECK-NEXT: 1 100 0.33 * ud2
# CHECK-NEXT: 1 100 0.33 U wrmsr
# CHECK-NEXT: 3 2 1.00 xaddb %bl, %cl
# CHECK-NEXT: 5 8 1.00 * * xaddb %bl, (%rcx)
diff --git a/llvm/test/tools/llvm-mca/X86/BdVer2/resources-x86_64.s b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-x86_64.s
index e7a0125bd0957..3b2beebd61242 100644
--- a/llvm/test/tools/llvm-mca/X86/BdVer2/resources-x86_64.s
+++ b/llvm/test/tools/llvm-mca/X86/BdVer2/resources-x86_64.s
@@ -1876,7 +1876,7 @@ xorq (%rax), %rdi
# CHECK-NEXT: 1 5 1.50 * testq $7, (%rax)
# CHECK-NEXT: 1 1 1.00 testq %rsi, %rdi
# CHECK-NEXT: 1 5 1.50 * testq %rsi, (%rax)
-# CHECK-NEXT: 1 100 0.50 * U ud2
+# CHECK-NEXT: 1 100 0.50 * ud2
# CHECK-NEXT: 1 100 0.50 U wrmsr
# CHECK-NEXT: 2 1 1.00 xaddb %bl, %cl
# CHECK-NEXT: 4 6 20.00 * * xaddb %bl, (%rcx)
diff --git a/llvm/test/tools/llvm-mca/X86/Broadwell/resources-x86_64.s b/llvm/test/tools/llvm-mca/X86/Broadwell/resources-x86_64.s
index bd9cf510e002f..1a5be98fccf92 100644
--- a/llvm/test/tools/llvm-mca/X86/Broadwell/resources-x86_64.s
+++ b/llvm/test/tools/llvm-mca/X86/Broadwell/resources-x86_64.s
@@ -1876,7 +1876,7 @@ xorq (%rax), %rdi
# CHECK-NEXT: 2 6 0.50 * testq $7, (%rax)
# CHECK-NEXT: 1 1 0.25 testq %rsi, %rdi
# CHECK-NEXT: 2 6 0.50 * testq %rsi, (%rax)
-# CHECK-NEXT: 1 100 0.25 * U ud2
+# CHECK-NEXT: 1 100 0.25 * ud2
# CHECK-NEXT: 1 100 0.25 U wrmsr
# CHECK-NEXT: 3 2 0.75 xaddb %bl, %cl
# CHECK-NEXT: 5 7 1.00 * * xaddb %bl, (%rcx)
diff --git a/llvm/test/tools/llvm-mca/X86/BtVer2/resources-x86_64.s b/llvm/test/tools/llvm-mca/X86/BtVer2/resources-x86_64.s
index ab6945ec523f1..881737d2a2239 100644
--- a/llvm/test/tools/llvm-mca/X86/BtVer2/resources-x86_64.s
+++ b/llvm/test/tools/llvm-mca/X86/BtVer2/resources-x86_64.s
@@ -1876,7 +1876,7 @@ xorq (%rax), %rdi
# CHECK-NEXT: 1 4 1.00 * testq $7, (%rax)
# CHECK-NEXT: 1 1 0.50 testq %rsi, %rdi
# CHECK-NEXT: 1 4 1.00 * testq %rsi, (%rax)
-# CHECK-NEXT: 1 100 0.50 * U ud2
+# CHECK-NEXT: 1 100 0.50 * ud2
# CHECK-NEXT: 1 100 0.50 U wrmsr
# CHECK-NEXT: 3 2 1.50 xaddb %bl, %cl
# CHECK-NEXT: 4 11 1.50 * * xaddb %bl, (%rcx)
diff --git a/llvm/test/tools/llvm-mca/X86/Generic/resources-x86_64.s b/llvm/test/tools/llvm-mca/X86/Generic/resources-x86_64.s
index 90cbb4891e75d..b47386732b16c 100644
--- a/llvm/test/tools/llvm-mca/X86/Generic/resources-x86_64.s
+++ b/llvm/test/tools/llvm-mca/X86/Generic/resources-x86_64.s
@@ -1876,7 +1876,7 @@ xorq (%rax), %rdi
# CHECK-NEXT: 2 6 0.50 * testq $7, (%rax)
# CHECK-NEXT: 1 1 0.33 testq %rsi, %rdi
# CHECK-NEXT: 2 6 0.50 * testq %rsi, (%rax)
-# CHECK-NEXT: 1 100 0.33 * U ud2
+# CHECK-NEXT: 1 100 0.33 * ud2
# CHECK-NEXT: 1 100 0.33 U wrmsr
# CHECK-NEXT: 3 2 1.00 xaddb %bl, %cl
# CHECK-NEXT: 5 8 1.00 * * xaddb %bl, (%rcx)
diff --git a/llvm/test/tools/llvm-mca/X86/Haswell/resources-x86_64.s b/llvm/test/tools/llvm-mca/X86/Haswell/resources-x86_64.s
index c85ad704a0aa2..08c41efde9e07 100644
--- a/llvm/test/tools/llvm-mca/X86/Haswell/resources-x86_64.s
+++ b/llvm/test/tools/llvm-mca/X86/Haswell/resources-x86_64.s
@@ -1876,7 +1876,7 @@ xorq (%rax), %rdi
# CHECK-NEXT: 2 6 0.50 * testq $7, (%rax)
# CHECK-NEXT: 1 1 0.25 testq %rsi, %rdi
# CHECK-NEXT: 2 6 0.50 * testq %rsi, (%rax)
-# CHECK-NEXT: 1 100 0.25 * U ud2
+# CHECK-NEXT: 1 100 0.25 * ud2
# CHECK-NEXT: 1 100 0.25 U wrmsr
# CHECK-NEXT: 3 2 0.75 xaddb %bl, %cl
# CHECK-NEXT: 5 8 1.00 * * xaddb %bl, (%rcx)
diff --git a/llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-x86_64.s b/llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-x86_64.s
index f00ae58e956de..67f8aaccea561 100644
--- a/llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-x86_64.s
+++ b/llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-x86_64.s
@@ -1876,7 +1876,7 @@ xorq (%rax), %rdi
# CHECK-NEXT: 2 6 0.50 * testq $7, (%rax)
# CHECK-NEXT: 1 1 0.25 testq %rsi, %rdi
# CHECK-NEXT: 2 6 0.50 * testq %rsi, (%rax)
-# CHECK-NEXT: 1 100 0.25 * U ud2
+# CHECK-NEXT: 1 100 0.25 * ud2
# CHECK-NEXT: 1 100 0.25 U wrmsr
# CHECK-NEXT: 3 2 0.75 xaddb %bl, %cl
# CHECK-NEXT: 5 7 0.50 * * xaddb %bl, (%rcx)
diff --git a/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-x86_64.s b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-x86_64.s
index c0fb7f6e6923c..4f227a7430864 100644
--- a/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-x86_64.s
+++ b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-x86_64.s
@@ -1873,7 +1873,7 @@ xorq (%rax), %rdi
# CHECK-NEXT: 2 7 0.33 * testq $7, (%rax)
# CHECK-NEXT: 1 2 0.17 testq %rsi, %rdi
# CHECK-NEXT: 2 7 0.33 * testq %rsi, (%rax)
-# CHECK-NEXT: 1 100 0.17 * U ud2
+# CHECK-NEXT: 1 100 0.17 * ud2
# CHECK-NEXT: 144 100 21.00 U wrmsr
# CHECK-NEXT: 3 2 0.50 xaddb %bl, %cl
# CHECK-NEXT: 5 13 0.50 * * xaddb %bl, (%rcx)
diff --git a/llvm/test/tools/llvm-mca/X86/SLM/resources-x86_64.s b/llvm/test/tools/llvm-mca/X86/SLM/resources-x86_64.s
index e597e976f1029..5863a15774301 100644
--- a/llvm/test/tools/llvm-mca/X86/SLM/resources-x86_64.s
+++ b/llvm/test/tools/llvm-mca/X86/SLM/resources-x86_64.s
@@ -1876,7 +1876,7 @@ xorq (%rax), %rdi
# CHECK-NEXT: 1 4 1.00 * testq $7, (%rax)
# CHECK-NEXT: 1 1 0.50 testq %rsi, %rdi
# CHECK-NEXT: 1 4 1.00 * testq %rsi, (%rax)
-# CHECK-NEXT: 1 100 1.00 * U ud2
+# CHECK-NEXT: 1 100 1.00 * ud2
# CHECK-NEXT: 1 100 1.00 U wrmsr
# CHECK-NEXT: 3 3 1.50 xaddb %bl, %cl
# CHECK-NEXT: 1 4 2.00 * * xaddb %bl, (%rcx)
diff --git a/llvm/test/tools/llvm-mca/X86/SandyBridge/resources-x86_64.s b/llvm/test/tools/llvm-mca/X86/SandyBridge/resources-x86_64.s
index 974fbdd04cec1..17f6531a99084 100644
--- a/llvm/test/tools/llvm-mca/X86/SandyBridge/resources-x86_64.s
+++ b/llvm/test/tools/llvm-mca/X86/SandyBridge/resources-x86_64.s
@@ -1876,7 +1876,7 @@ xorq (%rax), %rdi
# CHECK-NEXT: 2 6 0.50 * testq $7, (%rax)
# CHECK-NEXT: 1 1 0.33 testq %rsi, %rdi
# CHECK-NEXT: 2 6 0.50 * testq %rsi, (%rax)
-# CHECK-NEXT: 1 100 0.33 * U ud2
+# CHECK-NEXT: 1 100 0.33 * ud2
# CHECK-NEXT: 1 100 0.33 U wrmsr
# CHECK-NEXT: 3 2 1.00 xaddb %bl, %cl
# CHECK-NEXT: 5 8 1.00 * * xaddb %bl, (%rcx)
diff --git a/llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-x86_64.s b/llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-x86_64.s
index d41abf60de183..355947e5c9400 100644
--- a/llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-x86_64.s
+++ b/llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-x86_64.s
@@ -1876,7 +1876,7 @@ xorq (%rax), %rdi
# CHECK-NEXT: 2 7 0.33 * testq $7, (%rax)
# CHECK-NEXT: 1 2 0.20 testq %rsi, %rdi
# CHECK-NEXT: 2 7 0.33 * testq %rsi, (%rax)
-# CHECK-NEXT: 1 100 0.25 * U ud2
+# CHECK-NEXT: 1 100 0.25 * ud2
# CHECK-NEXT: 144 100 35.50 U wrmsr
# CHECK-NEXT: 3 2 0.60 xaddb %bl, %cl
# CHECK-NEXT: 5 13 0.50 * * xaddb %bl, (%rcx)
diff --git a/llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-x86_64.s b/llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-x86_64.s
index dbcf5f9735d6e..55b0f61827e44 100644
--- a/llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-x86_64.s
+++ b/llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-x86_64.s
@@ -1876,7 +1876,7 @@ xorq (%rax), %rdi
# CHECK-NEXT: 2 6 0.50 * testq $7, (%rax)
# CHECK-NEXT: 1 1 0.25 testq %rsi, %rdi
# CHECK-NEXT: 2 6 0.50 * testq %rsi, (%rax)
-# CHECK-NEXT: 1 100 0.25 * U ud2
+# CHECK-NEXT: 1 100 0.25 * ud2
# CHECK-NEXT: 1 100 0.25 U wrmsr
# CHECK-NEXT: 3 2 0.75 xaddb %bl, %cl
# CHECK-NEXT: 5 7 1.00 * * xaddb %bl, (%rcx)
diff --git a/llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-x86_64.s b/llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-x86_64.s
index a1de2b929df6c..afa109176552b 100644
--- a/llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-x86_64.s
+++ b/llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-x86_64.s
@@ -1876,7 +1876,7 @@ xorq (%rax), %rdi
# CHECK-NEXT: 2 6 0.50 * testq $7, (%rax)
# CHECK-NEXT: 1 1 0.25 testq %rsi, %rdi
# CHECK-NEXT: 2 6 0.50 * testq %rsi, (%rax)
-# CHECK-NEXT: 1 100 0.25 * U ud2
+# CHECK-NEXT: 1 100 0.25 * ud2
# CHECK-NEXT: 1 100 0.25 U wrmsr
# CHECK-NEXT: 3 2 0.75 xaddb %bl, %cl
# CHECK-NEXT: 5 7 1.00 * * xaddb %bl, (%rcx)
diff --git a/llvm/test/tools/llvm-mca/X86/Znver1/resources-x86_64.s b/llvm/test/tools/llvm-mca/X86/Znver1/resources-x86_64.s
index 5ed3284b25e43..f9f781330c265 100644
--- a/llvm/test/tools/llvm-mca/X86/Znver1/resources-x86_64.s
+++ b/llvm/test/tools/llvm-mca/X86/Znver1/resources-x86_64.s
@@ -1876,7 +1876,7 @@ xorq (%rax), %rdi
# CHECK-NEXT: 2 5 0.50 * testq $7, (%rax)
# CHECK-NEXT: 1 1 0.25 testq %rsi, %rdi
# CHECK-NEXT: 2 5 0.50 * testq %rsi, (%rax)
-# CHECK-NEXT: 1 100 0.25 * U ud2
+# CHECK-NEXT: 1 100 0.25 * ud2
# CHECK-NEXT: 1 100 0.25 U wrmsr
# CHECK-NEXT: 1 1 0.25 xaddb %bl, %cl
# CHECK-NEXT: 1 100 0.25 * * xaddb %bl, (%rcx)
diff --git a/llvm/test/tools/llvm-mca/X86/Znver2/resources-x86_64.s b/llvm/test/tools/llvm-mca/X86/Znver2/resources-x86_64.s
index ffa65b880164e..ad263f15475bf 100644
--- a/llvm/test/tools/llvm-mca/X86/Znver2/resources-x86_64.s
+++ b/llvm/test/tools/llvm-mca/X86/Znver2/resources-x86_64.s
@@ -1876,7 +1876,7 @@ xorq (%rax), %rdi
# CHECK-NEXT: 2 5 0.33 * testq $7, (%rax)
# CHECK-NEXT: 1 1 0.25 testq %rsi, %rdi
# CHECK-NEXT: 2 5 0.33 * testq %rsi, (%rax)
-# CHECK-NEXT: 1 100 0.25 * U ud2
+# CHECK-NEXT: 1 100 0.25 * ud2
# CHECK-NEXT: 1 100 0.25 U wrmsr
# CHECK-NEXT: 1 1 0.25 xaddb %bl, %cl
# CHECK-NEXT: 1 100 0.25 * * xaddb %bl, (%rcx)
diff --git a/llvm/test/tools/llvm-mca/X86/Znver3/resources-x86_64.s b/llvm/test/tools/llvm-mca/X86/Znver3/resources-x86_64.s
index 41ec631dc3fbb..eba418ced9bca 100644
--- a/llvm/test/tools/llvm-mca/X86/Znver3/resources-x86_64.s
+++ b/llvm/test/tools/llvm-mca/X86/Znver3/resources-x86_64.s
@@ -1876,7 +1876,7 @@ xorq (%rax), %rdi
# CHECK-NEXT: 1 5 0.33 * testq $7, (%rax)
# CHECK-NEXT: 1 1 0.25 testq %rsi, %rdi
# CHECK-NEXT: 1 5 0.33 * testq %rsi, (%rax)
-# CHECK-NEXT: 100 100 25.00 * U ud2
+# CHECK-NEXT: 100 100 25.00 * ud2
# CHECK-NEXT: 100 100 25.00 U wrmsr
# CHECK-NEXT: 2 0 2.00 xaddb %bl, %cl
# CHECK-NEXT: 1 5 0.67 * * xaddb %bl, (%rcx)
diff --git a/llvm/test/tools/llvm-mca/X86/Znver4/resources-x86_64.s b/llvm/test/tools/llvm-mca/X86/Znver4/resources-x86_64.s
index 886d9c6930418..3c3dca8cdd32e 100644
--- a/llvm/test/tools/llvm-mca/X86/Znver4/resources-x86_64.s
+++ b/llvm/test/tools/llvm-mca/X86/Znver4/resources-x86_64.s
@@ -1876,7 +1876,7 @@ xorq (%rax), %rdi
# CHECK-NEXT: 1 5 0.33 * testq $7, (%rax)
# CHECK-NEXT: 1 1 0.25 testq %rsi, %rdi
# CHECK-NEXT: 1 5 0.33 * testq %rsi, (%rax)
-# CHECK-NEXT: 100 100 25.00 * U ud2
+# CHECK-NEXT: 100 100 25.00 * ud2
# CHECK-NEXT: 100 100 25.00 U wrmsr
# CHECK-NEXT: 2 0 2.00 xaddb %bl, %cl
# CHECK-NEXT: 1 5 0.67 * * xaddb %bl, (%rcx)
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
index 364817fa6d030..a0cf589fd3cbf 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
@@ -3773,25 +3773,32 @@ static bool InferFromPattern(CodeGenInstruction &InstInfo,
InstInfo.InferredFrom = PatDef;
// Check explicitly set flags for consistency.
- if (InstInfo.hasSideEffects != PatInfo.hasSideEffects &&
- !InstInfo.hasSideEffects_Unset) {
+ if (InstInfo.hasSideEffects_Unset) {
+ InstInfo.hasSideEffects = PatInfo.hasSideEffects;
+ } else if (InstInfo.hasSideEffects != PatInfo.hasSideEffects) {
// Allow explicitly setting hasSideEffects = 1 on instructions, even when
// the pattern has no side effects. That could be useful for div/rem
// instructions that may trap.
- if (!InstInfo.hasSideEffects) {
+ // Allow setting isTrap = 1 on instructions instead, if we know better at
+ // the instruction level what the side effect is.
+ if (!InstInfo.hasSideEffects && !InstInfo.isTrap) {
Error = true;
PrintError(PatDef->getLoc(), "Pattern doesn't match hasSideEffects = " +
Twine(InstInfo.hasSideEffects));
}
}
- if (InstInfo.mayStore != PatInfo.mayStore && !InstInfo.mayStore_Unset) {
+ if (InstInfo.mayStore_Unset) {
+ InstInfo.mayStore = PatInfo.mayStore;
+ } else if (InstInfo.mayStore != PatInfo.mayStore) {
Error = true;
PrintError(PatDef->getLoc(),
"Pattern doesn't match mayStore = " + Twine(InstInfo.mayStore));
}
- if (InstInfo.mayLoad != PatInfo.mayLoad && !InstInfo.mayLoad_Unset) {
+ if (InstInfo.mayLoad_Unset) {
+ InstInfo.mayLoad = PatInfo.mayLoad;
+ } else if (InstInfo.mayLoad != PatInfo.mayLoad) {
// Allow explicitly setting mayLoad = 1, even when the pattern has no loads.
// Some targets translate immediates to loads.
if (!InstInfo.mayLoad) {
@@ -3801,11 +3808,6 @@ static bool InferFromPattern(CodeGenInstruction &InstInfo,
}
}
- // Transfer inferred flags.
- InstInfo.hasSideEffects |= PatInfo.hasSideEffects;
- InstInfo.mayStore |= PatInfo.mayStore;
- InstInfo.mayLoad |= PatInfo.mayLoad;
-
// These flags are silently added without any verification.
// FIXME: To match historical behavior of TableGen, for now add those flags
// only when we're inferring from the primary instruction pattern.
@@ -4263,11 +4265,13 @@ void CodeGenDAGPatterns::VerifyInstructionFlags() {
continue;
// Count the number of instructions with each flag set.
+ unsigned NumTraps = 0;
unsigned NumSideEffects = 0;
unsigned NumStores = 0;
unsigned NumLoads = 0;
for (const Record *Instr : Instrs) {
const CodeGenInstruction &InstInfo = Target.getInstruction(Instr);
+ NumTraps += InstInfo.isTrap;
NumSideEffects += InstInfo.hasSideEffects;
NumStores += InstInfo.mayStore;
NumLoads += InstInfo.mayLoad;
@@ -4282,7 +4286,10 @@ void CodeGenDAGPatterns::VerifyInstructionFlags() {
// Check for missing flags in the output.
// Permit extra flags for now at least.
- if (PatInfo.hasSideEffects && !NumSideEffects)
+
+ // Allow instructions to be marked isTrap instead of hasSideEffects if we
+ // know how the pattern's side effect manifests.
+ if (PatInfo.hasSideEffects && !NumSideEffects && !NumTraps)
Msgs.push_back("pattern has side effects, but hasSideEffects isn't set");
// Don't verify store flags on instructions with side effects. At least for
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