[llvm] [LLVM][AArch64] Remove hasNoSchedulingInfo from SVE pseudo instructions. (PR #171487)
Paul Walker via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 9 10:23:07 PST 2025
https://github.com/paulwalker-arm created https://github.com/llvm/llvm-project/pull/171487
These should always have the same schediling information as their real instruction counterparts. Removing this property means we'll catch missing entries when building the compiler.
>From 4bad0253664d1c92dcc6902df9be83dc525e798c Mon Sep 17 00:00:00 2001
From: Paul Walker <paul.walker at arm.com>
Date: Tue, 9 Dec 2025 17:54:27 +0000
Subject: [PATCH] [LLVM][AArch64] Remove hasNoSchedulingInfo from SVE pseudo
instructions.
These should always have the same schediling information as their real
instruction counterparts. Removing this property means we'll catch
missing entries when building the compiler.
---
llvm/lib/Target/AArch64/AArch64SchedA320.td | 2 +-
llvm/lib/Target/AArch64/AArch64SchedA510.td | 2 +-
.../Target/AArch64/AArch64SchedNeoverseN2.td | 2 +-
.../Target/AArch64/AArch64SchedNeoverseN3.td | 2 +-
.../Target/AArch64/AArch64SchedNeoverseV1.td | 2 +-
.../Target/AArch64/AArch64SchedNeoverseV2.td | 2 +-
.../Target/AArch64/AArch64SchedNeoverseV3.td | 2 +-
.../AArch64/AArch64SchedNeoverseV3AE.td | 2 +-
llvm/lib/Target/AArch64/SVEInstrFormats.td | 62 +++++++++----------
9 files changed, 38 insertions(+), 40 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64SchedA320.td b/llvm/lib/Target/AArch64/AArch64SchedA320.td
index 2c193e59cc417..49f5c544c8f8a 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedA320.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedA320.td
@@ -639,7 +639,7 @@ def : InstRW<[CortexA320Write<2, CortexA320UnitVALU>], (instregex "^PTRUES_[BHSD
def : InstRW<[CortexA320Write<2, CortexA320UnitVALU>], (instregex "^PFIRST_B", "^PNEXT_[BHSD]")>;
// Predicate test
-def : InstRW<[CortexA320Write<2, CortexA320UnitVALU>], (instrs PTEST_PP)>;
+def : InstRW<[CortexA320Write<2, CortexA320UnitVALU>], (instrs PTEST_PP, PTEST_PP_ANY, PTEST_PP_FIRST)>;
// Predicate transpose
def : InstRW<[CortexA320Write<2, CortexA320UnitVALU>], (instregex "^TRN[12]_PPP_[BHSDQ]")>;
diff --git a/llvm/lib/Target/AArch64/AArch64SchedA510.td b/llvm/lib/Target/AArch64/AArch64SchedA510.td
index 66f49f040ad12..19585f030a608 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedA510.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedA510.td
@@ -617,7 +617,7 @@ def : InstRW<[CortexA510Write<2, CortexA510UnitVALU0>], (instregex "^PTRUES_[BHS
def : InstRW<[CortexA510Write<2, CortexA510UnitVALU0>], (instregex "^PFIRST_B", "^PNEXT_[BHSD]")>;
// Predicate test
-def : InstRW<[CortexA510Write<2, CortexA510UnitVALU0>], (instrs PTEST_PP)>;
+def : InstRW<[CortexA510Write<2, CortexA510UnitVALU0>], (instrs PTEST_PP, PTEST_PP_ANY, PTEST_PP_FIRST)>;
// Predicate transpose
def : InstRW<[CortexA510Write<2, CortexA510UnitVALU0>], (instregex "^TRN[12]_PPP_[BHSDQ]")>;
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
index a02130f8390a7..f275b0d2b39dc 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
@@ -1625,7 +1625,7 @@ def : InstRW<[N2Write_3c_1M], (instregex "^PTRUES_[BHSD]$")>;
def : InstRW<[N2Write_3c_1M], (instregex "^PFIRST_B$", "^PNEXT_[BHSD]$")>;
// Predicate test
-def : InstRW<[N2Write_1c_1M], (instrs PTEST_PP)>;
+def : InstRW<[N2Write_1c_1M], (instrs PTEST_PP, PTEST_PP_ANY, PTEST_PP_FIRST)>;
// Predicate transpose
def : InstRW<[N2Write_2c_1M], (instregex "^TRN[12]_PPP_[BHSDQ]$")>;
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN3.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN3.td
index 22e6d1107a337..33ddae252c36c 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN3.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN3.td
@@ -1715,7 +1715,7 @@ def : InstRW<[N3Write_0or2c_1M], (instregex "^PTRUES_[BHSD]")>;
def : InstRW<[N3Write_2c_1M], (instregex "^PFIRST_B$", "^PNEXT_[BHSD]$")>;
// Predicate test
-def : InstRW<[N3Write_1c_1M], (instrs PTEST_PP)>;
+def : InstRW<[N3Write_1c_1M], (instrs PTEST_PP, PTEST_PP_ANY, PTEST_PP_FIRST)>;
// Predicate transpose
def : InstRW<[N3Write_2c_1M], (instregex "^TRN[12]_PPP_[BHSDQ]$")>;
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
index ac5e8897017c2..a279e28cf8da5 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
@@ -1481,7 +1481,7 @@ def : InstRW<[V1Write_2c_1M0], (instregex "^REV_PP_[BHSD]$",
// Predicate set/initialize/find next
// Predicate unpack and widen
-def : InstRW<[V1Write_2c_1M0], (instrs PTEST_PP,
+def : InstRW<[V1Write_2c_1M0], (instrs PTEST_PP, PTEST_PP_ANY, PTEST_PP_FIRST,
PUNPKHI_PP, PUNPKLO_PP)>;
// Predicate select
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
index 2387f176f3051..373a5dc22e187 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
@@ -2088,7 +2088,7 @@ def : InstRW<[V2Write_3c_2M], (instregex "^PTRUES_[BHSD]")>;
def : InstRW<[V2Write_2c_1M], (instregex "^PFIRST_B", "^PNEXT_[BHSD]")>;
// Predicate test
-def : InstRW<[V2Write_1c_1M], (instrs PTEST_PP)>;
+def : InstRW<[V2Write_1c_1M], (instrs PTEST_PP, PTEST_PP_ANY, PTEST_PP_FIRST)>;
// Predicate transpose
def : InstRW<[V2Write_2c_1M], (instregex "^TRN[12]_PPP_[BHSD]")>;
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV3.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV3.td
index e23576a20d277..67c77dcc223b1 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV3.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV3.td
@@ -2017,7 +2017,7 @@ def : InstRW<[V3Write_2c_1M], (instregex "^PTRUES_[BHSD]")>;
def : InstRW<[V3Write_2c_1M], (instregex "^PFIRST_B", "^PNEXT_[BHSD]")>;
// Predicate test
-def : InstRW<[V3Write_1c_1M], (instrs PTEST_PP)>;
+def : InstRW<[V3Write_1c_1M], (instrs PTEST_PP, PTEST_PP_ANY, PTEST_PP_FIRST)>;
// Predicate transpose
def : InstRW<[V3Write_2c_1M], (instregex "^TRN[12]_PPP_[BHSD]")>;
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV3AE.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV3AE.td
index 0f1ec669a4e5e..20e733feb32f0 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV3AE.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV3AE.td
@@ -1945,7 +1945,7 @@ def : InstRW<[V3AEWrite_2c_1M], (instregex "^PTRUES_[BHSD]")>;
def : InstRW<[V3AEWrite_2c_1M], (instregex "^PFIRST_B", "^PNEXT_[BHSD]")>;
// Predicate test
-def : InstRW<[V3AEWrite_1c_1M], (instrs PTEST_PP)>;
+def : InstRW<[V3AEWrite_1c_1M], (instrs PTEST_PP, PTEST_PP_ANY, PTEST_PP_FIRST)>;
// Predicate transpose
def : InstRW<[V3AEWrite_2c_1M], (instregex "^TRN[12]_PPP_[BHSD]")>;
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index 1f031f91f70e7..7a0d3711a2bce 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -800,45 +800,43 @@ class SVEInstr2Rev<string name1, string name2, bit name1IsReverseInstr> {
//
// Pseudos for destructive operands
//
-let hasNoSchedulingInfo = 1 in {
- class PredTwoOpPseudo<string name, ZPRRegOp zprty,
- FalseLanesEnum flags = FalseLanesNone>
- : SVEPseudo2Instr<name, 0>,
- Pseudo<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zs1, zprty:$Zs2), []> {
- let FalseLanes = flags;
- }
- class PredTwoOpImmPseudo<string name, ZPRRegOp zprty, Operand immty,
- FalseLanesEnum flags = FalseLanesNone>
- : SVEPseudo2Instr<name, 0>,
- Pseudo<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zs1, immty:$imm), []> {
- let FalseLanes = flags;
- }
+class PredTwoOpPseudo<string name, ZPRRegOp zprty,
+ FalseLanesEnum flags = FalseLanesNone>
+: SVEPseudo2Instr<name, 0>,
+ Pseudo<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zs1, zprty:$Zs2), []> {
+ let FalseLanes = flags;
+}
- class PredThreeOpPseudo<string name, ZPRRegOp zprty,
- FalseLanesEnum flags = FalseLanesNone>
- : SVEPseudo2Instr<name, 0>,
- Pseudo<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zs1, zprty:$Zs2, zprty:$Zs3), []> {
- let FalseLanes = flags;
- }
+class PredTwoOpImmPseudo<string name, ZPRRegOp zprty, Operand immty,
+ FalseLanesEnum flags = FalseLanesNone>
+: SVEPseudo2Instr<name, 0>,
+ Pseudo<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zs1, immty:$imm), []> {
+ let FalseLanes = flags;
+}
- class UnpredRegImmPseudo<ZPRRegOp zprty, Operand immty>
- : SVEPseudo2Instr<NAME, 0>,
- Pseudo<(outs zprty:$Zd), (ins zprty:$Zs, immty:$imm), []> {
- }
+class PredThreeOpPseudo<string name, ZPRRegOp zprty,
+ FalseLanesEnum flags = FalseLanesNone>
+: SVEPseudo2Instr<name, 0>,
+ Pseudo<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zs1, zprty:$Zs2, zprty:$Zs3), []> {
+ let FalseLanes = flags;
+}
+
+class UnpredRegImmPseudo<ZPRRegOp zprty, Operand immty>
+: SVEPseudo2Instr<NAME, 0>,
+ Pseudo<(outs zprty:$Zd), (ins zprty:$Zs, immty:$imm), []> {
}
//
// Pseudos for passthru operands
//
-let hasNoSchedulingInfo = 1 in {
- class PredOneOpPassthruPseudo<string name, ZPRRegOp zprty,
- FalseLanesEnum flags = FalseLanesNone>
- : SVEPseudo2Instr<name, 0>,
- Pseudo<(outs zprty:$Zd), (ins zprty:$Passthru, PPR3bAny:$Pg, zprty:$Zs), []> {
- let FalseLanes = flags;
- let Constraints = !if(!eq(flags, FalseLanesZero), "$Zd = $Passthru, at earlyclobber $Zd", "");
- }
+
+class PredOneOpPassthruPseudo<string name, ZPRRegOp zprty,
+ FalseLanesEnum flags = FalseLanesNone>
+: SVEPseudo2Instr<name, 0>,
+ Pseudo<(outs zprty:$Zd), (ins zprty:$Passthru, PPR3bAny:$Pg, zprty:$Zs), []> {
+ let FalseLanes = flags;
+ let Constraints = !if(!eq(flags, FalseLanesZero), "$Zd = $Passthru, at earlyclobber $Zd", "");
}
//===----------------------------------------------------------------------===//
@@ -901,7 +899,7 @@ multiclass sve_int_ptest<bits<6> opc, string asm, SDPatternOperator op,
SDPatternOperator op_any, SDPatternOperator op_first> {
def NAME : sve_int_ptest<opc, asm, op>;
- let hasNoSchedulingInfo = 1, isCompare = 1, Defs = [NZCV] in {
+ let isCompare = 1, Defs = [NZCV] in {
def _ANY : Pseudo<(outs), (ins PPRAny:$Pg, PPR8:$Pn),
[(set NZCV, (op_any (nxv16i1 PPRAny:$Pg), (nxv16i1 PPR8:$Pn)))]>,
PseudoInstExpansion<(!cast<Instruction>(NAME) PPRAny:$Pg, PPR8:$Pn)>;
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