[llvm] [RISCV] Generate Xqcilsm LWMI/SWMI load/store multiple instructions (PR #171079)

[Craig Topper via llvm-commits]

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@@ -168,14 +174,93 @@ bool RISCVLoadStoreOpt::tryToPairLdStInst(MachineBasicBlock::iterator &MBBI) {
   return false;
 }
 
-// Merge two adjacent load/store instructions into a paired instruction
-// (LDP/SDP/SWP/LWP) if the effective address is 8-byte aligned in case of
-// SWP/LWP 16-byte aligned in case of LDP/SDP. This function selects the
-// appropriate paired opcode, verifies that the memory operand is properly
-// aligned, and checks that the offset is valid. If all conditions are met, it
-// builds and inserts the paired instruction.
-bool RISCVLoadStoreOpt::tryConvertToLdStPair(
-    MachineBasicBlock::iterator First, MachineBasicBlock::iterator Second) {
+bool RISCVLoadStoreOpt::tryConvertToXqcilsmLdStPair(
+    MachineFunction *MF, MachineBasicBlock::iterator First,
+    MachineBasicBlock::iterator Second) {
+  unsigned Opc = First->getOpcode();
+  if ((Opc != RISCV::LW && Opc != RISCV::SW) || Second->getOpcode() != Opc)
+    return false;
+
+  auto FirstOp1 = First->getOperand(1);
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topperc wrote:

I think this is copying the MachineOperands? Can we use references?

https://github.com/llvm/llvm-project/pull/171079