[llvm] [RISCV] Disable splitValueIntoRegisterParts/joinRegisterPartsIntoValue for scalable vectors with same element count. (PR #171243)

[Craig Topper via llvm-commits]

topperc wrote:

I put up #171278 to add fractional LMUL register classes. I think that is the better fix.

https://github.com/llvm/llvm-project/pull/171243