[llvm] [AArch64] Eliminate redundant setcc on vector comparison results (PR #171431)

[Valeriy Savchenko via llvm-commits]

SavchenkoValeriy wrote:

@davemgreen I moved it to SelectionDAG and predicated it on boolean result === -1/0 mask using `computeNumSignBits`. Thanks for the suggestion!

https://github.com/llvm/llvm-project/pull/171431