[llvm] [AArch64]SIMD fpcvt codegen for rounding nodes (PR #165546)

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Lukacma wrote:

> I was thinking of things like store_i32(lrint), but wanted store_f32(bitcast(lrint)) then DAG would happily convert it back into store_i32(lrint) by optimizing the store+bitcast together. GISel has a nicer solution for this kind of problem, and I'm hoping it can be made more so in the future.

Yes that will be issue with SDAG for many cases. I am working on adding lowering for neon intrinsics nodes so at least those should work with new patterns, but unless the work is extended to all nodes, the impact of this work will be limited. 

https://github.com/llvm/llvm-project/pull/165546