[llvm] [AArch64] Eliminate redundant setcc on vector comparison results (PR #171431)

[David Green via llvm-commits]

https://github.com/davemgreen commented:

It sounds like you are trying to reimplement computeKnownBits / computeNumSignBits and perform optimizations based on it. A lot of the test cases already simplify in IR, but maybe not through a shuffle. I didn't look too much into the details, what would we be missing to make this happen through computeNumSignBits instead? Is there a generic DAG combine that could handle it if more AArch64 nodes were producing results?

https://github.com/llvm/llvm-project/pull/171431