[llvm] [AArch64][SVE] Rework VECTOR_COMPRESS lowering (PR #171162)

[Benjamin Maxwell via llvm-commits]

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@@ -263,13 +255,12 @@ define <4 x double> @test_compress_v4f64_with_sve(<4 x double> %vec, <4 x i1> %m
 define <2 x i16> @test_compress_v2i16_with_sve(<2 x i16> %vec, <2 x i1> %mask) {
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MacDue wrote:

This is not working right now as the SVE container for `<4 x i16>` is `nxv8i16` (which is unsupported). IMO, the best way to handle this is with `setOperationPromotedToType(ISD::VECTOR_COMPRESS, MVT::v4i16, MVT::v4i32);`, but vector promotion for `VECTOR_COMPRESS` is not implemented, so I think this should be done in another patch (rather than special-cased in the AArch64 lowering).

https://github.com/llvm/llvm-project/pull/171162