[llvm] 9bfb3be - [AArch64][GlobalISel] Added support for neon left shift intrinsics on single-element vector types (#170827)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 9 03:23:07 PST 2025
Author: Joshua Rodriguez
Date: 2025-12-09T11:23:04Z
New Revision: 9bfb3be8c82cf5cb5c564d628f3ea7e2b31c792f
URL: https://github.com/llvm/llvm-project/commit/9bfb3be8c82cf5cb5c564d628f3ea7e2b31c792f
DIFF: https://github.com/llvm/llvm-project/commit/9bfb3be8c82cf5cb5c564d628f3ea7e2b31c792f.diff
LOG: [AArch64][GlobalISel] Added support for neon left shift intrinsics on single-element vector types (#170827)
Previously, the left shift family of intrinsics would fail to lower for
<1 x i64> / <1 x i32> vector types, as IRTranslation lowers these to
scalars. Marking these intrinsics as only using fp operands ensures the
RegBankSelect phase places the vector on an fpr bank, instead of a gpr
bank.
Added:
Modified:
llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
llvm/test/CodeGen/AArch64/arm64-int-neon.ll
llvm/test/CodeGen/AArch64/arm64-vshift.ll
llvm/test/CodeGen/AArch64/neon-addlv.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
index 6b920f05227ad..4d3d0811b1524 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
@@ -483,6 +483,14 @@ static bool isFPIntrinsic(const MachineRegisterInfo &MRI,
case Intrinsic::aarch64_neon_sqadd:
case Intrinsic::aarch64_neon_sqsub:
case Intrinsic::aarch64_crypto_sha1h:
+ case Intrinsic::aarch64_neon_srshl:
+ case Intrinsic::aarch64_neon_urshl:
+ case Intrinsic::aarch64_neon_sqshl:
+ case Intrinsic::aarch64_neon_uqshl:
+ case Intrinsic::aarch64_neon_sqrshl:
+ case Intrinsic::aarch64_neon_uqrshl:
+ case Intrinsic::aarch64_neon_ushl:
+ case Intrinsic::aarch64_neon_sshl:
case Intrinsic::aarch64_crypto_sha1c:
case Intrinsic::aarch64_crypto_sha1p:
case Intrinsic::aarch64_crypto_sha1m:
diff --git a/llvm/test/CodeGen/AArch64/arm64-int-neon.ll b/llvm/test/CodeGen/AArch64/arm64-int-neon.ll
index f33d41b0dd6ef..e8ae8a3e53c9b 100644
--- a/llvm/test/CodeGen/AArch64/arm64-int-neon.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-int-neon.ll
@@ -3,15 +3,7 @@
; RUN: llc < %s -mtriple aarch64-unknown-unknown -global-isel -global-isel-abort=2 -mattr=+fprcvt,+fullfp16 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-; CHECK-GI: warning: Instruction selection used fallback path for test_sqrshl_s32
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_sqrshl_s64
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_sqshl_s32
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_sqshl_s64
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_uqrshl_s32
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_uqrshl_s64
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_uqshl_s32
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_uqshl_s64
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_uqadd_s32
+; CHECK-GI: warning: Instruction selection used fallback path for test_uqadd_s32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_uqadd_s64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_uqsub_s32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_uqsub_s64
diff --git a/llvm/test/CodeGen/AArch64/arm64-vshift.ll b/llvm/test/CodeGen/AArch64/arm64-vshift.ll
index d27e2e69f8605..9743639d99d9b 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vshift.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vshift.ll
@@ -2,105 +2,68 @@
; RUN: llc < %s -mtriple=arm64-eabi -global-isel=0 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple=arm64-eabi -global-isel=1 -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-; CHECK-GI: warning: Instruction selection used fallback path for sqshl1d
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshl1d_constant
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshl_scalar
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshl_scalar_constant
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqshl1d
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqshl1d_constant
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqshl_scalar
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqshl_scalar_constant
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for srshl1d
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for srshl1d_constant
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for srshl_scalar
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for srshl_scalar_constant
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for urshl1d
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for urshl1d_constant
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for urshl_scalar
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for urshl_scalar_constant
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqrshl1d
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqrshl1d_constant
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqrshl_scalar
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqrshl_scalar_constant
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqrshl1d
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqrshl1d_constant
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqrshl_scalar
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqrshl_scalar_constant
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for urshr1d
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for urshr_scalar
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for srshr1d
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for srshr_scalar
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshlu8b
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshlu4h
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshlu2s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshlu16b
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshlu8h
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshlu4s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshlu2d
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshlu1d_constant
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshlu_i64_constant
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshlu_i32_constant
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshrn1s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshrn8b
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshrn4h
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshrn2s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshrn16b
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshrn8h
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshrn4s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshrun1s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshrun8b
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshrun4h
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshrun2s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshrun16b
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshrun8h
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshrun4s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqrshrn1s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqrshrn8b
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqrshrn4h
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqrshrn2s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqrshrn16b
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqrshrn8h
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqrshrn4s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqrshrun1s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqrshrun8b
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqrshrun4h
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqrshrun2s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqrshrun16b
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqrshrun8h
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqrshrun4s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqrshrn1s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqrshrn8b
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqrshrn4h
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqrshrn2s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqrshrn16b
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqrshrn8h
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqrshrn4s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqshrn1s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqshrn8b
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqshrn4h
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqshrn2s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqshrn16b
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqshrn8h
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uqshrn4s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for neon_ushl_vscalar_constant_shift
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for neon_ushl_scalar_constant_shift
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for neon_sshll_vscalar_constant_shift
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for neon_sshll_scalar_constant_shift
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for neon_sshll_scalar_constant_shift_m1
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for ursra1d
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for ursra_scalar
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for srsra1d
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for srsra_scalar
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sli8b
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sli4h
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sli2s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sli1d
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sli1d_imm0
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sli16b
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sli8h
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sli4s
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sli2d
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sqshlu_zero_shift_amount
+; CHECK-GI: warning: Instruction selection used fallback path for sqshlu8b
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshlu4h
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshlu2s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshlu16b
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshlu8h
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshlu4s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshlu2d
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshlu1d_constant
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshlu_i64_constant
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshlu_i32_constant
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshrn1s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshrn8b
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshrn4h
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshrn2s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshrn16b
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshrn8h
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshrn4s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshrun1s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshrun8b
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshrun4h
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshrun2s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshrun16b
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshrun8h
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshrun4s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrn1s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrn8b
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrn4h
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrn2s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrn16b
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrn8h
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrn4s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrun1s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrun8b
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrun4h
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrun2s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrun16b
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrun8h
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqrshrun4s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqrshrn1s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqrshrn8b
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqrshrn4h
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqrshrn2s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqrshrn16b
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqrshrn8h
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqrshrn4s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqshrn1s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqshrn8b
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqshrn4h
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqshrn2s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqshrn16b
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqshrn8h
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for uqshrn4s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sli8b
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sli4h
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sli2s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sli1d
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sli1d_imm0
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sli16b
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sli8h
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sli4s
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sli2d
+; CHECK-GI NEXT: warning: Instruction selection used fallback path for sqshlu_zero_shift_amount
define <8 x i8> @sqshl8b(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: sqshl8b:
@@ -155,11 +118,19 @@ define <1 x i64> @sqshl1d(ptr %A, ptr %B) nounwind {
}
define <1 x i64> @sqshl1d_constant(ptr %A) nounwind {
-; CHECK-LABEL: sqshl1d_constant:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: sqshl d0, d0, #1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: sqshl1d_constant:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d0, [x0]
+; CHECK-SD-NEXT: sqshl d0, d0, #1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sqshl1d_constant:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #1 // =0x1
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: sqshl d0, d0, d1
+; CHECK-GI-NEXT: ret
%tmp1 = load <1 x i64>, ptr %A
%tmp3 = call <1 x i64> @llvm.aarch64.neon.sqshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 1>)
ret <1 x i64> %tmp3
@@ -180,12 +151,21 @@ define i64 @sqshl_scalar(ptr %A, ptr %B) nounwind {
}
define i64 @sqshl_scalar_constant(ptr %A) nounwind {
-; CHECK-LABEL: sqshl_scalar_constant:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: sqshl d0, d0, #1
-; CHECK-NEXT: fmov x0, d0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: sqshl_scalar_constant:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d0, [x0]
+; CHECK-SD-NEXT: sqshl d0, d0, #1
+; CHECK-SD-NEXT: fmov x0, d0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sqshl_scalar_constant:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #1 // =0x1
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: sqshl d0, d0, d1
+; CHECK-GI-NEXT: fmov x0, d0
+; CHECK-GI-NEXT: ret
%tmp1 = load i64, ptr %A
%tmp3 = call i64 @llvm.aarch64.neon.sqshl.i64(i64 %tmp1, i64 1)
ret i64 %tmp3
@@ -348,11 +328,19 @@ define <1 x i64> @uqshl1d(ptr %A, ptr %B) nounwind {
}
define <1 x i64> @uqshl1d_constant(ptr %A) nounwind {
-; CHECK-LABEL: uqshl1d_constant:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: uqshl d0, d0, #1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: uqshl1d_constant:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d0, [x0]
+; CHECK-SD-NEXT: uqshl d0, d0, #1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: uqshl1d_constant:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #1 // =0x1
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: uqshl d0, d0, d1
+; CHECK-GI-NEXT: ret
%tmp1 = load <1 x i64>, ptr %A
%tmp3 = call <1 x i64> @llvm.aarch64.neon.uqshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 1>)
ret <1 x i64> %tmp3
@@ -373,12 +361,21 @@ define i64 @uqshl_scalar(ptr %A, ptr %B) nounwind {
}
define i64 @uqshl_scalar_constant(ptr %A) nounwind {
-; CHECK-LABEL: uqshl_scalar_constant:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: uqshl d0, d0, #1
-; CHECK-NEXT: fmov x0, d0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: uqshl_scalar_constant:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d0, [x0]
+; CHECK-SD-NEXT: uqshl d0, d0, #1
+; CHECK-SD-NEXT: fmov x0, d0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: uqshl_scalar_constant:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #1 // =0x1
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: uqshl d0, d0, d1
+; CHECK-GI-NEXT: fmov x0, d0
+; CHECK-GI-NEXT: ret
%tmp1 = load i64, ptr %A
%tmp3 = call i64 @llvm.aarch64.neon.uqshl.i64(i64 %tmp1, i64 1)
ret i64 %tmp3
@@ -473,15 +470,23 @@ define <1 x i64> @srshl1d_constant(ptr %A) nounwind {
}
define i64 @srshl_scalar(ptr %A, ptr %B) nounwind {
-; CHECK-LABEL: srshl_scalar:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr x8, [x0]
-; CHECK-NEXT: ldr x9, [x1]
-; CHECK-NEXT: fmov d0, x8
-; CHECK-NEXT: fmov d1, x9
-; CHECK-NEXT: srshl d0, d0, d1
-; CHECK-NEXT: fmov x0, d0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: srshl_scalar:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr x8, [x0]
+; CHECK-SD-NEXT: ldr x9, [x1]
+; CHECK-SD-NEXT: fmov d0, x8
+; CHECK-SD-NEXT: fmov d1, x9
+; CHECK-SD-NEXT: srshl d0, d0, d1
+; CHECK-SD-NEXT: fmov x0, d0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: srshl_scalar:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: ldr d1, [x1]
+; CHECK-GI-NEXT: srshl d0, d0, d1
+; CHECK-GI-NEXT: fmov x0, d0
+; CHECK-GI-NEXT: ret
%tmp1 = load i64, ptr %A
%tmp2 = load i64, ptr %B
%tmp3 = call i64 @llvm.aarch64.neon.srshl.i64(i64 %tmp1, i64 %tmp2)
@@ -489,15 +494,24 @@ define i64 @srshl_scalar(ptr %A, ptr %B) nounwind {
}
define i64 @srshl_scalar_constant(ptr %A) nounwind {
-; CHECK-LABEL: srshl_scalar_constant:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr x9, [x0]
-; CHECK-NEXT: mov w8, #1 // =0x1
-; CHECK-NEXT: fmov d1, x8
-; CHECK-NEXT: fmov d0, x9
-; CHECK-NEXT: srshl d0, d0, d1
-; CHECK-NEXT: fmov x0, d0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: srshl_scalar_constant:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr x9, [x0]
+; CHECK-SD-NEXT: mov w8, #1 // =0x1
+; CHECK-SD-NEXT: fmov d1, x8
+; CHECK-SD-NEXT: fmov d0, x9
+; CHECK-SD-NEXT: srshl d0, d0, d1
+; CHECK-SD-NEXT: fmov x0, d0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: srshl_scalar_constant:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #1 // =0x1
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: srshl d0, d0, d1
+; CHECK-GI-NEXT: fmov x0, d0
+; CHECK-GI-NEXT: ret
%tmp1 = load i64, ptr %A
%tmp3 = call i64 @llvm.aarch64.neon.srshl.i64(i64 %tmp1, i64 1)
ret i64 %tmp3
@@ -569,15 +583,23 @@ define <1 x i64> @urshl1d_constant(ptr %A) nounwind {
}
define i64 @urshl_scalar(ptr %A, ptr %B) nounwind {
-; CHECK-LABEL: urshl_scalar:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr x8, [x0]
-; CHECK-NEXT: ldr x9, [x1]
-; CHECK-NEXT: fmov d0, x8
-; CHECK-NEXT: fmov d1, x9
-; CHECK-NEXT: urshl d0, d0, d1
-; CHECK-NEXT: fmov x0, d0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: urshl_scalar:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr x8, [x0]
+; CHECK-SD-NEXT: ldr x9, [x1]
+; CHECK-SD-NEXT: fmov d0, x8
+; CHECK-SD-NEXT: fmov d1, x9
+; CHECK-SD-NEXT: urshl d0, d0, d1
+; CHECK-SD-NEXT: fmov x0, d0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: urshl_scalar:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: ldr d1, [x1]
+; CHECK-GI-NEXT: urshl d0, d0, d1
+; CHECK-GI-NEXT: fmov x0, d0
+; CHECK-GI-NEXT: ret
%tmp1 = load i64, ptr %A
%tmp2 = load i64, ptr %B
%tmp3 = call i64 @llvm.aarch64.neon.urshl.i64(i64 %tmp1, i64 %tmp2)
@@ -585,15 +607,24 @@ define i64 @urshl_scalar(ptr %A, ptr %B) nounwind {
}
define i64 @urshl_scalar_constant(ptr %A) nounwind {
-; CHECK-LABEL: urshl_scalar_constant:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr x9, [x0]
-; CHECK-NEXT: mov w8, #1 // =0x1
-; CHECK-NEXT: fmov d1, x8
-; CHECK-NEXT: fmov d0, x9
-; CHECK-NEXT: urshl d0, d0, d1
-; CHECK-NEXT: fmov x0, d0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: urshl_scalar_constant:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr x9, [x0]
+; CHECK-SD-NEXT: mov w8, #1 // =0x1
+; CHECK-SD-NEXT: fmov d1, x8
+; CHECK-SD-NEXT: fmov d0, x9
+; CHECK-SD-NEXT: urshl d0, d0, d1
+; CHECK-SD-NEXT: fmov x0, d0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: urshl_scalar_constant:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #1 // =0x1
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: urshl d0, d0, d1
+; CHECK-GI-NEXT: fmov x0, d0
+; CHECK-GI-NEXT: ret
%tmp1 = load i64, ptr %A
%tmp3 = call i64 @llvm.aarch64.neon.urshl.i64(i64 %tmp1, i64 1)
ret i64 %tmp3
@@ -896,14 +927,23 @@ define i64 @sqrshl_scalar(ptr %A, ptr %B) nounwind {
}
define i64 @sqrshl_scalar_constant(ptr %A) nounwind {
-; CHECK-LABEL: sqrshl_scalar_constant:
-; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #1 // =0x1
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: fmov d1, x8
-; CHECK-NEXT: sqrshl d0, d0, d1
-; CHECK-NEXT: fmov x0, d0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: sqrshl_scalar_constant:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov x8, #1 // =0x1
+; CHECK-SD-NEXT: ldr d0, [x0]
+; CHECK-SD-NEXT: fmov d1, x8
+; CHECK-SD-NEXT: sqrshl d0, d0, d1
+; CHECK-SD-NEXT: fmov x0, d0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sqrshl_scalar_constant:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #1 // =0x1
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: sqrshl d0, d0, d1
+; CHECK-GI-NEXT: fmov x0, d0
+; CHECK-GI-NEXT: ret
%tmp1 = load i64, ptr %A
%tmp3 = call i64 @llvm.aarch64.neon.sqrshl.i64(i64 %tmp1, i64 1)
ret i64 %tmp3
@@ -1002,14 +1042,23 @@ define i64 @uqrshl_scalar(ptr %A, ptr %B) nounwind {
}
define i64 @uqrshl_scalar_constant(ptr %A) nounwind {
-; CHECK-LABEL: uqrshl_scalar_constant:
-; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #1 // =0x1
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: fmov d1, x8
-; CHECK-NEXT: uqrshl d0, d0, d1
-; CHECK-NEXT: fmov x0, d0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: uqrshl_scalar_constant:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov x8, #1 // =0x1
+; CHECK-SD-NEXT: ldr d0, [x0]
+; CHECK-SD-NEXT: fmov d1, x8
+; CHECK-SD-NEXT: uqrshl d0, d0, d1
+; CHECK-SD-NEXT: fmov x0, d0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: uqrshl_scalar_constant:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #1 // =0x1
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: uqrshl d0, d0, d1
+; CHECK-GI-NEXT: fmov x0, d0
+; CHECK-GI-NEXT: ret
%tmp1 = load i64, ptr %A
%tmp3 = call i64 @llvm.aarch64.neon.uqrshl.i64(i64 %tmp1, i64 1)
ret i64 %tmp3
@@ -1164,23 +1213,40 @@ define <2 x i64> @urshr2d(ptr %A) nounwind {
}
define <1 x i64> @urshr1d(ptr %A) nounwind {
-; CHECK-LABEL: urshr1d:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: urshr d0, d0, #1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: urshr1d:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d0, [x0]
+; CHECK-SD-NEXT: urshr d0, d0, #1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: urshr1d:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov x8, #-1 // =0xffffffffffffffff
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: urshl d0, d0, d1
+; CHECK-GI-NEXT: ret
%tmp1 = load <1 x i64>, ptr %A
%tmp3 = call <1 x i64> @llvm.aarch64.neon.urshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 -1>)
ret <1 x i64> %tmp3
}
define i64 @urshr_scalar(ptr %A) nounwind {
-; CHECK-LABEL: urshr_scalar:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: urshr d0, d0, #1
-; CHECK-NEXT: fmov x0, d0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: urshr_scalar:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d0, [x0]
+; CHECK-SD-NEXT: urshr d0, d0, #1
+; CHECK-SD-NEXT: fmov x0, d0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: urshr_scalar:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov x8, #-1 // =0xffffffffffffffff
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: urshl d0, d0, d1
+; CHECK-GI-NEXT: fmov x0, d0
+; CHECK-GI-NEXT: ret
%tmp1 = load i64, ptr %A
%tmp3 = call i64 @llvm.aarch64.neon.urshl.i64(i64 %tmp1, i64 -1)
ret i64 %tmp3
@@ -1313,23 +1379,40 @@ define <2 x i64> @srshr2d(ptr %A) nounwind {
}
define <1 x i64> @srshr1d(ptr %A) nounwind {
-; CHECK-LABEL: srshr1d:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: srshr d0, d0, #1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: srshr1d:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d0, [x0]
+; CHECK-SD-NEXT: srshr d0, d0, #1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: srshr1d:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov x8, #-1 // =0xffffffffffffffff
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: srshl d0, d0, d1
+; CHECK-GI-NEXT: ret
%tmp1 = load <1 x i64>, ptr %A
%tmp3 = call <1 x i64> @llvm.aarch64.neon.srshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 -1>)
ret <1 x i64> %tmp3
}
define i64 @srshr_scalar(ptr %A) nounwind {
-; CHECK-LABEL: srshr_scalar:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: srshr d0, d0, #1
-; CHECK-NEXT: fmov x0, d0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: srshr_scalar:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d0, [x0]
+; CHECK-SD-NEXT: srshr d0, d0, #1
+; CHECK-SD-NEXT: fmov x0, d0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: srshr_scalar:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov x8, #-1 // =0xffffffffffffffff
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: srshl d0, d0, d1
+; CHECK-GI-NEXT: fmov x0, d0
+; CHECK-GI-NEXT: ret
%tmp1 = load i64, ptr %A
%tmp3 = call i64 @llvm.aarch64.neon.srshl.i64(i64 %tmp1, i64 -1)
ret i64 %tmp3
@@ -2447,13 +2530,22 @@ define <2 x i64> @neon_ushll2d_constant_shift(ptr %A) nounwind {
}
define <1 x i64> @neon_ushl_vscalar_constant_shift(ptr %A) nounwind {
-; CHECK-LABEL: neon_ushl_vscalar_constant_shift:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi v0.2d, #0000000000000000
-; CHECK-NEXT: ldr s1, [x0]
-; CHECK-NEXT: zip1 v0.2s, v1.2s, v0.2s
-; CHECK-NEXT: shl d0, d0, #1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: neon_ushl_vscalar_constant_shift:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi v0.2d, #0000000000000000
+; CHECK-SD-NEXT: ldr s1, [x0]
+; CHECK-SD-NEXT: zip1 v0.2s, v1.2s, v0.2s
+; CHECK-SD-NEXT: shl d0, d0, #1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: neon_ushl_vscalar_constant_shift:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr w9, [x0]
+; CHECK-GI-NEXT: mov w8, #1 // =0x1
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: fmov d0, x9
+; CHECK-GI-NEXT: ushl d0, d0, d1
+; CHECK-GI-NEXT: ret
%tmp1 = load <1 x i32>, ptr %A
%tmp2 = zext <1 x i32> %tmp1 to <1 x i64>
%tmp3 = call <1 x i64> @llvm.aarch64.neon.ushl.v1i64(<1 x i64> %tmp2, <1 x i64> <i64 1>)
@@ -2461,13 +2553,23 @@ define <1 x i64> @neon_ushl_vscalar_constant_shift(ptr %A) nounwind {
}
define i64 @neon_ushl_scalar_constant_shift(ptr %A) nounwind {
-; CHECK-LABEL: neon_ushl_scalar_constant_shift:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr w8, [x0]
-; CHECK-NEXT: fmov d0, x8
-; CHECK-NEXT: shl d0, d0, #1
-; CHECK-NEXT: fmov x0, d0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: neon_ushl_scalar_constant_shift:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr w8, [x0]
+; CHECK-SD-NEXT: fmov d0, x8
+; CHECK-SD-NEXT: shl d0, d0, #1
+; CHECK-SD-NEXT: fmov x0, d0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: neon_ushl_scalar_constant_shift:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr w9, [x0]
+; CHECK-GI-NEXT: mov w8, #1 // =0x1
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: fmov d0, x9
+; CHECK-GI-NEXT: ushl d0, d0, d1
+; CHECK-GI-NEXT: fmov x0, d0
+; CHECK-GI-NEXT: ret
%tmp1 = load i32, ptr %A
%tmp2 = zext i32 %tmp1 to i64
%tmp3 = call i64 @llvm.aarch64.neon.ushl.i64(i64 %tmp2, i64 1)
@@ -2721,13 +2823,22 @@ define <2 x i64> @neon_sshll2d_constant_shift(ptr %A) nounwind {
}
define <1 x i64> @neon_sshll_vscalar_constant_shift(ptr %A) nounwind {
-; CHECK-LABEL: neon_sshll_vscalar_constant_shift:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi v0.2d, #0000000000000000
-; CHECK-NEXT: ldr s1, [x0]
-; CHECK-NEXT: zip1 v0.2s, v1.2s, v0.2s
-; CHECK-NEXT: shl d0, d0, #1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: neon_sshll_vscalar_constant_shift:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi v0.2d, #0000000000000000
+; CHECK-SD-NEXT: ldr s1, [x0]
+; CHECK-SD-NEXT: zip1 v0.2s, v1.2s, v0.2s
+; CHECK-SD-NEXT: shl d0, d0, #1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: neon_sshll_vscalar_constant_shift:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr w9, [x0]
+; CHECK-GI-NEXT: mov w8, #1 // =0x1
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: fmov d0, x9
+; CHECK-GI-NEXT: sshl d0, d0, d1
+; CHECK-GI-NEXT: ret
%tmp1 = load <1 x i32>, ptr %A
%tmp2 = zext <1 x i32> %tmp1 to <1 x i64>
%tmp3 = call <1 x i64> @llvm.aarch64.neon.sshl.v1i64(<1 x i64> %tmp2, <1 x i64> <i64 1>)
@@ -2735,13 +2846,23 @@ define <1 x i64> @neon_sshll_vscalar_constant_shift(ptr %A) nounwind {
}
define i64 @neon_sshll_scalar_constant_shift(ptr %A) nounwind {
-; CHECK-LABEL: neon_sshll_scalar_constant_shift:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr w8, [x0]
-; CHECK-NEXT: fmov d0, x8
-; CHECK-NEXT: shl d0, d0, #1
-; CHECK-NEXT: fmov x0, d0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: neon_sshll_scalar_constant_shift:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr w8, [x0]
+; CHECK-SD-NEXT: fmov d0, x8
+; CHECK-SD-NEXT: shl d0, d0, #1
+; CHECK-SD-NEXT: fmov x0, d0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: neon_sshll_scalar_constant_shift:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr w9, [x0]
+; CHECK-GI-NEXT: mov w8, #1 // =0x1
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: fmov d0, x9
+; CHECK-GI-NEXT: sshl d0, d0, d1
+; CHECK-GI-NEXT: fmov x0, d0
+; CHECK-GI-NEXT: ret
%tmp1 = load i32, ptr %A
%tmp2 = zext i32 %tmp1 to i64
%tmp3 = call i64 @llvm.aarch64.neon.sshl.i64(i64 %tmp2, i64 1)
@@ -2749,13 +2870,23 @@ define i64 @neon_sshll_scalar_constant_shift(ptr %A) nounwind {
}
define i64 @neon_sshll_scalar_constant_shift_m1(ptr %A) nounwind {
-; CHECK-LABEL: neon_sshll_scalar_constant_shift_m1:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr w8, [x0]
-; CHECK-NEXT: fmov d0, x8
-; CHECK-NEXT: sshr d0, d0, #1
-; CHECK-NEXT: fmov x0, d0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: neon_sshll_scalar_constant_shift_m1:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr w8, [x0]
+; CHECK-SD-NEXT: fmov d0, x8
+; CHECK-SD-NEXT: sshr d0, d0, #1
+; CHECK-SD-NEXT: fmov x0, d0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: neon_sshll_scalar_constant_shift_m1:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr w9, [x0]
+; CHECK-GI-NEXT: mov x8, #-1 // =0xffffffffffffffff
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: fmov d0, x9
+; CHECK-GI-NEXT: sshl d0, d0, d1
+; CHECK-GI-NEXT: fmov x0, d0
+; CHECK-GI-NEXT: ret
%tmp1 = load i32, ptr %A
%tmp2 = zext i32 %tmp1 to i64
%tmp3 = call i64 @llvm.aarch64.neon.sshl.i64(i64 %tmp2, i64 -1)
@@ -3290,12 +3421,24 @@ define <2 x i64> @ursra2d(ptr %A, ptr %B) nounwind {
}
define <1 x i64> @ursra1d(ptr %A, ptr %B) nounwind {
-; CHECK-LABEL: ursra1d:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr d1, [x0]
-; CHECK-NEXT: ldr d0, [x1]
-; CHECK-NEXT: ursra d0, d1, #1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: ursra1d:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d1, [x0]
+; CHECK-SD-NEXT: ldr d0, [x1]
+; CHECK-SD-NEXT: ursra d0, d1, #1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: ursra1d:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov x8, #-1 // =0xffffffffffffffff
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: ldr x8, [x1]
+; CHECK-GI-NEXT: urshl d0, d0, d1
+; CHECK-GI-NEXT: fmov x9, d0
+; CHECK-GI-NEXT: add x8, x9, x8
+; CHECK-GI-NEXT: fmov d0, x8
+; CHECK-GI-NEXT: ret
%tmp1 = load <1 x i64>, ptr %A
%tmp3 = call <1 x i64> @llvm.aarch64.neon.urshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 -1>)
%tmp4 = load <1 x i64>, ptr %B
@@ -3304,13 +3447,24 @@ define <1 x i64> @ursra1d(ptr %A, ptr %B) nounwind {
}
define i64 @ursra_scalar(ptr %A, ptr %B) nounwind {
-; CHECK-LABEL: ursra_scalar:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: ldr d1, [x1]
-; CHECK-NEXT: ursra d1, d0, #1
-; CHECK-NEXT: fmov x0, d1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: ursra_scalar:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d0, [x0]
+; CHECK-SD-NEXT: ldr d1, [x1]
+; CHECK-SD-NEXT: ursra d1, d0, #1
+; CHECK-SD-NEXT: fmov x0, d1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: ursra_scalar:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov x8, #-1 // =0xffffffffffffffff
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: ldr x8, [x1]
+; CHECK-GI-NEXT: urshl d0, d0, d1
+; CHECK-GI-NEXT: fmov x9, d0
+; CHECK-GI-NEXT: add x0, x9, x8
+; CHECK-GI-NEXT: ret
%tmp1 = load i64, ptr %A
%tmp3 = call i64 @llvm.aarch64.neon.urshl.i64(i64 %tmp1, i64 -1)
%tmp4 = load i64, ptr %B
@@ -3480,12 +3634,24 @@ define <2 x i64> @srsra2d(ptr %A, ptr %B) nounwind {
}
define <1 x i64> @srsra1d(ptr %A, ptr %B) nounwind {
-; CHECK-LABEL: srsra1d:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr d1, [x0]
-; CHECK-NEXT: ldr d0, [x1]
-; CHECK-NEXT: srsra d0, d1, #1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: srsra1d:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d1, [x0]
+; CHECK-SD-NEXT: ldr d0, [x1]
+; CHECK-SD-NEXT: srsra d0, d1, #1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: srsra1d:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov x8, #-1 // =0xffffffffffffffff
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: ldr x8, [x1]
+; CHECK-GI-NEXT: srshl d0, d0, d1
+; CHECK-GI-NEXT: fmov x9, d0
+; CHECK-GI-NEXT: add x8, x9, x8
+; CHECK-GI-NEXT: fmov d0, x8
+; CHECK-GI-NEXT: ret
%tmp1 = load <1 x i64>, ptr %A
%tmp3 = call <1 x i64> @llvm.aarch64.neon.srshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 -1>)
%tmp4 = load <1 x i64>, ptr %B
@@ -3494,13 +3660,24 @@ define <1 x i64> @srsra1d(ptr %A, ptr %B) nounwind {
}
define i64 @srsra_scalar(ptr %A, ptr %B) nounwind {
-; CHECK-LABEL: srsra_scalar:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr d0, [x0]
-; CHECK-NEXT: ldr d1, [x1]
-; CHECK-NEXT: srsra d1, d0, #1
-; CHECK-NEXT: fmov x0, d1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: srsra_scalar:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d0, [x0]
+; CHECK-SD-NEXT: ldr d1, [x1]
+; CHECK-SD-NEXT: srsra d1, d0, #1
+; CHECK-SD-NEXT: fmov x0, d1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: srsra_scalar:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov x8, #-1 // =0xffffffffffffffff
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: ldr x8, [x1]
+; CHECK-GI-NEXT: srshl d0, d0, d1
+; CHECK-GI-NEXT: fmov x9, d0
+; CHECK-GI-NEXT: add x0, x9, x8
+; CHECK-GI-NEXT: ret
%tmp1 = load i64, ptr %A
%tmp3 = call i64 @llvm.aarch64.neon.srshl.i64(i64 %tmp1, i64 -1)
%tmp4 = load i64, ptr %B
diff --git a/llvm/test/CodeGen/AArch64/neon-addlv.ll b/llvm/test/CodeGen/AArch64/neon-addlv.ll
index a747ee661adcd..1897570ad2542 100644
--- a/llvm/test/CodeGen/AArch64/neon-addlv.ll
+++ b/llvm/test/CodeGen/AArch64/neon-addlv.ll
@@ -1,8 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple aarch64-none-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
-; RUN: llc -mtriple aarch64-none-linux-gnu -global-isel -global-isel-abort=2 2>&1 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-
-; CHECK-GI: warning: Instruction selection used fallback path for uaddlv_v8i8_urshr
+; RUN: llc -mtriple aarch64-none-linux-gnu -global-isel < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI
declare <4 x i16> @llvm.aarch64.neon.uaddlp.v4i16.v8i8(<8 x i8>) nounwind readnone
declare <8 x i16> @llvm.aarch64.neon.uaddlp.v8i16.v16i8(<16 x i8>) nounwind readnone
@@ -223,12 +221,25 @@ declare <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16>, i32)
declare i64 @llvm.aarch64.neon.urshl.i64(i64, i64)
define <8 x i8> @uaddlv_v8i8_urshr(<8 x i8> %a) {
-; CHECK-LABEL: uaddlv_v8i8_urshr:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: uaddlv h0, v0.8b
-; CHECK-NEXT: urshr d0, d0, #3
-; CHECK-NEXT: dup v0.8b, v0.b[0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: uaddlv_v8i8_urshr:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: uaddlv h0, v0.8b
+; CHECK-SD-NEXT: urshr d0, d0, #3
+; CHECK-SD-NEXT: dup v0.8b, v0.b[0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: uaddlv_v8i8_urshr:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: uaddlv h0, v0.8b
+; CHECK-GI-NEXT: mov x8, #-3 // =0xfffffffffffffffd
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: fmov w9, s0
+; CHECK-GI-NEXT: and w9, w9, #0xffff
+; CHECK-GI-NEXT: fmov d0, x9
+; CHECK-GI-NEXT: urshl d0, d0, d1
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: dup v0.8b, w8
+; CHECK-GI-NEXT: ret
entry:
%vaddlv.i = tail call i32 @llvm.aarch64.neon.uaddlv.i32.v8i8(<8 x i8> %a)
%0 = and i32 %vaddlv.i, 65535
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