[llvm] [AMDGPU] Add register pressure guard on LLVM-IR level to prevent harmful optimizations (PR #171267)

[Jay Foad via llvm-commits]

jayfoad wrote:

> LICM and Sinking can increase vgpr pressure beyond optimal levels, reducing wave occupancy and causing performance degradation. Current LLVM optimizations don't account for AMDGPU's register pressure during IR-level transformations, and it's hard to undo the passes later.

Yeah. This has been a problem forever. Standard LLVM doctrine is that LICM is a canonicalization, not an optimization, and if it causes register pressure problems then it is the backend's job to undo it. But for whatever reasons, the backend has never been able to undo it well enough.

https://github.com/llvm/llvm-project/pull/171267