[llvm] [AArch64][SVE] Rework VECTOR_COMPRESS lowering (PR #171162)

[Gaëtan Bossu via llvm-commits]

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@@ -263,13 +255,12 @@ define <4 x double> @test_compress_v4f64_with_sve(<4 x double> %vec, <4 x i1> %m
 define <2 x i16> @test_compress_v2i16_with_sve(<2 x i16> %vec, <2 x i1> %mask) {
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gbossu wrote:

Could you add a test for `<4 x i16>`? It's a legal NEON type, so I'm guessing we do not promote it to a legal `<4 x i32>` SVE type?

https://github.com/llvm/llvm-project/pull/171162