[llvm] [RISCV] Add fractional LMUL register classes for inline assembly. (PR #171278)

[Pengcheng Wang via llvm-commits]

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@@ -809,10 +816,21 @@ def VRM8 : VReg<VM8VTs, (add V8M8, V16M8, V24M8, V0M8), 8>;
 
 def VRM8NoV0 : VReg<VM8VTs, (sub VRM8, V0M8), 8>;
 
+// Fractional LMUL register classes for inline assembly.
+def VRMF8 : VReg<VMF8VTs, (add VR), 1>;
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wangpc-pp wrote:

I don't know if we should set `GeneratePressureSet` to `false`, though we don't see any diffs caused by changes of register pressure sets.

https://github.com/llvm/llvm-project/pull/171278