[llvm] 93c7ad1 - [LTT] Bias branch weights as "expected" when lowering type tests with conditional (#170752)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 8 21:02:27 PST 2025
Author: Mircea Trofin
Date: 2025-12-08T21:02:23-08:00
New Revision: 93c7ad188042bfade0af38754ab87426a17e059c
URL: https://github.com/llvm/llvm-project/commit/93c7ad188042bfade0af38754ab87426a17e059c
DIFF: https://github.com/llvm/llvm-project/commit/93c7ad188042bfade0af38754ab87426a17e059c.diff
LOG: [LTT] Bias branch weights as "expected" when lowering type tests with conditional (#170752)
We expect the type test to succeed.
Added:
Modified:
llvm/lib/Transforms/IPO/LowerTypeTests.cpp
llvm/test/Transforms/LowerTypeTests/import.ll
llvm/utils/profcheck-xfail.txt
Removed:
################################################################################
diff --git a/llvm/lib/Transforms/IPO/LowerTypeTests.cpp b/llvm/lib/Transforms/IPO/LowerTypeTests.cpp
index f7aeda95e41b3..06deea8ba5848 100644
--- a/llvm/lib/Transforms/IPO/LowerTypeTests.cpp
+++ b/llvm/lib/Transforms/IPO/LowerTypeTests.cpp
@@ -48,12 +48,14 @@
#include "llvm/IR/IntrinsicInst.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/LLVMContext.h"
+#include "llvm/IR/MDBuilder.h"
#include "llvm/IR/Metadata.h"
#include "llvm/IR/Module.h"
#include "llvm/IR/ModuleSummaryIndex.h"
#include "llvm/IR/ModuleSummaryIndexYAML.h"
#include "llvm/IR/Operator.h"
#include "llvm/IR/PassManager.h"
+#include "llvm/IR/ProfDataUtils.h"
#include "llvm/IR/ReplaceConstant.h"
#include "llvm/IR/Type.h"
#include "llvm/IR/Use.h"
@@ -802,7 +804,9 @@ Value *LowerTypeTestsModule::lowerTypeTestCall(Metadata *TypeId, CallInst *CI,
return createBitSetTest(ThenB, TIL, BitOffset);
}
- IRBuilder<> ThenB(SplitBlockAndInsertIfThen(OffsetInRange, CI, false));
+ MDBuilder MDB(M.getContext());
+ IRBuilder<> ThenB(SplitBlockAndInsertIfThen(OffsetInRange, CI, false,
+ MDB.createLikelyBranchWeights()));
// Now that we know that the offset is in range and aligned, load the
// appropriate bit from the bitset.
diff --git a/llvm/test/Transforms/LowerTypeTests/import.ll b/llvm/test/Transforms/LowerTypeTests/import.ll
index e3c2d8a3d3e8c..1583dda58cddc 100644
--- a/llvm/test/Transforms/LowerTypeTests/import.ll
+++ b/llvm/test/Transforms/LowerTypeTests/import.ll
@@ -92,7 +92,7 @@ define i1 @bytearray7(ptr %p) {
; X86-NEXT: [[TMP2:%.*]] = sub i64 ptrtoint (ptr @__typeid_bytearray7_global_addr to i64), [[TMP1]]
; X86-NEXT: [[TMP3:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 ptrtoint (ptr @__typeid_bytearray7_align to i64))
; X86-NEXT: [[TMP4:%.*]] = icmp ule i64 [[TMP3]], ptrtoint (ptr @__typeid_bytearray7_size_m1 to i64)
-; X86-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP10:%.*]]
+; X86-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP10:%.*]], !prof [[PROF6:![0-9]+]]
; X86: 5:
; X86-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr @__typeid_bytearray7_byte_array, i64 [[TMP3]]
; X86-NEXT: [[TMP7:%.*]] = load i8, ptr [[TMP6]], align 1
@@ -109,7 +109,7 @@ define i1 @bytearray7(ptr %p) {
; ARM-NEXT: [[TMP2:%.*]] = sub i64 ptrtoint (ptr @__typeid_bytearray7_global_addr to i64), [[TMP1]]
; ARM-NEXT: [[TMP3:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 3)
; ARM-NEXT: [[TMP4:%.*]] = icmp ule i64 [[TMP3]], 43
-; ARM-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP10:%.*]]
+; ARM-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP10:%.*]], !prof [[PROF0:![0-9]+]]
; ARM: 5:
; ARM-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr @__typeid_bytearray7_byte_array, i64 [[TMP3]]
; ARM-NEXT: [[TMP7:%.*]] = load i8, ptr [[TMP6]], align 1
@@ -131,7 +131,7 @@ define i1 @bytearray32(ptr %p) {
; X86-NEXT: [[TMP2:%.*]] = sub i64 ptrtoint (ptr @__typeid_bytearray32_global_addr to i64), [[TMP1]]
; X86-NEXT: [[TMP3:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 ptrtoint (ptr @__typeid_bytearray32_align to i64))
; X86-NEXT: [[TMP4:%.*]] = icmp ule i64 [[TMP3]], ptrtoint (ptr @__typeid_bytearray32_size_m1 to i64)
-; X86-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP10:%.*]]
+; X86-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP10:%.*]], !prof [[PROF6]]
; X86: 5:
; X86-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr @__typeid_bytearray32_byte_array, i64 [[TMP3]]
; X86-NEXT: [[TMP7:%.*]] = load i8, ptr [[TMP6]], align 1
@@ -148,7 +148,7 @@ define i1 @bytearray32(ptr %p) {
; ARM-NEXT: [[TMP2:%.*]] = sub i64 ptrtoint (ptr @__typeid_bytearray32_global_addr to i64), [[TMP1]]
; ARM-NEXT: [[TMP3:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 4)
; ARM-NEXT: [[TMP4:%.*]] = icmp ule i64 [[TMP3]], 12346
-; ARM-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP10:%.*]]
+; ARM-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP10:%.*]], !prof [[PROF0]]
; ARM: 5:
; ARM-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr @__typeid_bytearray32_byte_array, i64 [[TMP3]]
; ARM-NEXT: [[TMP7:%.*]] = load i8, ptr [[TMP6]], align 1
@@ -170,7 +170,7 @@ define i1 @inline5(ptr %p) {
; X86-NEXT: [[TMP2:%.*]] = sub i64 ptrtoint (ptr @__typeid_inline5_global_addr to i64), [[TMP1]]
; X86-NEXT: [[TMP3:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 ptrtoint (ptr @__typeid_inline5_align to i64))
; X86-NEXT: [[TMP4:%.*]] = icmp ule i64 [[TMP3]], ptrtoint (ptr @__typeid_inline5_size_m1 to i64)
-; X86-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP11:%.*]]
+; X86-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP11:%.*]], !prof [[PROF6]]
; X86: 5:
; X86-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP3]] to i32
; X86-NEXT: [[TMP7:%.*]] = and i32 [[TMP6]], 31
@@ -188,7 +188,7 @@ define i1 @inline5(ptr %p) {
; ARM-NEXT: [[TMP2:%.*]] = sub i64 ptrtoint (ptr @__typeid_inline5_global_addr to i64), [[TMP1]]
; ARM-NEXT: [[TMP3:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 5)
; ARM-NEXT: [[TMP4:%.*]] = icmp ule i64 [[TMP3]], 31
-; ARM-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP11:%.*]]
+; ARM-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP11:%.*]], !prof [[PROF0]]
; ARM: 5:
; ARM-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP3]] to i32
; ARM-NEXT: [[TMP7:%.*]] = and i32 [[TMP6]], 31
@@ -211,7 +211,7 @@ define i1 @inline6(ptr %p) {
; X86-NEXT: [[TMP2:%.*]] = sub i64 ptrtoint (ptr @__typeid_inline6_global_addr to i64), [[TMP1]]
; X86-NEXT: [[TMP3:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 ptrtoint (ptr @__typeid_inline6_align to i64))
; X86-NEXT: [[TMP4:%.*]] = icmp ule i64 [[TMP3]], ptrtoint (ptr @__typeid_inline6_size_m1 to i64)
-; X86-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP10:%.*]]
+; X86-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP10:%.*]], !prof [[PROF6]]
; X86: 5:
; X86-NEXT: [[TMP6:%.*]] = and i64 [[TMP3]], 63
; X86-NEXT: [[TMP7:%.*]] = shl i64 1, [[TMP6]]
@@ -228,7 +228,7 @@ define i1 @inline6(ptr %p) {
; ARM-NEXT: [[TMP2:%.*]] = sub i64 ptrtoint (ptr @__typeid_inline6_global_addr to i64), [[TMP1]]
; ARM-NEXT: [[TMP3:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 6)
; ARM-NEXT: [[TMP4:%.*]] = icmp ule i64 [[TMP3]], 63
-; ARM-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP10:%.*]]
+; ARM-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP10:%.*]], !prof [[PROF0]]
; ARM: 5:
; ARM-NEXT: [[TMP6:%.*]] = and i64 [[TMP3]], 63
; ARM-NEXT: [[TMP7:%.*]] = shl i64 1, [[TMP6]]
@@ -257,13 +257,16 @@ define i1 @single(ptr %p) {
; X86: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
; X86: attributes #[[ATTR1:[0-9]+]] = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
;.
+; ARM: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+; ARM: attributes #[[ATTR1:[0-9]+]] = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
+;.
; X86: [[META0]] = !{i64 0, i64 256}
; X86: [[META1]] = !{i64 0, i64 64}
; X86: [[META2]] = !{i64 -1, i64 -1}
; X86: [[META3]] = !{i64 0, i64 32}
; X86: [[META4]] = !{i64 0, i64 4294967296}
; X86: [[META5]] = !{i64 0, i64 128}
+; X86: [[PROF6]] = !{!"branch_weights", i32 1048575, i32 1}
;.
-; ARM: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
-; ARM: attributes #[[ATTR1:[0-9]+]] = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
+; ARM: [[PROF0]] = !{!"branch_weights", i32 1048575, i32 1}
;.
diff --git a/llvm/utils/profcheck-xfail.txt b/llvm/utils/profcheck-xfail.txt
index bd0c4868ae17f..959d227992580 100644
--- a/llvm/utils/profcheck-xfail.txt
+++ b/llvm/utils/profcheck-xfail.txt
@@ -490,8 +490,6 @@ Transforms/LowerSwitch/do-not-handle-impossible-values.ll
Transforms/LowerSwitch/feature.ll
Transforms/LowerSwitch/fold-popular-case-to-unreachable-default.ll
Transforms/LowerSwitch/pr59316.ll
-Transforms/LowerTypeTests/import.ll
-Transforms/LowerTypeTests/simple.ll
Transforms/MergeFunc/2011-02-08-RemoveEqual.ll
Transforms/MergeFunc/apply_function_attributes.ll
Transforms/MergeFunc/call-and-invoke-with-ranges-attr.ll
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