[llvm] [NFC] Run UTC --check-globals on LowerTypeTests/import.ll (PR #170755)
Mircea Trofin via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 8 10:35:06 PST 2025
https://github.com/mtrofin updated https://github.com/llvm/llvm-project/pull/170755
>From 140bfa7cc41d67fb3991aa533ddc2af2db21d94c Mon Sep 17 00:00:00 2001
From: Mircea Trofin <mtrofin at google.com>
Date: Thu, 4 Dec 2025 13:57:20 -0800
Subject: [PATCH] [NFC] Run UTC --check-globals on LowerTypeTests/import.ll
---
llvm/test/Transforms/LowerTypeTests/import.ll | 290 ++++++++++--------
1 file changed, 154 insertions(+), 136 deletions(-)
diff --git a/llvm/test/Transforms/LowerTypeTests/import.ll b/llvm/test/Transforms/LowerTypeTests/import.ll
index 819ede96f997e..e3c2d8a3d3e8c 100644
--- a/llvm/test/Transforms/LowerTypeTests/import.ll
+++ b/llvm/test/Transforms/LowerTypeTests/import.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals --version 3
; RUN: opt -mtriple=x86_64-unknown-linux -S -passes=lowertypetests -lowertypetests-summary-action=import -lowertypetests-read-summary=%S/Inputs/import.yaml %s | FileCheck --check-prefixes=CHECK,X86 %s
; RUN: opt -mtriple=aarch64-unknown-linux -S -passes=lowertypetests -lowertypetests-summary-action=import -lowertypetests-read-summary=%S/Inputs/import.yaml %s | FileCheck --check-prefixes=CHECK,ARM %s
@@ -6,48 +6,59 @@ target datalayout = "e-p:64:64"
declare i1 @llvm.type.test(ptr %ptr, metadata %bitset) nounwind readnone
-; CHECK-DAG: @__typeid_single_global_addr = external hidden global [0 x i8], code_model "small"
-; CHECK-DAG: @__typeid_inline6_global_addr = external hidden global [0 x i8], code_model "small"
-; X86-DAG: @__typeid_inline6_align = external hidden global [0 x i8], !absolute_symbol !0
-; X86-DAG: @__typeid_inline6_size_m1 = external hidden global [0 x i8], !absolute_symbol !1
-; X86-DAG: @__typeid_inline6_inline_bits = external hidden global [0 x i8], !absolute_symbol !2
-; CHECK-DAG: @__typeid_inline5_global_addr = external hidden global [0 x i8], code_model "small"
-; X86-DAG: @__typeid_inline5_align = external hidden global [0 x i8], !absolute_symbol !0
-; X86-DAG: @__typeid_inline5_size_m1 = external hidden global [0 x i8], !absolute_symbol !3
-; X86-DAG: @__typeid_inline5_inline_bits = external hidden global [0 x i8], !absolute_symbol !4
-; CHECK-DAG: @__typeid_bytearray32_global_addr = external hidden global [0 x i8], code_model "small"
-; X86-DAG: @__typeid_bytearray32_align = external hidden global [0 x i8], !absolute_symbol !0
-; X86-DAG: @__typeid_bytearray32_size_m1 = external hidden global [0 x i8], !absolute_symbol !4
-; CHECK-DAG: @__typeid_bytearray32_byte_array = external hidden global [0 x i8]
-; X86-DAG: @__typeid_bytearray32_bit_mask = external hidden global [0 x i8], !absolute_symbol !0
-; CHECK-DAG: @__typeid_bytearray7_global_addr = external hidden global [0 x i8], code_model "small"
-; X86-DAG: @__typeid_bytearray7_align = external hidden global [0 x i8], !absolute_symbol !0
-; X86-DAG: @__typeid_bytearray7_size_m1 = external hidden global [0 x i8], !absolute_symbol !5
-; CHECK-DAG: @__typeid_bytearray7_byte_array = external hidden global [0 x i8]
-; X86-DAG: @__typeid_bytearray7_bit_mask = external hidden global [0 x i8], !absolute_symbol !0
-; CHECK-DAG: @__typeid_allones32_global_addr = external hidden global [0 x i8], code_model "small"
-; X86-DAG: @__typeid_allones32_align = external hidden global [0 x i8], !absolute_symbol !0
-; X86-DAG: @__typeid_allones32_size_m1 = external hidden global [0 x i8], !absolute_symbol !4
-; CHECK-DAG: @__typeid_allones7_global_addr = external hidden global [0 x i8], code_model "small"
-; X86-DAG: @__typeid_allones7_align = external hidden global [0 x i8], !absolute_symbol !0
-; X86-DAG: @__typeid_allones7_size_m1 = external hidden global [0 x i8], !absolute_symbol !5
-
+;.
+; X86: @__typeid_single_global_addr = external hidden global [0 x i8], code_model "small"
+; X86: @__typeid_inline6_global_addr = external hidden global [0 x i8], code_model "small"
+; X86: @__typeid_inline6_align = external hidden global [0 x i8], !absolute_symbol [[META0:![0-9]+]]
+; X86: @__typeid_inline6_size_m1 = external hidden global [0 x i8], !absolute_symbol [[META1:![0-9]+]]
+; X86: @__typeid_inline6_inline_bits = external hidden global [0 x i8], !absolute_symbol [[META2:![0-9]+]]
+; X86: @__typeid_inline5_global_addr = external hidden global [0 x i8], code_model "small"
+; X86: @__typeid_inline5_align = external hidden global [0 x i8], !absolute_symbol [[META0]]
+; X86: @__typeid_inline5_size_m1 = external hidden global [0 x i8], !absolute_symbol [[META3:![0-9]+]]
+; X86: @__typeid_inline5_inline_bits = external hidden global [0 x i8], !absolute_symbol [[META4:![0-9]+]]
+; X86: @__typeid_bytearray32_global_addr = external hidden global [0 x i8], code_model "small"
+; X86: @__typeid_bytearray32_align = external hidden global [0 x i8], !absolute_symbol [[META0]]
+; X86: @__typeid_bytearray32_size_m1 = external hidden global [0 x i8], !absolute_symbol [[META4]]
+; X86: @__typeid_bytearray32_byte_array = external hidden global [0 x i8]
+; X86: @__typeid_bytearray32_bit_mask = external hidden global [0 x i8], !absolute_symbol [[META0]]
+; X86: @__typeid_bytearray7_global_addr = external hidden global [0 x i8], code_model "small"
+; X86: @__typeid_bytearray7_align = external hidden global [0 x i8], !absolute_symbol [[META0]]
+; X86: @__typeid_bytearray7_size_m1 = external hidden global [0 x i8], !absolute_symbol [[META5:![0-9]+]]
+; X86: @__typeid_bytearray7_byte_array = external hidden global [0 x i8]
+; X86: @__typeid_bytearray7_bit_mask = external hidden global [0 x i8], !absolute_symbol [[META0]]
+; X86: @__typeid_allones32_global_addr = external hidden global [0 x i8], code_model "small"
+; X86: @__typeid_allones32_align = external hidden global [0 x i8], !absolute_symbol [[META0]]
+; X86: @__typeid_allones32_size_m1 = external hidden global [0 x i8], !absolute_symbol [[META4]]
+; X86: @__typeid_allones7_global_addr = external hidden global [0 x i8], code_model "small"
+; X86: @__typeid_allones7_align = external hidden global [0 x i8], !absolute_symbol [[META0]]
+; X86: @__typeid_allones7_size_m1 = external hidden global [0 x i8], !absolute_symbol [[META5]]
+;.
+; ARM: @__typeid_single_global_addr = external hidden global [0 x i8], code_model "small"
+; ARM: @__typeid_inline6_global_addr = external hidden global [0 x i8], code_model "small"
+; ARM: @__typeid_inline5_global_addr = external hidden global [0 x i8], code_model "small"
+; ARM: @__typeid_bytearray32_global_addr = external hidden global [0 x i8], code_model "small"
+; ARM: @__typeid_bytearray32_byte_array = external hidden global [0 x i8]
+; ARM: @__typeid_bytearray7_global_addr = external hidden global [0 x i8], code_model "small"
+; ARM: @__typeid_bytearray7_byte_array = external hidden global [0 x i8]
+; ARM: @__typeid_allones32_global_addr = external hidden global [0 x i8], code_model "small"
+; ARM: @__typeid_allones7_global_addr = external hidden global [0 x i8], code_model "small"
+;.
define i1 @allones7(ptr %p) {
; X86-LABEL: define i1 @allones7(
; X86-SAME: ptr [[P:%.*]]) {
; X86-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
; X86-NEXT: [[TMP2:%.*]] = sub i64 ptrtoint (ptr @__typeid_allones7_global_addr to i64), [[TMP1]]
-; X86-NEXT: [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 ptrtoint (ptr @__typeid_allones7_align to i64))
-; X86-NEXT: [[TMP8:%.*]] = icmp ule i64 [[TMP7]], ptrtoint (ptr @__typeid_allones7_size_m1 to i64)
-; X86-NEXT: ret i1 [[TMP8]]
+; X86-NEXT: [[TMP3:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 ptrtoint (ptr @__typeid_allones7_align to i64))
+; X86-NEXT: [[TMP4:%.*]] = icmp ule i64 [[TMP3]], ptrtoint (ptr @__typeid_allones7_size_m1 to i64)
+; X86-NEXT: ret i1 [[TMP4]]
;
; ARM-LABEL: define i1 @allones7(
; ARM-SAME: ptr [[P:%.*]]) {
; ARM-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
; ARM-NEXT: [[TMP2:%.*]] = sub i64 ptrtoint (ptr @__typeid_allones7_global_addr to i64), [[TMP1]]
-; ARM-NEXT: [[TMP5:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 1)
-; ARM-NEXT: [[TMP6:%.*]] = icmp ule i64 [[TMP5]], 42
-; ARM-NEXT: ret i1 [[TMP6]]
+; ARM-NEXT: [[TMP3:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 1)
+; ARM-NEXT: [[TMP4:%.*]] = icmp ule i64 [[TMP3]], 42
+; ARM-NEXT: ret i1 [[TMP4]]
;
%x = call i1 @llvm.type.test(ptr %p, metadata !"allones7")
ret i1 %x
@@ -58,17 +69,17 @@ define i1 @allones32(ptr %p) {
; X86-SAME: ptr [[P:%.*]]) {
; X86-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
; X86-NEXT: [[TMP2:%.*]] = sub i64 ptrtoint (ptr @__typeid_allones32_global_addr to i64), [[TMP1]]
-; X86-NEXT: [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 ptrtoint (ptr @__typeid_allones32_align to i64))
-; X86-NEXT: [[TMP8:%.*]] = icmp ule i64 [[TMP7]], ptrtoint (ptr @__typeid_allones32_size_m1 to i64)
-; X86-NEXT: ret i1 [[TMP8]]
+; X86-NEXT: [[TMP3:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 ptrtoint (ptr @__typeid_allones32_align to i64))
+; X86-NEXT: [[TMP4:%.*]] = icmp ule i64 [[TMP3]], ptrtoint (ptr @__typeid_allones32_size_m1 to i64)
+; X86-NEXT: ret i1 [[TMP4]]
;
; ARM-LABEL: define i1 @allones32(
; ARM-SAME: ptr [[P:%.*]]) {
; ARM-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
; ARM-NEXT: [[TMP2:%.*]] = sub i64 ptrtoint (ptr @__typeid_allones32_global_addr to i64), [[TMP1]]
-; ARM-NEXT: [[TMP5:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 2)
-; ARM-NEXT: [[TMP6:%.*]] = icmp ule i64 [[TMP5]], 12345
-; ARM-NEXT: ret i1 [[TMP6]]
+; ARM-NEXT: [[TMP3:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 2)
+; ARM-NEXT: [[TMP4:%.*]] = icmp ule i64 [[TMP3]], 12345
+; ARM-NEXT: ret i1 [[TMP4]]
;
%x = call i1 @llvm.type.test(ptr %p, metadata !"allones32")
ret i1 %x
@@ -79,35 +90,35 @@ define i1 @bytearray7(ptr %p) {
; X86-SAME: ptr [[P:%.*]]) {
; X86-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
; X86-NEXT: [[TMP2:%.*]] = sub i64 ptrtoint (ptr @__typeid_bytearray7_global_addr to i64), [[TMP1]]
-; X86-NEXT: [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 ptrtoint (ptr @__typeid_bytearray7_align to i64))
-; X86-NEXT: [[TMP8:%.*]] = icmp ule i64 [[TMP7]], ptrtoint (ptr @__typeid_bytearray7_size_m1 to i64)
-; X86-NEXT: br i1 [[TMP8]], label %[[TMP9:.*]], label %[[TMP14:.*]]
-; X86: [[TMP9]]:
-; X86-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr @__typeid_bytearray7_byte_array, i64 [[TMP7]]
-; X86-NEXT: [[TMP11:%.*]] = load i8, ptr [[TMP10]], align 1
-; X86-NEXT: [[TMP12:%.*]] = and i8 [[TMP11]], ptrtoint (ptr @__typeid_bytearray7_bit_mask to i8)
-; X86-NEXT: [[TMP13:%.*]] = icmp ne i8 [[TMP12]], 0
-; X86-NEXT: br label %[[TMP14]]
-; X86: [[TMP14]]:
-; X86-NEXT: [[TMP15:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP13]], %[[TMP9]] ]
-; X86-NEXT: ret i1 [[TMP15]]
+; X86-NEXT: [[TMP3:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 ptrtoint (ptr @__typeid_bytearray7_align to i64))
+; X86-NEXT: [[TMP4:%.*]] = icmp ule i64 [[TMP3]], ptrtoint (ptr @__typeid_bytearray7_size_m1 to i64)
+; X86-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP10:%.*]]
+; X86: 5:
+; X86-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr @__typeid_bytearray7_byte_array, i64 [[TMP3]]
+; X86-NEXT: [[TMP7:%.*]] = load i8, ptr [[TMP6]], align 1
+; X86-NEXT: [[TMP8:%.*]] = and i8 [[TMP7]], ptrtoint (ptr @__typeid_bytearray7_bit_mask to i8)
+; X86-NEXT: [[TMP9:%.*]] = icmp ne i8 [[TMP8]], 0
+; X86-NEXT: br label [[TMP10]]
+; X86: 10:
+; X86-NEXT: [[TMP11:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP9]], [[TMP5]] ]
+; X86-NEXT: ret i1 [[TMP11]]
;
; ARM-LABEL: define i1 @bytearray7(
; ARM-SAME: ptr [[P:%.*]]) {
; ARM-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
; ARM-NEXT: [[TMP2:%.*]] = sub i64 ptrtoint (ptr @__typeid_bytearray7_global_addr to i64), [[TMP1]]
-; ARM-NEXT: [[TMP5:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 3)
-; ARM-NEXT: [[TMP6:%.*]] = icmp ule i64 [[TMP5]], 43
-; ARM-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP12:%.*]]
+; ARM-NEXT: [[TMP3:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 3)
+; ARM-NEXT: [[TMP4:%.*]] = icmp ule i64 [[TMP3]], 43
+; ARM-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP10:%.*]]
; ARM: 5:
-; ARM-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr @__typeid_bytearray7_byte_array, i64 [[TMP5]]
-; ARM-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 1
-; ARM-NEXT: [[TMP10:%.*]] = and i8 [[TMP9]], ptrtoint (ptr inttoptr (i64 64 to ptr) to i8)
-; ARM-NEXT: [[TMP11:%.*]] = icmp ne i8 [[TMP10]], 0
-; ARM-NEXT: br label [[TMP12]]
+; ARM-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr @__typeid_bytearray7_byte_array, i64 [[TMP3]]
+; ARM-NEXT: [[TMP7:%.*]] = load i8, ptr [[TMP6]], align 1
+; ARM-NEXT: [[TMP8:%.*]] = and i8 [[TMP7]], ptrtoint (ptr inttoptr (i64 64 to ptr) to i8)
+; ARM-NEXT: [[TMP9:%.*]] = icmp ne i8 [[TMP8]], 0
+; ARM-NEXT: br label [[TMP10]]
; ARM: 10:
-; ARM-NEXT: [[TMP13:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP11]], [[TMP7]] ]
-; ARM-NEXT: ret i1 [[TMP13]]
+; ARM-NEXT: [[TMP11:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP9]], [[TMP5]] ]
+; ARM-NEXT: ret i1 [[TMP11]]
;
%x = call i1 @llvm.type.test(ptr %p, metadata !"bytearray7")
ret i1 %x
@@ -118,35 +129,35 @@ define i1 @bytearray32(ptr %p) {
; X86-SAME: ptr [[P:%.*]]) {
; X86-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
; X86-NEXT: [[TMP2:%.*]] = sub i64 ptrtoint (ptr @__typeid_bytearray32_global_addr to i64), [[TMP1]]
-; X86-NEXT: [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 ptrtoint (ptr @__typeid_bytearray32_align to i64))
-; X86-NEXT: [[TMP8:%.*]] = icmp ule i64 [[TMP7]], ptrtoint (ptr @__typeid_bytearray32_size_m1 to i64)
-; X86-NEXT: br i1 [[TMP8]], label %[[TMP9:.*]], label %[[TMP14:.*]]
-; X86: [[TMP9]]:
-; X86-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr @__typeid_bytearray32_byte_array, i64 [[TMP7]]
-; X86-NEXT: [[TMP11:%.*]] = load i8, ptr [[TMP10]], align 1
-; X86-NEXT: [[TMP12:%.*]] = and i8 [[TMP11]], ptrtoint (ptr @__typeid_bytearray32_bit_mask to i8)
-; X86-NEXT: [[TMP13:%.*]] = icmp ne i8 [[TMP12]], 0
-; X86-NEXT: br label %[[TMP14]]
-; X86: [[TMP14]]:
-; X86-NEXT: [[TMP15:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP13]], %[[TMP9]] ]
-; X86-NEXT: ret i1 [[TMP15]]
+; X86-NEXT: [[TMP3:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 ptrtoint (ptr @__typeid_bytearray32_align to i64))
+; X86-NEXT: [[TMP4:%.*]] = icmp ule i64 [[TMP3]], ptrtoint (ptr @__typeid_bytearray32_size_m1 to i64)
+; X86-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP10:%.*]]
+; X86: 5:
+; X86-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr @__typeid_bytearray32_byte_array, i64 [[TMP3]]
+; X86-NEXT: [[TMP7:%.*]] = load i8, ptr [[TMP6]], align 1
+; X86-NEXT: [[TMP8:%.*]] = and i8 [[TMP7]], ptrtoint (ptr @__typeid_bytearray32_bit_mask to i8)
+; X86-NEXT: [[TMP9:%.*]] = icmp ne i8 [[TMP8]], 0
+; X86-NEXT: br label [[TMP10]]
+; X86: 10:
+; X86-NEXT: [[TMP11:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP9]], [[TMP5]] ]
+; X86-NEXT: ret i1 [[TMP11]]
;
; ARM-LABEL: define i1 @bytearray32(
; ARM-SAME: ptr [[P:%.*]]) {
; ARM-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
; ARM-NEXT: [[TMP2:%.*]] = sub i64 ptrtoint (ptr @__typeid_bytearray32_global_addr to i64), [[TMP1]]
-; ARM-NEXT: [[TMP5:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 4)
-; ARM-NEXT: [[TMP6:%.*]] = icmp ule i64 [[TMP5]], 12346
-; ARM-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP12:%.*]]
+; ARM-NEXT: [[TMP3:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 4)
+; ARM-NEXT: [[TMP4:%.*]] = icmp ule i64 [[TMP3]], 12346
+; ARM-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP10:%.*]]
; ARM: 5:
-; ARM-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr @__typeid_bytearray32_byte_array, i64 [[TMP5]]
-; ARM-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 1
-; ARM-NEXT: [[TMP10:%.*]] = and i8 [[TMP9]], ptrtoint (ptr inttoptr (i64 128 to ptr) to i8)
-; ARM-NEXT: [[TMP11:%.*]] = icmp ne i8 [[TMP10]], 0
-; ARM-NEXT: br label [[TMP12]]
+; ARM-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr @__typeid_bytearray32_byte_array, i64 [[TMP3]]
+; ARM-NEXT: [[TMP7:%.*]] = load i8, ptr [[TMP6]], align 1
+; ARM-NEXT: [[TMP8:%.*]] = and i8 [[TMP7]], ptrtoint (ptr inttoptr (i64 128 to ptr) to i8)
+; ARM-NEXT: [[TMP9:%.*]] = icmp ne i8 [[TMP8]], 0
+; ARM-NEXT: br label [[TMP10]]
; ARM: 10:
-; ARM-NEXT: [[TMP13:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP11]], [[TMP7]] ]
-; ARM-NEXT: ret i1 [[TMP13]]
+; ARM-NEXT: [[TMP11:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP9]], [[TMP5]] ]
+; ARM-NEXT: ret i1 [[TMP11]]
;
%x = call i1 @llvm.type.test(ptr %p, metadata !"bytearray32")
ret i1 %x
@@ -157,37 +168,37 @@ define i1 @inline5(ptr %p) {
; X86-SAME: ptr [[P:%.*]]) {
; X86-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
; X86-NEXT: [[TMP2:%.*]] = sub i64 ptrtoint (ptr @__typeid_inline5_global_addr to i64), [[TMP1]]
-; X86-NEXT: [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 ptrtoint (ptr @__typeid_inline5_align to i64))
-; X86-NEXT: [[TMP8:%.*]] = icmp ule i64 [[TMP7]], ptrtoint (ptr @__typeid_inline5_size_m1 to i64)
-; X86-NEXT: br i1 [[TMP8]], label %[[TMP9:.*]], label %[[TMP15:.*]]
-; X86: [[TMP9]]:
-; X86-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP7]] to i32
-; X86-NEXT: [[TMP11:%.*]] = and i32 [[TMP10]], 31
-; X86-NEXT: [[TMP12:%.*]] = shl i32 1, [[TMP11]]
-; X86-NEXT: [[TMP13:%.*]] = and i32 ptrtoint (ptr @__typeid_inline5_inline_bits to i32), [[TMP12]]
-; X86-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
-; X86-NEXT: br label %[[TMP15]]
-; X86: [[TMP15]]:
-; X86-NEXT: [[TMP16:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP14]], %[[TMP9]] ]
-; X86-NEXT: ret i1 [[TMP16]]
+; X86-NEXT: [[TMP3:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 ptrtoint (ptr @__typeid_inline5_align to i64))
+; X86-NEXT: [[TMP4:%.*]] = icmp ule i64 [[TMP3]], ptrtoint (ptr @__typeid_inline5_size_m1 to i64)
+; X86-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP11:%.*]]
+; X86: 5:
+; X86-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP3]] to i32
+; X86-NEXT: [[TMP7:%.*]] = and i32 [[TMP6]], 31
+; X86-NEXT: [[TMP8:%.*]] = shl i32 1, [[TMP7]]
+; X86-NEXT: [[TMP9:%.*]] = and i32 ptrtoint (ptr @__typeid_inline5_inline_bits to i32), [[TMP8]]
+; X86-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
+; X86-NEXT: br label [[TMP11]]
+; X86: 11:
+; X86-NEXT: [[TMP12:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP10]], [[TMP5]] ]
+; X86-NEXT: ret i1 [[TMP12]]
;
; ARM-LABEL: define i1 @inline5(
; ARM-SAME: ptr [[P:%.*]]) {
; ARM-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
; ARM-NEXT: [[TMP2:%.*]] = sub i64 ptrtoint (ptr @__typeid_inline5_global_addr to i64), [[TMP1]]
-; ARM-NEXT: [[TMP5:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 5)
-; ARM-NEXT: [[TMP6:%.*]] = icmp ule i64 [[TMP5]], 31
-; ARM-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP13:%.*]]
+; ARM-NEXT: [[TMP3:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 5)
+; ARM-NEXT: [[TMP4:%.*]] = icmp ule i64 [[TMP3]], 31
+; ARM-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP11:%.*]]
; ARM: 5:
-; ARM-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP5]] to i32
-; ARM-NEXT: [[TMP9:%.*]] = and i32 [[TMP8]], 31
-; ARM-NEXT: [[TMP10:%.*]] = shl i32 1, [[TMP9]]
-; ARM-NEXT: [[TMP11:%.*]] = and i32 123, [[TMP10]]
-; ARM-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
-; ARM-NEXT: br label [[TMP13]]
+; ARM-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP3]] to i32
+; ARM-NEXT: [[TMP7:%.*]] = and i32 [[TMP6]], 31
+; ARM-NEXT: [[TMP8:%.*]] = shl i32 1, [[TMP7]]
+; ARM-NEXT: [[TMP9:%.*]] = and i32 123, [[TMP8]]
+; ARM-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
+; ARM-NEXT: br label [[TMP11]]
; ARM: 11:
-; ARM-NEXT: [[TMP14:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP12]], [[TMP7]] ]
-; ARM-NEXT: ret i1 [[TMP14]]
+; ARM-NEXT: [[TMP12:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP10]], [[TMP5]] ]
+; ARM-NEXT: ret i1 [[TMP12]]
;
%x = call i1 @llvm.type.test(ptr %p, metadata !"inline5")
ret i1 %x
@@ -198,35 +209,35 @@ define i1 @inline6(ptr %p) {
; X86-SAME: ptr [[P:%.*]]) {
; X86-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
; X86-NEXT: [[TMP2:%.*]] = sub i64 ptrtoint (ptr @__typeid_inline6_global_addr to i64), [[TMP1]]
-; X86-NEXT: [[TMP7:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 ptrtoint (ptr @__typeid_inline6_align to i64))
-; X86-NEXT: [[TMP8:%.*]] = icmp ule i64 [[TMP7]], ptrtoint (ptr @__typeid_inline6_size_m1 to i64)
-; X86-NEXT: br i1 [[TMP8]], label %[[TMP9:.*]], label %[[TMP14:.*]]
-; X86: [[TMP9]]:
-; X86-NEXT: [[TMP10:%.*]] = and i64 [[TMP7]], 63
-; X86-NEXT: [[TMP11:%.*]] = shl i64 1, [[TMP10]]
-; X86-NEXT: [[TMP12:%.*]] = and i64 ptrtoint (ptr @__typeid_inline6_inline_bits to i64), [[TMP11]]
-; X86-NEXT: [[TMP13:%.*]] = icmp ne i64 [[TMP12]], 0
-; X86-NEXT: br label %[[TMP14]]
-; X86: [[TMP14]]:
-; X86-NEXT: [[TMP15:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP13]], %[[TMP9]] ]
-; X86-NEXT: ret i1 [[TMP15]]
+; X86-NEXT: [[TMP3:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 ptrtoint (ptr @__typeid_inline6_align to i64))
+; X86-NEXT: [[TMP4:%.*]] = icmp ule i64 [[TMP3]], ptrtoint (ptr @__typeid_inline6_size_m1 to i64)
+; X86-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP10:%.*]]
+; X86: 5:
+; X86-NEXT: [[TMP6:%.*]] = and i64 [[TMP3]], 63
+; X86-NEXT: [[TMP7:%.*]] = shl i64 1, [[TMP6]]
+; X86-NEXT: [[TMP8:%.*]] = and i64 ptrtoint (ptr @__typeid_inline6_inline_bits to i64), [[TMP7]]
+; X86-NEXT: [[TMP9:%.*]] = icmp ne i64 [[TMP8]], 0
+; X86-NEXT: br label [[TMP10]]
+; X86: 10:
+; X86-NEXT: [[TMP11:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP9]], [[TMP5]] ]
+; X86-NEXT: ret i1 [[TMP11]]
;
; ARM-LABEL: define i1 @inline6(
; ARM-SAME: ptr [[P:%.*]]) {
; ARM-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
; ARM-NEXT: [[TMP2:%.*]] = sub i64 ptrtoint (ptr @__typeid_inline6_global_addr to i64), [[TMP1]]
-; ARM-NEXT: [[TMP5:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 6)
-; ARM-NEXT: [[TMP6:%.*]] = icmp ule i64 [[TMP5]], 63
-; ARM-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP12:%.*]]
+; ARM-NEXT: [[TMP3:%.*]] = call i64 @llvm.fshr.i64(i64 [[TMP2]], i64 [[TMP2]], i64 6)
+; ARM-NEXT: [[TMP4:%.*]] = icmp ule i64 [[TMP3]], 63
+; ARM-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP10:%.*]]
; ARM: 5:
-; ARM-NEXT: [[TMP8:%.*]] = and i64 [[TMP5]], 63
-; ARM-NEXT: [[TMP9:%.*]] = shl i64 1, [[TMP8]]
-; ARM-NEXT: [[TMP10:%.*]] = and i64 1000000000000, [[TMP9]]
-; ARM-NEXT: [[TMP11:%.*]] = icmp ne i64 [[TMP10]], 0
-; ARM-NEXT: br label [[TMP12]]
+; ARM-NEXT: [[TMP6:%.*]] = and i64 [[TMP3]], 63
+; ARM-NEXT: [[TMP7:%.*]] = shl i64 1, [[TMP6]]
+; ARM-NEXT: [[TMP8:%.*]] = and i64 1000000000000, [[TMP7]]
+; ARM-NEXT: [[TMP9:%.*]] = icmp ne i64 [[TMP8]], 0
+; ARM-NEXT: br label [[TMP10]]
; ARM: 10:
-; ARM-NEXT: [[TMP13:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP11]], [[TMP7]] ]
-; ARM-NEXT: ret i1 [[TMP13]]
+; ARM-NEXT: [[TMP11:%.*]] = phi i1 [ false, [[TMP0:%.*]] ], [ [[TMP9]], [[TMP5]] ]
+; ARM-NEXT: ret i1 [[TMP11]]
;
%x = call i1 @llvm.type.test(ptr %p, metadata !"inline6")
ret i1 %x
@@ -242,10 +253,17 @@ define i1 @single(ptr %p) {
%x = call i1 @llvm.type.test(ptr %p, metadata !"single")
ret i1 %x
}
-
-; X86: !0 = !{i64 0, i64 256}
-; X86: !1 = !{i64 0, i64 64}
-; X86: !2 = !{i64 -1, i64 -1}
-; X86: !3 = !{i64 0, i64 32}
-; X86: !4 = !{i64 0, i64 4294967296}
-; X86: !5 = !{i64 0, i64 128}
+;.
+; X86: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+; X86: attributes #[[ATTR1:[0-9]+]] = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
+;.
+; X86: [[META0]] = !{i64 0, i64 256}
+; X86: [[META1]] = !{i64 0, i64 64}
+; X86: [[META2]] = !{i64 -1, i64 -1}
+; X86: [[META3]] = !{i64 0, i64 32}
+; X86: [[META4]] = !{i64 0, i64 4294967296}
+; X86: [[META5]] = !{i64 0, i64 128}
+;.
+; ARM: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+; ARM: attributes #[[ATTR1:[0-9]+]] = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
+;.
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