[llvm] [RISCV] Combine (addi (addi)) and add post riscv-opt-w-instrs machine-combiner (PR #171165)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp,h -- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp llvm/lib/Target/RISCV/RISCVInstrInfo.h llvm/lib/Target/RISCV/RISCVTargetMachine.cpp --diff_from_common_commit
``````````

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``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 37dec648b..bc65989a9 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -2852,8 +2852,8 @@ static void combineADDIADDI(MachineInstr &Root,
 
   auto MIB = BuildMI(*MF, MIMetadata(Root), TII->get(RISCV::ADDI),
                      Root.getOperand(0).getReg())
-                  .addReg(X.getReg(), getKillRegState(X.isKill()))
-                  .addImm(Sum);
+                 .addReg(X.getReg(), getKillRegState(X.isKill()))
+                 .addImm(Sum);
   InsInstrs.push_back(MIB);
   DelInstrs.push_back(Inner);
   DelInstrs.push_back(&Root);

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https://github.com/llvm/llvm-project/pull/171165