[llvm] a05fc9e - HexagonGenWideningVecInstr.cpp - fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFC. (#171095)

[via llvm-commits]

Author: Simon Pilgrim
Date: 2025-12-08T16:17:25Z
New Revision: a05fc9edb99b143f837baf136a68c35444558069

URL: https://github.com/llvm/llvm-project/commit/a05fc9edb99b143f837baf136a68c35444558069
DIFF: https://github.com/llvm/llvm-project/commit/a05fc9edb99b143f837baf136a68c35444558069.diff

LOG: HexagonGenWideningVecInstr.cpp - fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFC. (#171095)

Added: 
    

Modified: 
    llvm/lib/Target/Hexagon/HexagonGenWideningVecInstr.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/Hexagon/HexagonGenWideningVecInstr.cpp b/llvm/lib/Target/Hexagon/HexagonGenWideningVecInstr.cpp
index 895de57561430..478eaf10b0710 100644
--- a/llvm/lib/Target/Hexagon/HexagonGenWideningVecInstr.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonGenWideningVecInstr.cpp
@@ -596,7 +596,7 @@ bool HexagonGenWideningVecInstr::replaceWithIntrinsic(Instruction *Inst,
   if (IsConstScalar && OPK == OP_Shl) {
     if (((NewOpEltSize == 8) && (SplatVal > 0) && (SplatVal < 8)) ||
         ((NewOpEltSize == 16) && (SplatVal > 0) && (SplatVal < 16))) {
-      SplatVal = 1 << SplatVal;
+      SplatVal = 1LL << SplatVal;
       OPK = OP_Mul;
     } else {
       return false;