[llvm] [AArch64] Mark Armv8.4-a LDAPUR* instructions as mayLoad (PR #171142)

[David Green via llvm-commits]

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@@ -4384,6 +4384,7 @@ class BaseLoadStoreUnscale<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
 // Armv8.4 LDAPR & STLR with Immediate Offset instruction
 multiclass BaseLoadUnscaleV84<string asm, bits<2> sz, bits<2> opc,
                               DAGOperand regtype > {
+  let mayLoad = 1 in
   def i : BaseLoadStoreUnscale<sz, 0, opc, (outs regtype:$Rt),
                                (ins GPR64sp:$Rn, simm9:$offset), asm, []>,
           Sched<[WriteST]> {
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davemgreen wrote:

This should probably be WriteLD or WriteAtomic. The scheduling info in the tests looks incorrect.

https://github.com/llvm/llvm-project/pull/171142