[clang] [llvm] [RISCV] Add Propeller support for RISC-V (PR #170992)
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Mon Dec 8 07:23:29 PST 2025
https://github.com/leidian977 updated https://github.com/llvm/llvm-project/pull/170992
>From c90691476842a90b414949724eacaea1ecc6f472 Mon Sep 17 00:00:00 2001
From: leidian977 <943677770 at qq.com>
Date: Sat, 6 Dec 2025 13:20:34 -0500
Subject: [PATCH 1/3] [RISCV] Add basic Propeller infrastructure
---
clang/lib/Driver/ToolChains/Clang.cpp | 7 +++++++
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 9 +++++++++
llvm/lib/Target/RISCV/RISCVInstrInfo.h | 3 +++
3 files changed, 19 insertions(+)
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp
index 0380568412e62..d6b93777b8dd1 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -6128,6 +6128,13 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA,
<< A->getAsString(Args) << A->getValue();
else
A->render(Args, CmdArgs);
+ } else if (Triple.isRISCV() && Triple.isOSBinFormatELF()) {
+ // Add RISC-V support for basic block sections
+ if (Val != "labels" && Val != "none" && !Val.starts_with("list="))
+ D.Diag(diag::err_drv_invalid_value)
+ << A->getAsString(Args) << A->getValue();
+ else
+ A->render(Args, CmdArgs);
} else if (Triple.isNVPTX()) {
// Do not pass the option to the GPU compilation. We still want it enabled
// for the host-side compilation, so seeing it here is not an error.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 9fb7ac0573824..269a3ca539635 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -89,6 +89,15 @@ RISCVInstrInfo::RISCVInstrInfo(const RISCVSubtarget &STI)
#define GET_INSTRINFO_HELPERS
#include "RISCVGenInstrInfo.inc"
+void RISCVInstrInfo::insertNoop(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI) const {
+ DebugLoc DL;
+ BuildMI(MBB, MI, DL, get(RISCV::ADDI))
+ .addReg(RISCV::X0)
+ .addReg(RISCV::X0)
+ .addImm(0);
+}
+
MCInst RISCVInstrInfo::getNop() const {
if (STI.hasStdExtZca())
return MCInstBuilder(RISCV::C_NOP);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index 0ffe015b9fac8..bf12c1900be25 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -86,6 +86,9 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
const RISCVRegisterInfo &getRegisterInfo() const { return RegInfo; }
+ void insertNoop(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI) const override;
+
MCInst getNop() const override;
Register isLoadFromStackSlot(const MachineInstr &MI,
>From 8d37c32cca26d5820f3012084dbabca0c27de392 Mon Sep 17 00:00:00 2001
From: leidian977 <943677770 at qq.com>
Date: Mon, 8 Dec 2025 10:00:22 -0500
Subject: [PATCH 2/3] [RISCV] Add basic Propeller Test
---
clang/lib/Driver/ToolChains/Clang.cpp | 2 +-
clang/test/Driver/basic-block-address-map.c | 1 +
clang/test/Driver/fbasic-block-sections.c | 5 +++++
3 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp
index d6b93777b8dd1..62ceaa7536f04 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -6098,7 +6098,7 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA,
if (Arg *A = Args.getLastArg(options::OPT_fbasic_block_address_map,
options::OPT_fno_basic_block_address_map)) {
- if ((Triple.isX86() || Triple.isAArch64()) && Triple.isOSBinFormatELF()) {
+ if ((Triple.isX86() || Triple.isAArch64() || Triple.isRISCV()) && Triple.isOSBinFormatELF()) {
if (A->getOption().matches(options::OPT_fbasic_block_address_map))
A->render(Args, CmdArgs);
} else {
diff --git a/clang/test/Driver/basic-block-address-map.c b/clang/test/Driver/basic-block-address-map.c
index 12393e8ebfd54..48d8ae445f45d 100644
--- a/clang/test/Driver/basic-block-address-map.c
+++ b/clang/test/Driver/basic-block-address-map.c
@@ -1,5 +1,6 @@
// RUN: %clang -### --target=x86_64 -fbasic-block-address-map %s -S 2>&1 | FileCheck -check-prefix=CHECK-PRESENT %s
// RUN: %clang -### --target=aarch64 -fbasic-block-address-map %s -S 2>&1 | FileCheck -check-prefix=CHECK-PRESENT %s
+// RUN: %clang -### --target=riscv64 -fbasic-block-address-map %s -S 2>&1 | FileCheck -check-prefix=CHECK-PRESENT %s
// CHECK-PRESENT: -fbasic-block-address-map
// RUN: %clang -### --target=x86_64 -fno-basic-block-address-map %s -S 2>&1 | FileCheck %s --check-prefix=CHECK-ABSENT
diff --git a/clang/test/Driver/fbasic-block-sections.c b/clang/test/Driver/fbasic-block-sections.c
index 6dfba5f404cee..78999c89ea9f8 100644
--- a/clang/test/Driver/fbasic-block-sections.c
+++ b/clang/test/Driver/fbasic-block-sections.c
@@ -9,6 +9,11 @@
// RUN: not %clang -c --target=arm-unknown-linux -fbasic-block-sections=all %s -S 2>&1 | FileCheck -check-prefix=CHECK-TRIPLE %s
// RUN: %clang -### --target=arm-unknown-linux -fbasic-block-sections=all -fbasic-block-sections=none %s -S 2>&1 \
// RUN: | FileCheck -check-prefix=CHECK-NOOPT %s
+// RUN: %clang -### --target=riscv64 -fbasic-block-sections=none %s -S 2>&1 | FileCheck -check-prefix=CHECK-OPT-NONE %s
+// RUN: %clang -### --target=riscv64 -fbasic-block-sections=list=%s %s -S 2>&1 | FileCheck -check-prefix=CHECK-OPT-LIST %s
+// RUN: %clang -### --target=riscv64 -fbasic-block-sections=labels %s -S 2>&1 | FileCheck -check-prefix=CHECK-OPT-LABELS %s
+// RUN: not %clang -### --target=riscv64 -fbasic-block-sections=all %s -S 2>&1 | FileCheck -check-prefix=CHECK-INVALID-VALUE %s
+// RUN: not %clang -c --target=riscv64-unknown-linux -fbasic-block-sections=all %s -S 2>&1 | FileCheck -check-prefix=CHECK-INVALID-VALUE %s
// RUN: not %clang -c --target=x86_64-apple-darwin10 -fbasic-block-sections=all %s -S 2>&1 | FileCheck -check-prefix=CHECK-TRIPLE %s
// RUN: not %clang -### --target=x86_64 -fbasic-block-sections=alll %s -S 2>&1 | FileCheck -check-prefix=CHECK-INVALID-VALUE %s
// RUN: not %clang -### --target=x86_64 -fbasic-block-sections=list %s -S 2>&1 | FileCheck -check-prefix=CHECK-INVALID-VALUE %s
>From bf8eeb68cc9077c420e73dbf2246342d21c842ba Mon Sep 17 00:00:00 2001
From: leidian977 <943677770 at qq.com>
Date: Mon, 8 Dec 2025 10:23:11 -0500
Subject: [PATCH 3/3] [RISCV] update RISCVInstrInfo::insertNoop
---
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 269a3ca539635..2cfc88b41763f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -92,6 +92,8 @@ RISCVInstrInfo::RISCVInstrInfo(const RISCVSubtarget &STI)
void RISCVInstrInfo::insertNoop(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const {
DebugLoc DL;
+ if (STI.hasStdExtZca())
+ BuildMI(MBB, MI, DL, get(RISCV::C_NOP));;
BuildMI(MBB, MI, DL, get(RISCV::ADDI))
.addReg(RISCV::X0)
.addReg(RISCV::X0)
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