[llvm] [X86] LowerAsmOperandForConstraint - ensure we treat L constraint immediates as signed constants (PR #171098)

[Simon Pilgrim via llvm-commits]

https://github.com/RKSimon updated https://github.com/llvm/llvm-project/pull/171098

>From b8a26dba1cde68ce4a3d08b2dd4fee9378211e47 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: Mon, 8 Dec 2025 09:42:26 +0000
Subject: [PATCH 1/4] [X86] LowerAsmOperandForConstraint - ensure we treat L
 constraint immediates as signed constants

getTargetConstant no longer tolerates sign-extended values that can't be represented by the appropriate APInt bitwidth, which now defaults to unsigned behaviour.

Fixes #166058
---
 llvm/lib/Target/X86/X86ISelLowering.cpp |  4 ++--
 llvm/test/CodeGen/X86/pr166058.ll       | 15 +++++++++++++++
 2 files changed, 17 insertions(+), 2 deletions(-)
 create mode 100644 llvm/test/CodeGen/X86/pr166058.ll

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index d0ae75b2e6785..8f22f8c3618a6 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -61928,8 +61928,8 @@ void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
     if (auto *C = dyn_cast<ConstantSDNode>(Op)) {
       if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
           (Subtarget.is64Bit() && C->getZExtValue() == 0xffffffff)) {
-        Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
-                                       Op.getValueType());
+        Result = DAG.getSignedTargetConstant(C->getSExtValue(), SDLoc(Op),
+                                             Op.getValueType());
         break;
       }
     }
diff --git a/llvm/test/CodeGen/X86/pr166058.ll b/llvm/test/CodeGen/X86/pr166058.ll
new file mode 100644
index 0000000000000..2e0bb6036820f
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr166058.ll
@@ -0,0 +1,15 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=x86_64-- | FileCheck %s
+
+ at out = global i32 0, align 4
+define void @bar() {
+; CHECK-LABEL: bar:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movq out at GOTPCREL(%rip), %rax
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    addq $-1, (%rax)
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    retq
+  call void asm "addq $1,$0", "=*m,L,~{dirflag},~{fpsr},~{flags}"(ptr elementtype(i32) @out, i32 -1)
+  ret void
+}

>From 55438fbd0468b3c480e8f7209af4b9ff651ff0cc Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: Mon, 8 Dec 2025 10:44:29 +0000
Subject: [PATCH 2/4] fix typo in RUN

---
 llvm/test/CodeGen/X86/pr166058.ll | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/test/CodeGen/X86/pr166058.ll b/llvm/test/CodeGen/X86/pr166058.ll
index 2e0bb6036820f..cecb73b43b5fb 100644
--- a/llvm/test/CodeGen/X86/pr166058.ll
+++ b/llvm/test/CodeGen/X86/pr166058.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=x86_64-- | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
 
 @out = global i32 0, align 4
 define void @bar() {

>From d3530a6fabeef76f6c3061477ffee8b133768318 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: Mon, 8 Dec 2025 14:37:57 +0000
Subject: [PATCH 3/4] Fix elementtype

---
 llvm/test/CodeGen/X86/pr166058.ll | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/test/CodeGen/X86/pr166058.ll b/llvm/test/CodeGen/X86/pr166058.ll
index cecb73b43b5fb..d22f924cc96ae 100644
--- a/llvm/test/CodeGen/X86/pr166058.ll
+++ b/llvm/test/CodeGen/X86/pr166058.ll
@@ -10,6 +10,6 @@ define void @bar() {
 ; CHECK-NEXT:    addq $-1, (%rax)
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    retq
-  call void asm "addq $1,$0", "=*m,L,~{dirflag},~{fpsr},~{flags}"(ptr elementtype(i32) @out, i32 -1)
+  call void asm "addq $1,$0", "=*m,L,~{dirflag},~{fpsr},~{flags}"(ptr elementtype(i64) @out, i32 -1)
   ret void
 }

>From 3211611c5752814c585098c23a60aa7f3d892e3d Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: Mon, 8 Dec 2025 14:46:48 +0000
Subject: [PATCH 4/4] Fix instruction/elementtype

---
 llvm/test/CodeGen/X86/pr166058.ll | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/llvm/test/CodeGen/X86/pr166058.ll b/llvm/test/CodeGen/X86/pr166058.ll
index d22f924cc96ae..42d68fd0fad12 100644
--- a/llvm/test/CodeGen/X86/pr166058.ll
+++ b/llvm/test/CodeGen/X86/pr166058.ll
@@ -7,9 +7,9 @@ define void @bar() {
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movq out at GOTPCREL(%rip), %rax
 ; CHECK-NEXT:    #APP
-; CHECK-NEXT:    addq $-1, (%rax)
+; CHECK-NEXT:    addl $-1, (%rax)
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    retq
-  call void asm "addq $1,$0", "=*m,L,~{dirflag},~{fpsr},~{flags}"(ptr elementtype(i64) @out, i32 -1)
+  call void asm "addl $1,$0", "=*m,L,~{dirflag},~{fpsr},~{flags}"(ptr elementtype(i32) @out, i32 -1)
   ret void
 }