[clang] [llvm] [AArch64] Add support for C1 CPUs (PR #171124)

[via llvm-commits]

Andarwinux wrote:

It looks like all C1 series enabled SME and MOPS unconditionally. But according to Arm, only C1-Ultra/Premium are forced with SME support, and MOPS may cause performance degradation.

https://developer.arm.com/documentation/111076/0100
https://developer.arm.com/documentation/107753/0001/The-C1-Nano--core/C1-Nano--core-features
>The C1-SME2unit is optional, unless the cluster includes an ultimate-performance core. If the C1-SME2unit is not implemented, SME and SME2 are not supported. For more information about configuring the C1-SME2 unit, see the Arm® C1-Scalable Matrix Extension 2 Configuration and Integration Manual and the RTL configuration process section in the Arm® C1-DynamIQ™ Shared Unit Configuration and Integration Manual.

https://developer.arm.com/documentation/111077/8-0
> Under certain micro-architectural conditions, when the Processing Element (PE) is executing
FEAT_MOPS instructions, performance might be degraded. This is due to micro-architectural flushes that
occur due to read-after-write hazards or hardware prefetch ineffectively caching contiguous accesses.

https://github.com/llvm/llvm-project/pull/171124