[clang] [llvm] [AArch64] Add support for C1 CPUs (PR #171124)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 8 05:45:08 PST 2025
https://github.com/dcandler created https://github.com/llvm/llvm-project/pull/171124
This patch adds initial support for the Arm v9.3 C1 processors:
* C1-Nano
* C1-Pro
* C1-Premium
* C1-Ultra
For more information on each, see:
https://developer.arm.com/Processors/C1-Nano
https://developer.arm.com/Processors/C1-Pro
https://developer.arm.com/Processors/C1-Premium
https://developer.arm.com/Processors/C1-Ultra
Technical Reference Manual for C1-Nano:
https://developer.arm.com/documentation/107753/latest/
Technical Reference Manual for C1-Pro:
https://developer.arm.com/documentation/107771/latest/
Technical Reference Manual for C1-Premium:
https://developer.arm.com/documentation/109416/latest/
Technical Reference Manual for C1-Ultra:
https://developer.arm.com/documentation/108014/latest/
>From 01c2164e60a957e251ab568241e8414fd5fd9ee3 Mon Sep 17 00:00:00 2001
From: David Candler <david.candler at arm.com>
Date: Mon, 8 Dec 2025 13:30:37 +0000
Subject: [PATCH] [AArch64] Add support for C1 CPUs
This patch adds initial support for the Arm v9.3 C1 processors:
* C1-Nano
* C1-Pro
* C1-Premium
* C1-Ultra
For more information on each, see:
https://developer.arm.com/Processors/C1-Nano
https://developer.arm.com/Processors/C1-Pro
https://developer.arm.com/Processors/C1-Premium
https://developer.arm.com/Processors/C1-Ultra
Technical Reference Manual for C1-Nano:
https://developer.arm.com/documentation/107753/latest/
Technical Reference Manual for C1-Pro:
https://developer.arm.com/documentation/107771/latest/
Technical Reference Manual for C1-Premium:
https://developer.arm.com/documentation/109416/latest/
Technical Reference Manual for C1-Ultra:
https://developer.arm.com/documentation/108014/latest/
---
clang/docs/ReleaseNotes.rst | 5 +
clang/test/Driver/aarch64-mcpu.c | 8 ++
.../aarch64-c1-nano.c | 69 +++++++++++
.../aarch64-c1-premium.c | 71 ++++++++++++
.../print-enabled-extensions/aarch64-c1-pro.c | 71 ++++++++++++
.../aarch64-c1-ultra.c | 71 ++++++++++++
.../Misc/target-invalid-cpu-note/aarch64.c | 4 +
llvm/docs/ReleaseNotes.md | 2 +
llvm/lib/Target/AArch64/AArch64Processors.td | 107 ++++++++++++++++++
llvm/lib/Target/AArch64/AArch64Subtarget.cpp | 4 +
llvm/lib/TargetParser/Host.cpp | 4 +
llvm/unittests/TargetParser/Host.cpp | 12 ++
.../TargetParser/TargetParserTest.cpp | 6 +-
13 files changed, 433 insertions(+), 1 deletion(-)
create mode 100644 clang/test/Driver/print-enabled-extensions/aarch64-c1-nano.c
create mode 100644 clang/test/Driver/print-enabled-extensions/aarch64-c1-premium.c
create mode 100644 clang/test/Driver/print-enabled-extensions/aarch64-c1-pro.c
create mode 100644 clang/test/Driver/print-enabled-extensions/aarch64-c1-ultra.c
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index acca997e0ff64..e36a4c64965cb 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -631,6 +631,11 @@ X86 Support
Arm and AArch64 Support
^^^^^^^^^^^^^^^^^^^^^^^
+- Support has been added for the following processors (command-line identifiers in parentheses):
+ - Arm C1-Nano (``c1-nano``)
+ - Arm C1-Pro (``c1-pro``)
+ - Arm C1-Premium (``c1-premium``)
+ - Arm C1-Ultra (``c1-ultra``)
- More intrinsics for the following AArch64 instructions:
FCVTZ[US], FCVTN[US], FCVTM[US], FCVTP[US], FCVTA[US]
diff --git a/clang/test/Driver/aarch64-mcpu.c b/clang/test/Driver/aarch64-mcpu.c
index 447ee4bd3a6f9..fdf2e4011487a 100644
--- a/clang/test/Driver/aarch64-mcpu.c
+++ b/clang/test/Driver/aarch64-mcpu.c
@@ -84,6 +84,14 @@
// CORTEX-A520: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a520"
// RUN: %clang --target=aarch64 -mcpu=cortex-a520ae -### -c %s 2>&1 | FileCheck -check-prefix=CORTEX-A520AE %s
// CORTEX-A520AE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a520ae"
+// RUN: %clang --target=aarch64 -mcpu=c1-nano -### -c %s 2>&1 | FileCheck -check-prefix=C1-NANO %s
+// C1-NANO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "c1-nano"
+// RUN: %clang --target=aarch64 -mcpu=c1-pro -### -c %s 2>&1 | FileCheck -check-prefix=C1-PRO %s
+// C1-PRO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "c1-pro"
+// RUN: %clang --target=aarch64 -mcpu=c1-premium -### -c %s 2>&1 | FileCheck -check-prefix=C1-PREMIUM %s
+// C1-PREMIUM: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "c1-premium"
+// RUN: %clang --target=aarch64 -mcpu=c1-ultra -### -c %s 2>&1 | FileCheck -check-prefix=C1-ULTRA %s
+// C1-ULTRA: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "c1-ultra"
// RUN: %clang --target=aarch64 -mcpu=cortex-r82 -### -c %s 2>&1 | FileCheck -check-prefix=CORTEXR82 %s
// CORTEXR82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-r82"
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-c1-nano.c b/clang/test/Driver/print-enabled-extensions/aarch64-c1-nano.c
new file mode 100644
index 0000000000000..33112527c9add
--- /dev/null
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-c1-nano.c
@@ -0,0 +1,69 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang --target=aarch64 --print-enabled-extensions -mcpu=c1-nano | FileCheck --strict-whitespace --implicit-check-not=FEAT_ %s
+
+// CHECK: Extensions enabled for the given AArch64 target
+// CHECK-EMPTY:
+// CHECK-NEXT: Architecture Feature(s) Description
+// CHECK-NEXT: FEAT_AMUv1 Enable Armv8.4-A Activity Monitors extension
+// CHECK-NEXT: FEAT_AMUv1p1 Enable Armv8.6-A Activity Monitors Virtualization support
+// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
+// CHECK-NEXT: FEAT_BF16 Enable BFloat16 Extension
+// CHECK-NEXT: FEAT_BTI Enable Branch Target Identification
+// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets
+// CHECK-NEXT: FEAT_CHK Enable Armv8.0-A Check Feature Status Extension
+// CHECK-NEXT: FEAT_CLRBHB Enable Clear BHB instruction
+// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
+// CHECK-NEXT: FEAT_CSV2_2 Enable architectural speculation restriction
+// CHECK-NEXT: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions
+// CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence
+// CHECK-NEXT: FEAT_DPB2 Enable Armv8.5-A Cache Clean to Point of Deep Persistence
+// CHECK-NEXT: FEAT_DotProd Enable dot product support
+// CHECK-NEXT: FEAT_ECV Enable enhanced counter virtualization extension
+// CHECK-NEXT: FEAT_ETE Enable Embedded Trace Extension
+// CHECK-NEXT: FEAT_FCMA Enable Armv8.3-A Floating-point complex number support
+// CHECK-NEXT: FEAT_FGT Enable fine grained virtualization traps extension
+// CHECK-NEXT: FEAT_FHM Enable FP16 FML instructions
+// CHECK-NEXT: FEAT_FP Enable Armv8.0-A Floating Point Extensions
+// CHECK-NEXT: FEAT_FP16 Enable half-precision floating-point data processing
+// CHECK-NEXT: FEAT_FPAC Enable Armv8.3-A Pointer Authentication Faulting enhancement
+// CHECK-NEXT: FEAT_FRINTTS Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int
+// CHECK-NEXT: FEAT_FlagM Enable Armv8.4-A Flag Manipulation instructions
+// CHECK-NEXT: FEAT_FlagM2 Enable alternative NZCV format for floating point comparisons
+// CHECK-NEXT: FEAT_HBC Enable Armv8.8-A Hinted Conditional Branches Extension
+// CHECK-NEXT: FEAT_HCX Enable Armv8.7-A HCRX_EL2 system register
+// CHECK-NEXT: FEAT_I8MM Enable Matrix Multiply Int8 Extension
+// CHECK-NEXT: FEAT_JSCVT Enable Armv8.3-A JavaScript FP conversion instructions
+// CHECK-NEXT: FEAT_LOR Enable Armv8.1-A Limited Ordering Regions extension
+// CHECK-NEXT: FEAT_LRCPC Enable support for RCPC extension
+// CHECK-NEXT: FEAT_LRCPC2 Enable Armv8.4-A RCPC instructions with Immediate Offsets
+// CHECK-NEXT: FEAT_LRCPC3 Enable Armv8.9-A RCPC instructions for A64 and Advanced SIMD and floating-point instruction set
+// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
+// CHECK-NEXT: FEAT_LSE2 Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules
+// CHECK-NEXT: FEAT_MOPS Enable Armv8.8-A memcpy and memset acceleration instructions
+// CHECK-NEXT: FEAT_MPAM Enable Armv8.4-A Memory system Partitioning and Monitoring extension
+// CHECK-NEXT: FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension
+// CHECK-NEXT: FEAT_NMI, FEAT_GICv3_NMI Enable Armv8.8-A Non-maskable Interrupts
+// CHECK-NEXT: FEAT_NV, FEAT_NV2 Enable Armv8.4-A Nested Virtualization Enchancement
+// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
+// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
+// CHECK-NEXT: FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension
+// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
+// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
+// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
+// CHECK-NEXT: FEAT_SB Enable Armv8.5-A Speculation Barrier
+// CHECK-NEXT: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension
+// CHECK-NEXT: FEAT_SME Enable Scalable Matrix Extension (SME)
+// CHECK-NEXT: FEAT_SME2 Enable Scalable Matrix Extension 2 (SME2) instructions
+// CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions
+// CHECK-NEXT: FEAT_SPECRES2 Enable Speculation Restriction Instruction
+// CHECK-NEXT: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit
+// CHECK-NEXT: FEAT_SVE Enable Scalable Vector Extension (SVE) instructions
+// CHECK-NEXT: FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions
+// CHECK-NEXT: FEAT_SVE_BitPerm Enable bit permutation SVE2 instructions
+// CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions
+// CHECK-NEXT: FEAT_TRBE Enable Trace Buffer Extension
+// CHECK-NEXT: FEAT_TRF Enable Armv8.4-A Trace extension
+// CHECK-NEXT: FEAT_UAO Enable Armv8.2-A UAO PState
+// CHECK-NEXT: FEAT_VHE Enable Armv8.1-A Virtual Host extension
+// CHECK-NEXT: FEAT_WFxT Enable Armv8.7-A WFET and WFIT instruction
+// CHECK-NEXT: FEAT_XS Enable Armv8.7-A limited-TLB-maintenance instruction
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-c1-premium.c b/clang/test/Driver/print-enabled-extensions/aarch64-c1-premium.c
new file mode 100644
index 0000000000000..3b146e36f81a2
--- /dev/null
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-c1-premium.c
@@ -0,0 +1,71 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang --target=aarch64 --print-enabled-extensions -mcpu=c1-premium | FileCheck --strict-whitespace --implicit-check-not=FEAT_ %s
+
+// CHECK: Extensions enabled for the given AArch64 target
+// CHECK-EMPTY:
+// CHECK-NEXT: Architecture Feature(s) Description
+// CHECK-NEXT: FEAT_AMUv1 Enable Armv8.4-A Activity Monitors extension
+// CHECK-NEXT: FEAT_AMUv1p1 Enable Armv8.6-A Activity Monitors Virtualization support
+// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
+// CHECK-NEXT: FEAT_BF16 Enable BFloat16 Extension
+// CHECK-NEXT: FEAT_BTI Enable Branch Target Identification
+// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets
+// CHECK-NEXT: FEAT_CHK Enable Armv8.0-A Check Feature Status Extension
+// CHECK-NEXT: FEAT_CLRBHB Enable Clear BHB instruction
+// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
+// CHECK-NEXT: FEAT_CSV2_2 Enable architectural speculation restriction
+// CHECK-NEXT: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions
+// CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence
+// CHECK-NEXT: FEAT_DPB2 Enable Armv8.5-A Cache Clean to Point of Deep Persistence
+// CHECK-NEXT: FEAT_DotProd Enable dot product support
+// CHECK-NEXT: FEAT_ECV Enable enhanced counter virtualization extension
+// CHECK-NEXT: FEAT_ETE Enable Embedded Trace Extension
+// CHECK-NEXT: FEAT_FCMA Enable Armv8.3-A Floating-point complex number support
+// CHECK-NEXT: FEAT_FGT Enable fine grained virtualization traps extension
+// CHECK-NEXT: FEAT_FHM Enable FP16 FML instructions
+// CHECK-NEXT: FEAT_FP Enable Armv8.0-A Floating Point Extensions
+// CHECK-NEXT: FEAT_FP16 Enable half-precision floating-point data processing
+// CHECK-NEXT: FEAT_FPAC Enable Armv8.3-A Pointer Authentication Faulting enhancement
+// CHECK-NEXT: FEAT_FRINTTS Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int
+// CHECK-NEXT: FEAT_FlagM Enable Armv8.4-A Flag Manipulation instructions
+// CHECK-NEXT: FEAT_FlagM2 Enable alternative NZCV format for floating point comparisons
+// CHECK-NEXT: FEAT_HBC Enable Armv8.8-A Hinted Conditional Branches Extension
+// CHECK-NEXT: FEAT_HCX Enable Armv8.7-A HCRX_EL2 system register
+// CHECK-NEXT: FEAT_I8MM Enable Matrix Multiply Int8 Extension
+// CHECK-NEXT: FEAT_JSCVT Enable Armv8.3-A JavaScript FP conversion instructions
+// CHECK-NEXT: FEAT_LOR Enable Armv8.1-A Limited Ordering Regions extension
+// CHECK-NEXT: FEAT_LRCPC Enable support for RCPC extension
+// CHECK-NEXT: FEAT_LRCPC2 Enable Armv8.4-A RCPC instructions with Immediate Offsets
+// CHECK-NEXT: FEAT_LRCPC3 Enable Armv8.9-A RCPC instructions for A64 and Advanced SIMD and floating-point instruction set
+// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
+// CHECK-NEXT: FEAT_LSE2 Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules
+// CHECK-NEXT: FEAT_MOPS Enable Armv8.8-A memcpy and memset acceleration instructions
+// CHECK-NEXT: FEAT_MPAM Enable Armv8.4-A Memory system Partitioning and Monitoring extension
+// CHECK-NEXT: FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension
+// CHECK-NEXT: FEAT_NMI, FEAT_GICv3_NMI Enable Armv8.8-A Non-maskable Interrupts
+// CHECK-NEXT: FEAT_NV, FEAT_NV2 Enable Armv8.4-A Nested Virtualization Enchancement
+// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
+// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
+// CHECK-NEXT: FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension
+// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
+// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
+// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
+// CHECK-NEXT: FEAT_SB Enable Armv8.5-A Speculation Barrier
+// CHECK-NEXT: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension
+// CHECK-NEXT: FEAT_SME Enable Scalable Matrix Extension (SME)
+// CHECK-NEXT: FEAT_SME2 Enable Scalable Matrix Extension 2 (SME2) instructions
+// CHECK-NEXT: FEAT_SPE Enable Statistical Profiling extension
+// CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions
+// CHECK-NEXT: FEAT_SPECRES2 Enable Speculation Restriction Instruction
+// CHECK-NEXT: FEAT_SPEv1p2 Enable extra register in the Statistical Profiling Extension
+// CHECK-NEXT: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit
+// CHECK-NEXT: FEAT_SVE Enable Scalable Vector Extension (SVE) instructions
+// CHECK-NEXT: FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions
+// CHECK-NEXT: FEAT_SVE_BitPerm Enable bit permutation SVE2 instructions
+// CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions
+// CHECK-NEXT: FEAT_TRBE Enable Trace Buffer Extension
+// CHECK-NEXT: FEAT_TRF Enable Armv8.4-A Trace extension
+// CHECK-NEXT: FEAT_UAO Enable Armv8.2-A UAO PState
+// CHECK-NEXT: FEAT_VHE Enable Armv8.1-A Virtual Host extension
+// CHECK-NEXT: FEAT_WFxT Enable Armv8.7-A WFET and WFIT instruction
+// CHECK-NEXT: FEAT_XS Enable Armv8.7-A limited-TLB-maintenance instruction
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-c1-pro.c b/clang/test/Driver/print-enabled-extensions/aarch64-c1-pro.c
new file mode 100644
index 0000000000000..d31a598463267
--- /dev/null
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-c1-pro.c
@@ -0,0 +1,71 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang --target=aarch64 --print-enabled-extensions -mcpu=c1-pro | FileCheck --strict-whitespace --implicit-check-not=FEAT_ %s
+
+// CHECK: Extensions enabled for the given AArch64 target
+// CHECK-EMPTY:
+// CHECK-NEXT: Architecture Feature(s) Description
+// CHECK-NEXT: FEAT_AMUv1 Enable Armv8.4-A Activity Monitors extension
+// CHECK-NEXT: FEAT_AMUv1p1 Enable Armv8.6-A Activity Monitors Virtualization support
+// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
+// CHECK-NEXT: FEAT_BF16 Enable BFloat16 Extension
+// CHECK-NEXT: FEAT_BTI Enable Branch Target Identification
+// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets
+// CHECK-NEXT: FEAT_CHK Enable Armv8.0-A Check Feature Status Extension
+// CHECK-NEXT: FEAT_CLRBHB Enable Clear BHB instruction
+// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
+// CHECK-NEXT: FEAT_CSV2_2 Enable architectural speculation restriction
+// CHECK-NEXT: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions
+// CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence
+// CHECK-NEXT: FEAT_DPB2 Enable Armv8.5-A Cache Clean to Point of Deep Persistence
+// CHECK-NEXT: FEAT_DotProd Enable dot product support
+// CHECK-NEXT: FEAT_ECV Enable enhanced counter virtualization extension
+// CHECK-NEXT: FEAT_ETE Enable Embedded Trace Extension
+// CHECK-NEXT: FEAT_FCMA Enable Armv8.3-A Floating-point complex number support
+// CHECK-NEXT: FEAT_FGT Enable fine grained virtualization traps extension
+// CHECK-NEXT: FEAT_FHM Enable FP16 FML instructions
+// CHECK-NEXT: FEAT_FP Enable Armv8.0-A Floating Point Extensions
+// CHECK-NEXT: FEAT_FP16 Enable half-precision floating-point data processing
+// CHECK-NEXT: FEAT_FPAC Enable Armv8.3-A Pointer Authentication Faulting enhancement
+// CHECK-NEXT: FEAT_FRINTTS Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int
+// CHECK-NEXT: FEAT_FlagM Enable Armv8.4-A Flag Manipulation instructions
+// CHECK-NEXT: FEAT_FlagM2 Enable alternative NZCV format for floating point comparisons
+// CHECK-NEXT: FEAT_HBC Enable Armv8.8-A Hinted Conditional Branches Extension
+// CHECK-NEXT: FEAT_HCX Enable Armv8.7-A HCRX_EL2 system register
+// CHECK-NEXT: FEAT_I8MM Enable Matrix Multiply Int8 Extension
+// CHECK-NEXT: FEAT_JSCVT Enable Armv8.3-A JavaScript FP conversion instructions
+// CHECK-NEXT: FEAT_LOR Enable Armv8.1-A Limited Ordering Regions extension
+// CHECK-NEXT: FEAT_LRCPC Enable support for RCPC extension
+// CHECK-NEXT: FEAT_LRCPC2 Enable Armv8.4-A RCPC instructions with Immediate Offsets
+// CHECK-NEXT: FEAT_LRCPC3 Enable Armv8.9-A RCPC instructions for A64 and Advanced SIMD and floating-point instruction set
+// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
+// CHECK-NEXT: FEAT_LSE2 Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules
+// CHECK-NEXT: FEAT_MOPS Enable Armv8.8-A memcpy and memset acceleration instructions
+// CHECK-NEXT: FEAT_MPAM Enable Armv8.4-A Memory system Partitioning and Monitoring extension
+// CHECK-NEXT: FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension
+// CHECK-NEXT: FEAT_NMI, FEAT_GICv3_NMI Enable Armv8.8-A Non-maskable Interrupts
+// CHECK-NEXT: FEAT_NV, FEAT_NV2 Enable Armv8.4-A Nested Virtualization Enchancement
+// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
+// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
+// CHECK-NEXT: FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension
+// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
+// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
+// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
+// CHECK-NEXT: FEAT_SB Enable Armv8.5-A Speculation Barrier
+// CHECK-NEXT: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension
+// CHECK-NEXT: FEAT_SME Enable Scalable Matrix Extension (SME)
+// CHECK-NEXT: FEAT_SME2 Enable Scalable Matrix Extension 2 (SME2) instructions
+// CHECK-NEXT: FEAT_SPE Enable Statistical Profiling extension
+// CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions
+// CHECK-NEXT: FEAT_SPECRES2 Enable Speculation Restriction Instruction
+// CHECK-NEXT: FEAT_SPEv1p2 Enable extra register in the Statistical Profiling Extension
+// CHECK-NEXT: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit
+// CHECK-NEXT: FEAT_SVE Enable Scalable Vector Extension (SVE) instructions
+// CHECK-NEXT: FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions
+// CHECK-NEXT: FEAT_SVE_BitPerm Enable bit permutation SVE2 instructions
+// CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions
+// CHECK-NEXT: FEAT_TRBE Enable Trace Buffer Extension
+// CHECK-NEXT: FEAT_TRF Enable Armv8.4-A Trace extension
+// CHECK-NEXT: FEAT_UAO Enable Armv8.2-A UAO PState
+// CHECK-NEXT: FEAT_VHE Enable Armv8.1-A Virtual Host extension
+// CHECK-NEXT: FEAT_WFxT Enable Armv8.7-A WFET and WFIT instruction
+// CHECK-NEXT: FEAT_XS Enable Armv8.7-A limited-TLB-maintenance instruction
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-c1-ultra.c b/clang/test/Driver/print-enabled-extensions/aarch64-c1-ultra.c
new file mode 100644
index 0000000000000..d3ab7d92eca92
--- /dev/null
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-c1-ultra.c
@@ -0,0 +1,71 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang --target=aarch64 --print-enabled-extensions -mcpu=c1-ultra | FileCheck --strict-whitespace --implicit-check-not=FEAT_ %s
+
+// CHECK: Extensions enabled for the given AArch64 target
+// CHECK-EMPTY:
+// CHECK-NEXT: Architecture Feature(s) Description
+// CHECK-NEXT: FEAT_AMUv1 Enable Armv8.4-A Activity Monitors extension
+// CHECK-NEXT: FEAT_AMUv1p1 Enable Armv8.6-A Activity Monitors Virtualization support
+// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
+// CHECK-NEXT: FEAT_BF16 Enable BFloat16 Extension
+// CHECK-NEXT: FEAT_BTI Enable Branch Target Identification
+// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets
+// CHECK-NEXT: FEAT_CHK Enable Armv8.0-A Check Feature Status Extension
+// CHECK-NEXT: FEAT_CLRBHB Enable Clear BHB instruction
+// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
+// CHECK-NEXT: FEAT_CSV2_2 Enable architectural speculation restriction
+// CHECK-NEXT: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions
+// CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence
+// CHECK-NEXT: FEAT_DPB2 Enable Armv8.5-A Cache Clean to Point of Deep Persistence
+// CHECK-NEXT: FEAT_DotProd Enable dot product support
+// CHECK-NEXT: FEAT_ECV Enable enhanced counter virtualization extension
+// CHECK-NEXT: FEAT_ETE Enable Embedded Trace Extension
+// CHECK-NEXT: FEAT_FCMA Enable Armv8.3-A Floating-point complex number support
+// CHECK-NEXT: FEAT_FGT Enable fine grained virtualization traps extension
+// CHECK-NEXT: FEAT_FHM Enable FP16 FML instructions
+// CHECK-NEXT: FEAT_FP Enable Armv8.0-A Floating Point Extensions
+// CHECK-NEXT: FEAT_FP16 Enable half-precision floating-point data processing
+// CHECK-NEXT: FEAT_FPAC Enable Armv8.3-A Pointer Authentication Faulting enhancement
+// CHECK-NEXT: FEAT_FRINTTS Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int
+// CHECK-NEXT: FEAT_FlagM Enable Armv8.4-A Flag Manipulation instructions
+// CHECK-NEXT: FEAT_FlagM2 Enable alternative NZCV format for floating point comparisons
+// CHECK-NEXT: FEAT_HBC Enable Armv8.8-A Hinted Conditional Branches Extension
+// CHECK-NEXT: FEAT_HCX Enable Armv8.7-A HCRX_EL2 system register
+// CHECK-NEXT: FEAT_I8MM Enable Matrix Multiply Int8 Extension
+// CHECK-NEXT: FEAT_JSCVT Enable Armv8.3-A JavaScript FP conversion instructions
+// CHECK-NEXT: FEAT_LOR Enable Armv8.1-A Limited Ordering Regions extension
+// CHECK-NEXT: FEAT_LRCPC Enable support for RCPC extension
+// CHECK-NEXT: FEAT_LRCPC2 Enable Armv8.4-A RCPC instructions with Immediate Offsets
+// CHECK-NEXT: FEAT_LRCPC3 Enable Armv8.9-A RCPC instructions for A64 and Advanced SIMD and floating-point instruction set
+// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
+// CHECK-NEXT: FEAT_LSE2 Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules
+// CHECK-NEXT: FEAT_MOPS Enable Armv8.8-A memcpy and memset acceleration instructions
+// CHECK-NEXT: FEAT_MPAM Enable Armv8.4-A Memory system Partitioning and Monitoring extension
+// CHECK-NEXT: FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension
+// CHECK-NEXT: FEAT_NMI, FEAT_GICv3_NMI Enable Armv8.8-A Non-maskable Interrupts
+// CHECK-NEXT: FEAT_NV, FEAT_NV2 Enable Armv8.4-A Nested Virtualization Enchancement
+// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
+// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
+// CHECK-NEXT: FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension
+// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
+// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
+// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
+// CHECK-NEXT: FEAT_SB Enable Armv8.5-A Speculation Barrier
+// CHECK-NEXT: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension
+// CHECK-NEXT: FEAT_SME Enable Scalable Matrix Extension (SME)
+// CHECK-NEXT: FEAT_SME2 Enable Scalable Matrix Extension 2 (SME2) instructions
+// CHECK-NEXT: FEAT_SPE Enable Statistical Profiling extension
+// CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions
+// CHECK-NEXT: FEAT_SPECRES2 Enable Speculation Restriction Instruction
+// CHECK-NEXT: FEAT_SPEv1p2 Enable extra register in the Statistical Profiling Extension
+// CHECK-NEXT: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit
+// CHECK-NEXT: FEAT_SVE Enable Scalable Vector Extension (SVE) instructions
+// CHECK-NEXT: FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions
+// CHECK-NEXT: FEAT_SVE_BitPerm Enable bit permutation SVE2 instructions
+// CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions
+// CHECK-NEXT: FEAT_TRBE Enable Trace Buffer Extension
+// CHECK-NEXT: FEAT_TRF Enable Armv8.4-A Trace extension
+// CHECK-NEXT: FEAT_UAO Enable Armv8.2-A UAO PState
+// CHECK-NEXT: FEAT_VHE Enable Armv8.1-A Virtual Host extension
+// CHECK-NEXT: FEAT_WFxT Enable Armv8.7-A WFET and WFIT instruction
+// CHECK-NEXT: FEAT_XS Enable Armv8.7-A limited-TLB-maintenance instruction
diff --git a/clang/test/Misc/target-invalid-cpu-note/aarch64.c b/clang/test/Misc/target-invalid-cpu-note/aarch64.c
index 0346ab2bb6b13..1720579c9c774 100644
--- a/clang/test/Misc/target-invalid-cpu-note/aarch64.c
+++ b/clang/test/Misc/target-invalid-cpu-note/aarch64.c
@@ -34,6 +34,10 @@
// CHECK-SAME: {{^}}, apple-s7
// CHECK-SAME: {{^}}, apple-s8
// CHECK-SAME: {{^}}, apple-s9
+// CHECK-SAME: {{^}}, c1-nano
+// CHECK-SAME: {{^}}, c1-premium
+// CHECK-SAME: {{^}}, c1-pro
+// CHECK-SAME: {{^}}, c1-ultra
// CHECK-SAME: {{^}}, carmel
// CHECK-SAME: {{^}}, cobalt-100
// CHECK-SAME: {{^}}, cortex-a320
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 22d5b4183fac0..2decbb7a1ab39 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -111,6 +111,8 @@ Changes to the AArch64 Backend
* `FEAT_TME` support has been removed, as it has been withdrawn from
all future versions of the A-profile architecture.
+* Added support for C1-Nano, C1-Pro, C1-Premium, and C1-Ultra CPUs.
+
Changes to the AMDGPU Backend
-----------------------------
diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td
index 120415f91c9ae..59a1b780e8145 100644
--- a/llvm/lib/Target/AArch64/AArch64Processors.td
+++ b/llvm/lib/Target/AArch64/AArch64Processors.td
@@ -669,6 +669,48 @@ def TuneNeoverseV3AE : SubtargetFeature<"neoversev3AE", "ARMProcFamily", "Neover
FeatureAvoidLDAPUR,
FeaturePredictableSelectIsExpensive]>;
+def TuneC1Nano : SubtargetFeature<"c1-nano", "ARMProcFamily",
+ "C1Nano", "C1-Nano ARM Processors",[
+ FeatureFuseAES,
+ FeatureFuseAdrpAdd,
+ FeaturePostRAScheduler,
+ FeatureUseWzrToVecMove,
+ FeatureUseFixedOverScalableIfEqualCost]>;
+
+def TuneC1Pro : SubtargetFeature<"c1-pro", "ARMProcFamily",
+ "C1Pro", "C1-Pro ARM Processors",[
+ FeatureFuseAES,
+ FeaturePostRAScheduler,
+ FeatureCmpBccFusion,
+ FeatureALULSLFast,
+ FeatureFuseAdrpAdd,
+ FeatureFuseCmpCSel,
+ FeatureFuseCmpCSet,
+ FeatureEnableSelectOptimize,
+ FeaturePredictableSelectIsExpensive]>;
+
+def TuneC1Premium : SubtargetFeature<"c1-premium", "ARMProcFamily",
+ "C1Premium", "C1-Premium ARM Processors",[
+ FeatureALULSLFast,
+ FeatureFuseAdrpAdd,
+ FeatureFuseAES,
+ FeaturePostRAScheduler,
+ FeatureEnableSelectOptimize,
+ FeaturePredictableSelectIsExpensive]>;
+
+def TuneC1Ultra : SubtargetFeature<"c1-ultra", "ARMProcFamily",
+ "C1Ultra", "C1-Ultra ARM Processors",[
+ FeatureALULSLFast,
+ FeatureFuseAdrpAdd,
+ FeatureFuseCmpCSel,
+ FeatureFuseCmpCSet,
+ FeatureFuseAES,
+ FeaturePostRAScheduler,
+ FeatureEnableSelectOptimize,
+ FeatureUseFixedOverScalableIfEqualCost,
+ FeatureAvoidLDAPUR,
+ FeaturePredictableSelectIsExpensive]>;
+
def TuneSaphira : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira",
"Qualcomm Saphira processors", [
FeaturePostRAScheduler,
@@ -1139,6 +1181,63 @@ def ProcessorFeatures {
FeatureDotProd, FeatureFPARMv8, FeatureMatMulInt8, FeatureJS,
FeatureLSE, FeatureNEON, FeatureRAS, FeatureRCPC, FeatureRDM,
FeatureRME, FeatureFPAC];
+ list<SubtargetFeature> C1Nano = [HasV9_3aOps, FeatureNEON, FeatureCLRBHB,
+ FeatureCHK, FeatureFPARMv8, FeaturePerfMon,
+ FeatureSPECRES2, FeatureSSBS, FeatureRDM,
+ FeatureVH, FeatureBF16, FeatureDotProd,
+ FeatureFP16FML, FeatureFullFP16, FeatureMPAM,
+ FeatureSVE, FeatureCCIDX, FeatureComplxNum,
+ FeatureFPAC, FeatureJS, FeatureAM,
+ FeatureRAS, FeatureSEL2, FeatureTRACEV8_4,
+ FeatureAltFPCmp, FeatureFRInt3264,
+ FeatureMTE, FeatureFineGrainedTraps,
+ FeatureHCX, FeatureRCPC3, FeatureETE,
+ FeatureSVEBitPerm, FeatureSVE2, FeatureTRBE,
+ FeatureSME, FeatureSME2];
+ list<SubtargetFeature> C1Pro = [HasV9_3aOps, FeatureNEON, FeatureCLRBHB,
+ FeatureCHK, FeatureFPARMv8, FeaturePerfMon,
+ FeatureSPECRES2, FeatureSSBS, FeatureRDM,
+ FeatureVH, FeatureBF16, FeatureDotProd,
+ FeatureFP16FML, FeatureFullFP16, FeatureMPAM,
+ FeatureSPE, FeatureSVE, FeatureCCIDX,
+ FeatureComplxNum, FeatureFPAC, FeatureJS,
+ FeatureAM, FeatureRAS, FeatureSEL2,
+ FeatureTRACEV8_4, FeatureAltFPCmp,
+ FeatureFRInt3264, FeatureMTE,
+ FeatureFineGrainedTraps, FeatureHCX,
+ FeatureSPE_EEF, FeatureRCPC3, FeatureETE,
+ FeatureSVEBitPerm, FeatureSVE2, FeatureTRBE,
+ FeatureSME, FeatureSME2];
+ list<SubtargetFeature> C1Premium = [HasV9_3aOps, FeatureNEON, FeatureCLRBHB,
+ FeatureCHK, FeatureFPARMv8,
+ FeaturePerfMon, FeatureSPECRES2,
+ FeatureSSBS, FeatureRDM, FeatureVH,
+ FeatureBF16, FeatureDotProd,
+ FeatureFP16FML, FeatureFullFP16,
+ FeatureMPAM, FeatureSPE, FeatureSVE,
+ FeatureCCIDX, FeatureComplxNum,
+ FeatureFPAC, FeatureJS, FeatureAM,
+ FeatureRAS, FeatureSEL2, FeatureTRACEV8_4,
+ FeatureAltFPCmp, FeatureFRInt3264,
+ FeatureMTE, FeatureFineGrainedTraps,
+ FeatureHCX, FeatureSPE_EEF, FeatureRCPC3,
+ FeatureETE, FeatureSVEBitPerm,
+ FeatureSVE2, FeatureTRBE, FeatureSME,
+ FeatureSME2];
+ list<SubtargetFeature> C1Ultra = [HasV9_3aOps, FeatureNEON, FeatureCLRBHB,
+ FeatureCHK, FeatureFPARMv8, FeaturePerfMon,
+ FeatureSPECRES2, FeatureSSBS, FeatureRDM,
+ FeatureVH, FeatureBF16, FeatureDotProd,
+ FeatureFP16FML, FeatureFullFP16,
+ FeatureMPAM, FeatureSPE, FeatureSVE,
+ FeatureCCIDX, FeatureComplxNum, FeatureFPAC,
+ FeatureJS, FeatureAM, FeatureRAS,
+ FeatureSEL2, FeatureTRACEV8_4,
+ FeatureAltFPCmp, FeatureFRInt3264,
+ FeatureMTE, FeatureFineGrainedTraps,
+ FeatureHCX, FeatureSPE_EEF, FeatureRCPC3,
+ FeatureETE, FeatureSVEBitPerm, FeatureSVE2,
+ FeatureTRBE, FeatureSME, FeatureSME2];
list<SubtargetFeature> Saphira = [HasV8_4aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
FeatureNEON, FeatureSPE, FeaturePerfMon, FeatureCRC,
FeatureCCIDX,
@@ -1301,6 +1400,14 @@ def : ProcessorModel<"neoverse-v3", NeoverseV3Model,
ProcessorFeatures.NeoverseV3, [TuneNeoverseV3]>;
def : ProcessorModel<"neoverse-v3ae", NeoverseV3AEModel,
ProcessorFeatures.NeoverseV3AE, [TuneNeoverseV3AE]>;
+def : ProcessorModel<"c1-nano", CortexA510Model,
+ ProcessorFeatures.C1Nano, [TuneC1Nano]>;
+def : ProcessorModel<"c1-pro", NeoverseN2Model,
+ ProcessorFeatures.C1Pro, [TuneC1Pro]>;
+def : ProcessorModel<"c1-premium", NeoverseV3Model,
+ ProcessorFeatures.C1Premium, [TuneC1Premium]>;
+def : ProcessorModel<"c1-ultra", NeoverseV3Model,
+ ProcessorFeatures.C1Ultra, [TuneC1Ultra]>;
def : ProcessorModel<"exynos-m3", ExynosM3Model, ProcessorFeatures.ExynosM3,
[TuneExynosM3]>;
def : ProcessorModel<"exynos-m4", ExynosM4Model, ProcessorFeatures.ExynosM4,
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
index dae4f6a82e3aa..347fdccde365a 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
@@ -177,6 +177,7 @@ void AArch64Subtarget::initializeProperties(bool HasMinSize) {
case CortexA320:
case CortexA510:
case CortexA520:
+ case C1Nano:
PrefFunctionAlignment = Align(16);
VScaleForTuning = 1;
PrefLoopAlignment = Align(16);
@@ -190,6 +191,9 @@ void AArch64Subtarget::initializeProperties(bool HasMinSize) {
case CortexX3:
case CortexX4:
case CortexX925:
+ case C1Premium:
+ case C1Pro:
+ case C1Ultra:
PrefFunctionAlignment = Align(16);
VScaleForTuning = 1;
PrefLoopAlignment = Align(32);
diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp
index cb793d60a286f..6735e572f6d82 100644
--- a/llvm/lib/TargetParser/Host.cpp
+++ b/llvm/lib/TargetParser/Host.cpp
@@ -203,6 +203,10 @@ getHostCPUNameForARMFromComponents(StringRef Implementer, StringRef Hardware,
.Case("0xb36", "arm1136j-s")
.Case("0xb56", "arm1156t2-s")
.Case("0xb76", "arm1176jz-s")
+ .Case("0xd8a", "c1-nano")
+ .Case("0xd90", "c1-premium")
+ .Case("0xd8b", "c1-pro")
+ .Case("0xd8c", "c1-ultra")
.Case("0xc05", "cortex-a5")
.Case("0xc07", "cortex-a7")
.Case("0xc08", "cortex-a8")
diff --git a/llvm/unittests/TargetParser/Host.cpp b/llvm/unittests/TargetParser/Host.cpp
index be8548ebf8551..db88f4fa95f52 100644
--- a/llvm/unittests/TargetParser/Host.cpp
+++ b/llvm/unittests/TargetParser/Host.cpp
@@ -148,6 +148,18 @@ TEST(getLinuxHostCPUName, AArch64) {
EXPECT_EQ(sys::detail::getHostCPUNameForARM(
0x4100d870, ArrayRef<uint64_t>{0x4100d870, 0x4100d850}),
"cortex-x925");
+ EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
+ "CPU part : 0xd8a"),
+ "c1-nano");
+ EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
+ "CPU part : 0xd90"),
+ "c1-premium");
+ EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
+ "CPU part : 0xd8b"),
+ "c1-pro");
+ EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
+ "CPU part : 0xd8c"),
+ "c1-ultra");
EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x51\n"
"CPU part : 0xc00"),
"falkor");
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index 92e2d77816cc7..594e913248bd1 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1120,6 +1120,10 @@ INSTANTIATE_TEST_SUITE_P(
AArch64CPUTestParams("cortex-x3", "armv9-a"),
AArch64CPUTestParams("cortex-x4", "armv9.2-a"),
AArch64CPUTestParams("cortex-x925", "armv9.2-a"),
+ AArch64CPUTestParams("c1-nano", "armv9.3-a"),
+ AArch64CPUTestParams("c1-premium", "armv9.3-a"),
+ AArch64CPUTestParams("c1-pro", "armv9.3-a"),
+ AArch64CPUTestParams("c1-ultra", "armv9.3-a"),
AArch64CPUTestParams("cyclone", "armv8-a"),
AArch64CPUTestParams("apple-a7", "armv8-a"),
AArch64CPUTestParams("apple-a8", "armv8-a"),
@@ -1264,7 +1268,7 @@ INSTANTIATE_TEST_SUITE_P(
AArch64CPUAliasTestParams::PrintToStringParamName);
// Note: number of CPUs includes aliases.
-static constexpr unsigned NumAArch64CPUArchs = 91;
+static constexpr unsigned NumAArch64CPUArchs = 95;
TEST(TargetParserTest, testAArch64CPUArchList) {
SmallVector<StringRef, NumAArch64CPUArchs> List;
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