[llvm] [IR] Split vector.splice into vector.splice.down and vector.splice.up (PR #170796)

[Luke Lau via llvm-commits]

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@@ -12891,20 +12892,22 @@ void SelectionDAGBuilder::visitVectorSplice(const CallInst &I) {
   SDLoc DL = getCurSDLoc();
   SDValue V1 = getValue(I.getOperand(0));
   SDValue V2 = getValue(I.getOperand(1));
-  int64_t Imm = cast<ConstantInt>(I.getOperand(2))->getSExtValue();
+  uint64_t Imm = cast<ConstantInt>(I.getOperand(2))->getSExtValue();
+  const bool IsDown = I.getIntrinsicID() == Intrinsic::vector_splice_down;
 
   // VECTOR_SHUFFLE doesn't support a scalable mask so use a dedicated node.
   if (VT.isScalableVector()) {
-    setValue(
-        &I, DAG.getNode(ISD::VECTOR_SPLICE, DL, VT, V1, V2,
-                        DAG.getSignedConstant(
-                            Imm, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))));
+    setValue(&I, DAG.getNode(
+                     IsDown ? ISD::VECTOR_SPLICE_DOWN : ISD::VECTOR_SPLICE_UP,
+                     DL, VT, V1, V2,
+                     DAG.getConstant(Imm, DL,
+                                     TLI.getVectorIdxTy(DAG.getDataLayout()))));
     return;
   }
 
   unsigned NumElts = VT.getVectorNumElements();
 
-  uint64_t Idx = (NumElts + Imm) % NumElts;
+  uint64_t Idx = (NumElts + (IsDown ? Imm : -Imm)) % NumElts;
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lukel97 wrote:

I've restored the previous restriction on VL in bca832b14442607550addf0ec5d753af740c527a so that immediate shouldn't be allowed now.

https://github.com/llvm/llvm-project/pull/170796