[llvm] [AMDGPU] Verify dominance when rewriting spills to registers (PR #167347)

[Austin Kerbow via llvm-commits]

kerbowa wrote:

I spent more time today trying to build a small reproducer, both in IR and MIR, and ran into some practical problems.

MIR test:
The bug only manifests after greedy RA where analyses aren’t serialized to MIR, and this pass runs between RA and the register rewriter. I tried experiments with manually inserted spills and `-start-before=greedy`, but without the real RA + LiveStacks state, the pass never sees the original failure.

IR test:
At the IR level, it’s extremely hard to force. It needs a particular value to spill to a VGPR stack slot (and not AGPR/AV),
with spills/reloads placed in exactly the right basic blocks, and with the poisoning/control‑flow structure that breaks the dominance assumption. Small changes to either avoid the spill entirely or move it enough that the joint-dominance corner case disappears. My original large reproducer already stopped triggering the issue for this reason.

Because of this I added a unit test instead.

Thanks @ruiling for your comment about joint dominance not being necessary for memory store/load. I'll look into reworking the patch to add an implicit_def on any path without a store.

https://github.com/llvm/llvm-project/pull/167347