[llvm] [RISCV] LMUL lists for indexed and strided loads (PR #169756)

[Min-Yih Hsu via llvm-commits]

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@@ -582,10 +582,8 @@ multiclass SiFive7WriteResBase<int VLEN,
       defm : LMULWriteResMX<"WriteVSTOX8", [VCQ, VS], mx, IsWorstCase>;
     }
   }
-  // TODO: The MxLists need to be filtered by EEW. We only need to support
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mshockwave wrote:

I think this comment might be outdated already: the fact that it excludes MF8 means that it already accounts for EEW, as explained by the comment itself. 

https://github.com/llvm/llvm-project/pull/169756