[llvm] [AArch64][GlobalISel] SIMD fpcvt codegen for rounding nodes (PR #165546)

[via llvm-commits]

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@@ -6805,6 +6805,83 @@ defm : FPToIntegerPats<fp_to_uint, fp_to_uint_sat, fp_to_uint_sat_gi, ftrunc, "F
 defm : FPToIntegerPats<fp_to_sint, fp_to_sint_sat, fp_to_sint_sat_gi, fround, "FCVTAS">;
 defm : FPToIntegerPats<fp_to_uint, fp_to_uint_sat, fp_to_uint_sat_gi, fround, "FCVTAU">;
 
+// For global-isel we can use register classes to determine
+// which FCVT instruction to use.
+let Predicates = [HasFPRCVT] in {
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CarolineConcatto wrote:

I am not sure if it will help, but maybe we could split the PR into patterns only for GlobalISel and another for the standard lowering/SelectionDAG?
I imagine that the ones from lines:
 6810 till 6823
and 
6848 till 6861 
are only for GlobalISel while the other ones are for SelectionDAG

https://github.com/llvm/llvm-project/pull/165546