[llvm] [WoA] Remove extra barriers after ARM LSE instructions with MSVC (PR #169596)

[John Brawn via llvm-commits]

john-brawn-arm wrote:

Trying some stuff using https://developer.arm.com/herd7 it looks not having DMB after LDADDL is correct. Trying the following example (based on what my comment in https://reviews.llvm.org/D141748)
```
AArch64 SeqCst
{
0:X1=x; 1:X1=x; 2:X1=x;
0:X3=y; 1:X3=y; 2:X3=y;
}
 P0                   | P1            | P2 ;
 MOV W0, #1           | MOV W2, #1    | LDAR W2, [X3] ;
 LDADDAL W0, W2, [X1] | STLR W2, [X3] | LDAR W0, [X1] ;
 LDR W2, [X3]         | LDAR W0, [X1] | ;
 DMB ISH              |               | ;
exists(2:X2=1 /\ 2:X0=0 /\ 0:X2=0 /\ 1:X0=1)
```
gives the answer "No", meaning it's not possible for sequential consistency to be violated. By comparison, using LDADDL (i.e. no acquire) gives an answer of "Ok" meaning in that case it is possible for sequential consistency to be violated (and DMB after it fixes that). 

https://github.com/llvm/llvm-project/pull/169596