[llvm] [AArch64] Improve select dagcombine (PR #169925)

[Sander de Smalen via llvm-commits]

================
@@ -26965,6 +26965,11 @@ static SDValue performSelectCombine(SDNode *N,
   if (!ResVT.isVector() || NumMaskElts == 0)
     return SDValue();
 
+  // Avoid creating vectors with excessive VFs for small types.
+  if (DCI.isBeforeLegalize() &&
+      SrcVT.getSizeInBits() < ResVT.getScalarSizeInBits())
----------------
sdesmalen-arm wrote:

I would think we always want to use `NumMaskElts` before type legalisation, that would also improve e.g. 

```
define <32 x i8> @any_of_select_vf8(<32 x i8> %mask, <32 x i8> %a, <32 x i8> %b) {
  %cmp = icmp slt <32 x i8> %mask, zeroinitializer                                
  %cmp.bc = bitcast <32 x i1> %cmp to i32                                         
  %cmp.bc.not = icmp eq i32 %cmp.bc, 0                                            
  %res = select i1 %cmp.bc.not, <32 x i8> %a, <32 x i8> %b                        
  ret <32 x i8> %res                                                              
}                                                                                 
```

https://github.com/llvm/llvm-project/pull/169925